Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
48 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
51 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
54 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
56 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
58 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
63 struct ixgbe_mac_info *mac = &hw->mac;
71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
72 !ixgbe_mng_enabled(hw)) {
73 mac->ops.disable_tx_laser =
75 mac->ops.enable_tx_laser =
77 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL;
85 if (hw->phy.multispeed_fiber) {
87 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
88 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
89 mac->ops.set_rate_select_speed =
91 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
92 mac->ops.set_rate_select_speed =
95 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
96 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
97 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
98 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
99 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
101 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
107 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
108 * @hw: pointer to hardware structure
115 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
117 struct ixgbe_mac_info *mac = &hw->mac;
118 struct ixgbe_phy_info *phy = &hw->phy;
124 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
126 hw->phy.qsfp_shared_i2c_bus = true;
129 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
135 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
136 IXGBE_WRITE_FLUSH(hw);
138 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
139 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
142 ret_val = phy->ops.identify(hw);
147 ixgbe_init_mac_link_ops_82599(hw);
148 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
149 hw->phy.ops.reset = NULL;
152 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
153 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
154 mac->ops.get_link_capabilities =
159 switch (hw->phy.type) {
161 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
162 phy->ops.check_link = ixgbe_check_phy_link_tnx;
163 phy->ops.get_firmware_version =
173 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
180 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
181 ixgbe_init_mac_link_ops_82599(hw);
183 hw->phy.ops.reset = NULL;
185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
191 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
198 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
201 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
202 IXGBE_WRITE_FLUSH(hw);
203 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
208 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
212 msec_delay(hw->eeprom.semaphore_delay);
215 ret_val = hw->mac.ops.prot_autoc_write(hw,
216 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
232 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
234 msec_delay(hw->eeprom.semaphore_delay);
241 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
242 * @hw: pointer to hardware structure
246 * For this part (82599) we need to wrap read-modify-writes with a possible
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
256 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
257 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
270 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
271 * @hw: pointer to hardware structure
279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
284 if (ixgbe_check_reset_blocked(hw))
288 * - We didn't do it already (in the read part of a read-modify-write)
289 * - LESM is enabled.
291 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
292 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
301 ret_val = ixgbe_reset_pipeline_82599(hw);
308 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
314 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
315 * @hw: pointer to hardware structure
321 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
323 struct ixgbe_mac_info *mac = &hw->mac;
324 struct ixgbe_phy_info *phy = &hw->phy;
325 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
331 ixgbe_init_phy_ops_generic(hw);
332 ret_val = ixgbe_init_ops_generic(hw);
335 phy->ops.identify = ixgbe_identify_phy_82599;
336 phy->ops.init = ixgbe_init_phy_ops_82599;
339 mac->ops.reset_hw = ixgbe_reset_hw_82599;
340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
341 mac->ops.get_media_type = ixgbe_get_media_type_82599;
342 mac->ops.get_supported_physical_layer =
344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
349 mac->ops.start_hw = ixgbe_start_hw_82599;
350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
355 mac->ops.prot_autoc_read = prot_autoc_read_82599;
356 mac->ops.prot_autoc_write = prot_autoc_write_82599;
359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
363 mac->rar_highwater = 1;
364 mac->ops.set_vfta = ixgbe_set_vfta_generic;
365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
374 mac->ops.check_link = ixgbe_check_mac_link_generic;
375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
376 ixgbe_init_mac_link_ops_82599(hw);
378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
390 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf;
393 eeprom->ops.read = ixgbe_read_eeprom_82599;
394 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
397 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
399 mac->ops.get_thermal_sensor_data =
401 mac->ops.init_thermal_sensor_thresh =
404 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
405 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
406 mac->ops.bypass_set = ixgbe_bypass_set_generic;
407 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
409 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
415 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
416 * @hw: pointer to hardware structure
422 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
433 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
434 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
436 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
438 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
444 if (hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core0 ||
445 hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core1) {
449 if (hw->phy.multispeed_fiber)
460 if (hw->mac.orig_link_settings_stored)
461 autoc = hw->mac.orig_autoc;
463 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
520 if (hw->phy.multispeed_fiber) {
524 /* QSFP must not enable full auto-negotiation
527 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
538 * ixgbe_get_media_type_82599 - Get media type
539 * @hw: pointer to hardware structure
543 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
550 switch (hw->phy.type) {
559 switch (hw->device_id) {
591 hw->phy.multispeed_fiber = true;
602 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
603 * @hw: pointer to hardware structure
608 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
614 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
616 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
618 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
620 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
625 * ixgbe_start_mac_link_82599 - Setup MAC link settings
626 * @hw: pointer to hardware structure
632 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
647 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
648 status = hw->mac.ops.acquire_swfw_sync(hw,
657 ixgbe_reset_pipeline_82599(hw);
660 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
664 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
673 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
693 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
694 * @hw: pointer to hardware structure
700 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
702 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
705 if (ixgbe_check_reset_blocked(hw))
710 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
711 IXGBE_WRITE_FLUSH(hw);
716 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
717 * @hw: pointer to hardware structure
723 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
725 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
729 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
730 IXGBE_WRITE_FLUSH(hw);
735 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
736 * @hw: pointer to hardware structure
741 * so, we set the speed then disable and re-enable the Tx laser, to
746 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
751 if (ixgbe_check_reset_blocked(hw))
754 if (hw->mac.autotry_restart) {
755 ixgbe_disable_tx_laser_multispeed_fiber(hw);
756 ixgbe_enable_tx_laser_multispeed_fiber(hw);
757 hw->mac.autotry_restart = false;
762 * ixgbe_set_hard_rate_select_speed - Set module link speed
763 * @hw: pointer to hardware structure
768 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
771 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
786 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
787 IXGBE_WRITE_FLUSH(hw);
791 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
792 * @hw: pointer to hardware structure
798 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
806 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
811 hw->phy.autoneg_advertised = 0;
814 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
817 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
820 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
830 hw->phy.smart_speed_active = false;
832 status = ixgbe_setup_mac_link_82599(hw, speed,
847 status = ixgbe_check_link(hw, &link_speed, &link_up,
866 hw->phy.smart_speed_active = true;
867 status = ixgbe_setup_mac_link_82599(hw, speed,
876 * connect attempts as defined in the AN MAS table 73-7.
882 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
891 hw->phy.smart_speed_active = false;
892 status = ixgbe_setup_mac_link_82599(hw, speed,
903 * ixgbe_setup_mac_link_82599 - Set MAC link speed
904 * @hw: pointer to hardware structure
910 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
917 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
920 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
929 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
941 if (hw->mac.orig_link_settings_stored)
942 orig_autoc = hw->mac.orig_autoc;
958 (hw->phy.smart_speed_active == false))
978 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
987 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
999 IXGBE_READ_REG(hw, IXGBE_LINKS);
1021 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1022 * @hw: pointer to hardware structure
1028 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1037 status = hw->phy.ops.setup_link_speed(hw, speed,
1040 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1046 * ixgbe_reset_hw_82599 - Perform hardware reset
1047 * @hw: pointer to hardware structure
1053 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1057 u32 ctrl = 0;
1065 status = hw->mac.ops.stop_adapter(hw);
1070 ixgbe_clear_tx_pending(hw);
1075 status = hw->phy.ops.init(hw);
1081 if (hw->phy.sfp_setup_needed) {
1082 status = hw->mac.ops.setup_sfp(hw);
1083 hw->phy.sfp_setup_needed = false;
1090 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1091 hw->phy.ops.reset(hw);
1094 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1103 ctrl = IXGBE_CTRL_LNK_RST;
1104 if (!hw->force_full_reset) {
1105 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1107 ctrl = IXGBE_CTRL_RST;
1110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1112 IXGBE_WRITE_FLUSH(hw);
1114 /* Poll for reset bit to self-clear meaning reset is complete */
1117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1118 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1122 if (ctrl & IXGBE_CTRL_RST_MASK) {
1132 * allow time for any pending HW events to complete.
1134 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1135 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1144 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1145 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1150 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1151 IXGBE_WRITE_FLUSH(hw);
1154 if (hw->mac.orig_link_settings_stored == false) {
1155 hw->mac.orig_autoc = autoc;
1156 hw->mac.orig_autoc2 = autoc2;
1157 hw->mac.orig_link_settings_stored = true;
1160 /* If MNG FW is running on a multi-speed device that
1166 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1167 hw->wol_enabled)
1168 hw->mac.orig_autoc =
1169 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1172 if (autoc != hw->mac.orig_autoc) {
1173 status = hw->mac.ops.prot_autoc_write(hw,
1174 hw->mac.orig_autoc,
1181 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1183 autoc2 |= (hw->mac.orig_autoc2 &
1185 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1190 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1197 hw->mac.num_rar_entries = 128;
1198 hw->mac.ops.init_rx_addrs(hw);
1201 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1204 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1206 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1208 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1209 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1212 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1216 hw->mac.num_rar_entries--;
1220 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1221 &hw->mac.wwpn_prefix);
1228 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1229 * @hw: pointer to hardware structure
1232 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1237 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1247 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1248 * @hw: pointer to hardware structure
1250 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1254 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1264 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1266 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1270 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1271 IXGBE_WRITE_FLUSH(hw);
1273 * 82599 adapters flow director init flow cannot be restarted,
1275 * before re-writing the FDIRCTRL control register with the same value.
1276 * - write 1 to bit 8 of FDIRCMD register &
1277 * - write 0 to bit 8 of FDIRCMD register
1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1280 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1282 IXGBE_WRITE_FLUSH(hw);
1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1284 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1286 IXGBE_WRITE_FLUSH(hw);
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1292 IXGBE_WRITE_FLUSH(hw);
1294 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1295 IXGBE_WRITE_FLUSH(hw);
1297 /* Poll init-done after we write FDIRCTRL register */
1299 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1305 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1310 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1311 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1312 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1313 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1314 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1320 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1321 * @hw: pointer to hardware structure
1322 * @fdirctrl: value to write to flow director control register
1324 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1331 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1332 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1335 * Poll init-done after we write the register. Estimated times:
1347 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1348 IXGBE_WRITE_FLUSH(hw);
1350 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1357 DEBUGOUT("Flow Director poll time exceeded!\n");
1361 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1362 * @hw: pointer to hardware structure
1363 * @fdirctrl: value to write to flow director control register, initially
1366 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1372 * Move the flexible bytes to use the ethertype - shift 6 words
1381 ixgbe_fdir_enable_82599(hw, fdirctrl);
1387 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1388 * @hw: pointer to hardware structure
1389 * @fdirctrl: value to write to flow director control register, initially
1391 * @cloud_mode: true - cloud mode, false - other mode
1393 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1404 * Move the flexible bytes to use the ethertype - shift 6 words
1420 ixgbe_fdir_enable_82599(hw, fdirctrl);
1426 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1427 * @hw: pointer to hardware structure
1430 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1436 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1441 if ((hw->mac.type == ixgbe_mac_X550) ||
1442 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1443 (hw->mac.type == ixgbe_mac_X550EM_a))
1446 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1447 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1449 IXGBE_WRITE_FLUSH(hw);
1450 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1451 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1453 IXGBE_WRITE_FLUSH(hw);
1456 ixgbe_fdir_enable_82599(hw, fdirctrl);
1474 sig_hash ^= lo_hash_dword << (16 - n); \
1480 sig_hash ^= hi_hash_dword << (16 - n); \
1484 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1509 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1516 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1551 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1552 * @hw: pointer to hardware structure
1560 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1579 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1589 DEBUGOUT(" Error on flow type input\n");
1602 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1603 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1607 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1624 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1645 input->dword_stream[i] &= input_mask->dword_stream[i];
1648 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1652 hi_dword ^= input->dword_stream[i];
1658 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1665 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1679 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1683 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1686 * The source and destination port masks for flow director are bit swapped
1693 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1695 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port);
1704 * that are either all or in part big-endian. As a result on big-endian
1705 * systems we will end up byte swapping the value to little-endian before
1707 * big-endian format.
1719 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1740 if (input_mask->formatted.bkt_hash)
1744 switch (input_mask->formatted.vm_pool & 0x7F) {
1754 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1757 if (input_mask->formatted.dst_port ||
1758 input_mask->formatted.src_port) {
1765 DEBUGOUT(" Error on flow type mask\n");
1769 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1792 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1809 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1820 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1835 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1845 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1851 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1852 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1853 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1854 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1855 switch (hw->mac.type) {
1859 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1866 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1867 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1875 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1876 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1878 switch (hw->mac.type) {
1882 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1888 /* store source and destination IP masks (big-enian) */
1889 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1890 ~input_mask->formatted.src_ip[0]);
1891 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1892 ~input_mask->formatted.dst_ip[0]);
1893 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF);
1898 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1911 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1912 input->formatted.src_ip[0]);
1913 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1914 input->formatted.src_ip[1]);
1915 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1916 input->formatted.src_ip[2]);
1918 /* record the source address (big-endian) */
1919 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1920 input->formatted.src_ip[0]);
1923 * (big-endian) */
1924 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1925 input->formatted.dst_ip[0]);
1927 /* record source and destination port (little-endian)*/
1928 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1930 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port);
1931 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1934 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1935 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1937 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id);
1938 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1941 if (input->formatted.tunnel_type != 0)
1944 addr_low = ((u32)input->formatted.inner_mac[0] |
1945 ((u32)input->formatted.inner_mac[1] << 8) |
1946 ((u32)input->formatted.inner_mac[2] << 16) |
1947 ((u32)input->formatted.inner_mac[3] << 24));
1948 addr_high = ((u32)input->formatted.inner_mac[4] |
1949 ((u32)input->formatted.inner_mac[5] << 8));
1951 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1952 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1953 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1957 fdirhash = input->formatted.bkt_hash;
1959 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1965 IXGBE_WRITE_FLUSH(hw);
1972 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1974 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1976 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1978 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1979 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1981 DEBUGOUT("Flow Director command did not complete!\n");
1988 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1997 fdirhash = input->formatted.bkt_hash;
1999 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2001 /* flush hash to HW */
2002 IXGBE_WRITE_FLUSH(hw);
2005 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
2007 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
2009 DEBUGOUT("Flow Director command did not complete!\n");
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2016 IXGBE_WRITE_FLUSH(hw);
2017 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
2025 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2026 * @hw: pointer to hardware structure
2036 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2050 switch (input->formatted.flow_type) {
2053 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2054 if (input->formatted.dst_port || input->formatted.src_port) {
2061 if (input->formatted.dst_port || input->formatted.src_port) {
2065 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2072 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2076 DEBUGOUT(" Error on flow type input\n");
2080 /* program input mask into the HW */
2081 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2089 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2094 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2095 * @hw: pointer to hardware structure
2101 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2107 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2109 IXGBE_WRITE_FLUSH(hw);
2111 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2118 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2119 * @hw: pointer to hardware structure
2125 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2132 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2133 IXGBE_WRITE_FLUSH(hw);
2140 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2141 * @hw: pointer to hardware structure
2145 * Then performs revision-specific operations, if any.
2147 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2153 ret_val = ixgbe_start_hw_generic(hw);
2157 ixgbe_start_hw_gen2(hw);
2160 hw->mac.autotry_restart = true;
2163 ret_val = ixgbe_verify_fw_version_82599(hw);
2169 * ixgbe_identify_phy_82599 - Get physical layer module
2170 * @hw: pointer to hardware structure
2173 * If PHY already detected, maintains current PHY type in hw struct,
2176 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2182 /* Detect PHY if not unknown - returns success if already detected. */
2183 status = ixgbe_identify_phy_generic(hw);
2185 /* 82599 10GBASE-T requires an external PHY */
2186 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2189 status = ixgbe_identify_module_generic(hw);
2193 if (hw->phy.type == ixgbe_phy_unknown) {
2194 hw->phy.type = ixgbe_phy_none;
2199 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2206 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2207 * @hw: pointer to hardware structure
2211 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2214 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2215 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2223 hw->phy.ops.identify(hw);
2225 switch (hw->phy.type) {
2228 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2285 * test KR mode - we need to id KR mode correctly before SFP module.
2287 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2293 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2294 * @hw: pointer to hardware structure
2299 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2311 hw->mac.ops.disable_sec_rx_path(hw);
2314 ixgbe_enable_rx(hw);
2316 ixgbe_disable_rx(hw);
2318 hw->mac.ops.enable_sec_rx_path(hw);
2324 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2325 * @hw: pointer to hardware structure
2333 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2342 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2348 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2358 if (hw->eeprom.ops.read(hw, (fw_offset +
2372 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2388 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2389 * @hw: pointer to hardware structure
2394 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2403 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2410 status = hw->eeprom.ops.read(hw, (fw_offset +
2419 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2432 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2435 * @hw: pointer to hardware structure
2442 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2445 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2454 if ((eeprom->type == ixgbe_eeprom_spi) &&
2455 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2456 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2459 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2467 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2470 * @hw: pointer to hardware structure
2476 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2479 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2488 if ((eeprom->type == ixgbe_eeprom_spi) &&
2490 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2492 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2498 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2500 * @hw: pointer to hardware structure
2505 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2512 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2515 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2516 IXGBE_WRITE_FLUSH(hw);
2519 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2522 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2527 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2542 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2543 IXGBE_WRITE_FLUSH(hw);
2549 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2550 * @hw: pointer to hardware structure
2558 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2567 if (hw->phy.qsfp_shared_i2c_bus == true) {
2569 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2571 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2572 IXGBE_WRITE_FLUSH(hw);
2575 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2580 timeout--;
2591 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2595 if (hw->phy.qsfp_shared_i2c_bus == true) {
2597 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2599 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2600 IXGBE_WRITE_FLUSH(hw);
2607 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2608 * @hw: pointer to hardware structure
2616 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2625 if (hw->phy.qsfp_shared_i2c_bus == true) {
2627 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2629 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2630 IXGBE_WRITE_FLUSH(hw);
2633 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2638 timeout--;
2649 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2653 if (hw->phy.qsfp_shared_i2c_bus == true) {
2655 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2658 IXGBE_WRITE_FLUSH(hw);