Lines Matching +full:led +full:- +full:7 +full:seg
1 /*-
2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr>
84 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" },
85 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" },
86 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" },
87 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" },
88 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" },
89 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" },
90 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" },
91 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" },
92 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" },
93 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" },
94 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" },
95 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" },
96 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" },
97 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" },
99 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" },
100 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" },
101 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" },
102 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" },
103 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" },
104 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" },
105 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" },
106 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" },
107 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" },
108 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" },
110 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" },
111 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" },
119 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" },
120 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" },
378 nitems(iwn_ident_table) - 1);
403 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
404 if (pci_get_vendor(dev) == ident->vendor &&
405 pci_get_device(dev) == ident->device) {
406 device_set_desc(dev, ident->name);
417 if (sc->hw_type == IWN_HW_REV_TYPE_5300)
429 sc->sc_dev = dev;
432 error = resource_int_value(device_get_name(sc->sc_dev),
433 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug));
435 sc->sc_debug = 0;
437 sc->sc_debug = 0;
440 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__);
446 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
452 /* Clear device-specific "PCI retry timeout" register (41h). */
455 /* Enable bus-mastering. */
459 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
461 if (sc->mem == NULL) {
466 sc->sc_st = rman_get_bustag(sc->mem);
467 sc->sc_sh = rman_get_bushandle(sc->mem);
474 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE |
476 if (sc->irq == NULL) {
485 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT)
487 sc->subdevice_id = pci_get_subdevice(dev);
493 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
529 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
544 for (i = 0; i < sc->ntxqs; i++) {
545 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
554 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
563 ic = &sc->sc_ic;
564 ic->ic_softc = sc;
565 ic->ic_name = device_get_nameunit(dev);
566 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
567 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
570 ic->ic_caps =
584 | IEEE80211_C_PMGT /* Station-side power mgmt */
588 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) {
595 sc->ntxchains =
596 ((sc->txchainmask >> 2) & 1) +
597 ((sc->txchainmask >> 1) & 1) +
598 ((sc->txchainmask >> 0) & 1);
599 sc->nrxchains =
600 ((sc->rxchainmask >> 2) & 1) +
601 ((sc->rxchainmask >> 1) & 1) +
602 ((sc->rxchainmask >> 0) & 1);
605 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
606 ic->ic_macaddr, ":");
609 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
610 ic->ic_rxstream = sc->nrxchains;
611 ic->ic_txstream = sc->ntxchains;
616 * it's not a 3-stream device.
619 if (ic->ic_rxstream > 2)
620 ic->ic_rxstream = 2;
621 if (ic->ic_txstream > 2)
622 ic->ic_txstream = 2;
625 ic->ic_htcaps =
633 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */
635 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
640 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
642 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
648 ic->ic_vap_create = iwn_vap_create;
649 ic->ic_ioctl = iwn_ioctl;
650 ic->ic_parent = iwn_parent;
651 ic->ic_vap_delete = iwn_vap_delete;
652 ic->ic_transmit = iwn_transmit;
653 ic->ic_raw_xmit = iwn_raw_xmit;
654 ic->ic_node_alloc = iwn_node_alloc;
655 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
656 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
657 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
658 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
659 sc->sc_addba_request = ic->ic_addba_request;
660 ic->ic_addba_request = iwn_addba_request;
661 sc->sc_addba_response = ic->ic_addba_response;
662 ic->ic_addba_response = iwn_addba_response;
663 sc->sc_addba_stop = ic->ic_addba_stop;
664 ic->ic_addba_stop = iwn_ampdu_tx_stop;
665 ic->ic_newassoc = iwn_newassoc;
666 ic->ic_wme.wme_update = iwn_updateedca;
667 ic->ic_update_promisc = iwn_update_promisc;
668 ic->ic_update_mcast = iwn_update_mcast;
669 ic->ic_scan_start = iwn_scan_start;
670 ic->ic_scan_end = iwn_scan_end;
671 ic->ic_set_channel = iwn_set_channel;
672 ic->ic_scan_curchan = iwn_scan_curchan;
673 ic->ic_scan_mindwell = iwn_scan_mindwell;
674 ic->ic_getradiocaps = iwn_getradiocaps;
675 ic->ic_setregdomain = iwn_setregdomain;
679 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
680 callout_init_mtx(&sc->scan_timeout, &sc->sc_mtx, 0);
681 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
682 TASK_INIT(&sc->sc_rftoggle_task, 0, iwn_rftoggle_task, sc);
683 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc);
684 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc);
686 mbufq_init(&sc->sc_xmit_queue, 1024);
688 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK,
689 taskqueue_thread_enqueue, &sc->sc_tq);
690 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq");
701 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
702 NULL, iwn_intr, sc, &sc->sc_ih);
710 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n",
718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
721 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev),
723 if (sc->sc_cdev == NULL) {
726 sc->sc_cdev->si_drv1 = sc;
731 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
749 sc->base_params = &iwn4965_base_params;
750 sc->limits = &iwn4965_sensitivity_limits;
751 sc->fwname = "iwn4965fw";
753 sc->txchainmask = IWN_ANT_AB;
754 sc->rxchainmask = IWN_ANT_ABC;
756 sc->sc_flags |= IWN_FLAG_BTCOEX;
761 switch(sc->subdevice_id) {
774 sc->limits = &iwn1000_sensitivity_limits;
775 sc->base_params = &iwn1000_base_params;
776 sc->fwname = "iwn1000fw";
779 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
781 sc->subdevice_id,sc->hw_type);
790 sc->fwname = "iwn6000fw";
791 sc->limits = &iwn6000_sensitivity_limits;
792 switch(sc->subdevice_id) {
797 sc->base_params = &iwn_6000_base_params;
809 sc->base_params = &iwn_6000i_base_params;
810 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
811 sc->txchainmask = IWN_ANT_BC;
812 sc->rxchainmask = IWN_ANT_BC;
815 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
817 sc->subdevice_id,sc->hw_type);
824 switch(sc->subdevice_id) {
844 sc->fwname = "iwn6000g2afw";
845 sc->limits = &iwn6000_sensitivity_limits;
846 sc->base_params = &iwn_6000g2_base_params;
849 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
851 sc->subdevice_id,sc->hw_type);
858 switch(sc->subdevice_id) {
864 sc->fwname = "iwn6000g2bfw";
865 sc->limits = &iwn6235_sensitivity_limits;
866 sc->base_params = &iwn_6235_base_params;
869 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
871 sc->subdevice_id,sc->hw_type);
878 switch(sc->subdevice_id) {
887 sc->fwname = "iwn6050fw";
888 sc->txchainmask = IWN_ANT_AB;
889 sc->rxchainmask = IWN_ANT_AB;
890 sc->limits = &iwn6000_sensitivity_limits;
891 sc->base_params = &iwn_6050_base_params;
894 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
896 sc->subdevice_id,sc->hw_type);
903 switch(sc->subdevice_id) {
912 sc->fwname = "iwn6050fw";
913 sc->limits = &iwn6000_sensitivity_limits;
914 sc->base_params = &iwn_6150_base_params;
917 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
919 sc->subdevice_id,sc->hw_type);
928 switch(sc->subdevice_id) {
951 sc->fwname = "iwn6000g2bfw";
952 sc->limits = &iwn6000_sensitivity_limits;
953 sc->base_params = &iwn_6000g2b_base_params;
956 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
958 sc->subdevice_id,sc->hw_type);
968 switch(sc->subdevice_id) {
977 sc->fwname = "iwn6000g2bfw";
978 sc->limits = &iwn6000_sensitivity_limits;
979 sc->base_params = &iwn_6000g2b_base_params;
982 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
984 sc->subdevice_id,sc->hw_type);
991 switch(sc->subdevice_id) {
998 sc->limits = &iwn1000_sensitivity_limits;
999 sc->base_params = &iwn1000_base_params;
1000 sc->fwname = "iwn100fw";
1003 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1005 sc->subdevice_id,sc->hw_type);
1016 switch(sc->subdevice_id) {
1023 sc->limits = &iwn2030_sensitivity_limits;
1024 sc->base_params = &iwn2000_base_params;
1025 sc->fwname = "iwn105fw";
1028 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1030 sc->subdevice_id,sc->hw_type);
1041 switch(sc->subdevice_id) {
1045 sc->limits = &iwn2030_sensitivity_limits;
1046 sc->base_params = &iwn2030_base_params;
1047 sc->fwname = "iwn135fw";
1050 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1052 sc->subdevice_id,sc->hw_type);
1060 switch(sc->subdevice_id) {
1067 sc->limits = &iwn2030_sensitivity_limits;
1068 sc->base_params = &iwn2000_base_params;
1069 sc->fwname = "iwn2000fw";
1072 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1074 pid, sc->subdevice_id, sc->hw_type);
1081 switch(sc->subdevice_id) {
1090 sc->limits = &iwn2030_sensitivity_limits;
1091 sc->base_params = &iwn2030_base_params;
1092 sc->fwname = "iwn2030fw";
1095 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1097 sc->subdevice_id,sc->hw_type);
1106 sc->limits = &iwn5000_sensitivity_limits;
1107 sc->base_params = &iwn5000_base_params;
1108 sc->fwname = "iwn5000fw";
1109 switch(sc->subdevice_id) {
1123 sc->txchainmask = IWN_ANT_B;
1124 sc->rxchainmask = IWN_ANT_AB;
1133 sc->txchainmask = IWN_ANT_B;
1134 sc->rxchainmask = IWN_ANT_AB;
1143 sc->txchainmask = IWN_ANT_B;
1144 sc->rxchainmask = IWN_ANT_AB;
1159 sc->txchainmask = IWN_ANT_ABC;
1160 sc->rxchainmask = IWN_ANT_ABC;
1163 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1165 sc->subdevice_id,sc->hw_type);
1174 sc->limits = &iwn5000_sensitivity_limits;
1175 sc->base_params = &iwn5000_base_params;
1176 sc->fwname = "iwn5000fw";
1177 switch(sc->subdevice_id) {
1182 sc->limits = &iwn5000_sensitivity_limits;
1183 sc->base_params = &iwn5000_base_params;
1184 sc->fwname = "iwn5000fw";
1198 sc->limits = &iwn5000_sensitivity_limits;
1199 sc->fwname = "iwn5150fw";
1200 sc->base_params = &iwn_5x50_base_params;
1203 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :"
1205 sc->subdevice_id,sc->hw_type);
1210 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x"
1211 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id,
1212 sc->hw_type);
1221 struct iwn_ops *ops = &sc->ops;
1223 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1225 ops->load_firmware = iwn4965_load_firmware;
1226 ops->read_eeprom = iwn4965_read_eeprom;
1227 ops->post_alive = iwn4965_post_alive;
1228 ops->nic_config = iwn4965_nic_config;
1229 ops->update_sched = iwn4965_update_sched;
1230 ops->get_temperature = iwn4965_get_temperature;
1231 ops->get_rssi = iwn4965_get_rssi;
1232 ops->set_txpower = iwn4965_set_txpower;
1233 ops->init_gains = iwn4965_init_gains;
1234 ops->set_gains = iwn4965_set_gains;
1235 ops->rxon_assoc = iwn4965_rxon_assoc;
1236 ops->add_node = iwn4965_add_node;
1237 ops->tx_done = iwn4965_tx_done;
1238 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
1239 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
1240 sc->ntxqs = IWN4965_NTXQUEUES;
1241 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
1242 sc->ndmachnls = IWN4965_NDMACHNLS;
1243 sc->broadcast_id = IWN4965_ID_BROADCAST;
1244 sc->rxonsz = IWN4965_RXONSZ;
1245 sc->schedsz = IWN4965_SCHEDSZ;
1246 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
1247 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
1248 sc->fwsz = IWN4965_FWSZ;
1249 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
1250 sc->limits = &iwn4965_sensitivity_limits;
1251 sc->fwname = "iwn4965fw";
1253 sc->txchainmask = IWN_ANT_AB;
1254 sc->rxchainmask = IWN_ANT_ABC;
1256 sc->sc_flags |= IWN_FLAG_BTCOEX;
1264 struct iwn_ops *ops = &sc->ops;
1266 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1268 ops->load_firmware = iwn5000_load_firmware;
1269 ops->read_eeprom = iwn5000_read_eeprom;
1270 ops->post_alive = iwn5000_post_alive;
1271 ops->nic_config = iwn5000_nic_config;
1272 ops->update_sched = iwn5000_update_sched;
1273 ops->get_temperature = iwn5000_get_temperature;
1274 ops->get_rssi = iwn5000_get_rssi;
1275 ops->set_txpower = iwn5000_set_txpower;
1276 ops->init_gains = iwn5000_init_gains;
1277 ops->set_gains = iwn5000_set_gains;
1278 ops->rxon_assoc = iwn5000_rxon_assoc;
1279 ops->add_node = iwn5000_add_node;
1280 ops->tx_done = iwn5000_tx_done;
1281 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
1282 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
1283 sc->ntxqs = IWN5000_NTXQUEUES;
1284 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
1285 sc->ndmachnls = IWN5000_NDMACHNLS;
1286 sc->broadcast_id = IWN5000_ID_BROADCAST;
1287 sc->rxonsz = IWN5000_RXONSZ;
1288 sc->schedsz = IWN5000_SCHEDSZ;
1289 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
1290 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
1291 sc->fwsz = IWN5000_FWSZ;
1292 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
1293 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
1294 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
1306 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1307 ieee80211_radiotap_attach(&sc->sc_ic,
1308 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
1310 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
1312 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1319 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
1320 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
1323 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug,
1334 struct iwn_softc *sc = ic->ic_softc;
1338 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1342 vap = &ivp->iv_vap;
1344 ivp->ctx = IWN_RXON_BSS_CTX;
1345 vap->iv_bmissthreshold = 10; /* override default */
1347 ivp->iv_newstate = vap->iv_newstate;
1348 vap->iv_newstate = iwn_newstate;
1349 sc->ivap[IWN_RXON_BSS_CTX] = vap;
1350 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1351 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; /* 4uS */
1357 ic->ic_opmode = opmode;
1378 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
1379 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1390 return (mbufq_enqueue(&sc->sc_xmit_queue, m));
1399 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1401 if (sc->sc_ic.ic_softc != NULL) {
1409 taskqueue_drain_all(sc->sc_tq);
1410 taskqueue_free(sc->sc_tq);
1412 callout_drain(&sc->watchdog_to);
1413 callout_drain(&sc->scan_timeout);
1414 callout_drain(&sc->calib_to);
1415 ieee80211_ifdetach(&sc->sc_ic);
1419 if (sc->irq != NULL) {
1420 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
1421 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq),
1422 sc->irq);
1427 iwn_free_rx_ring(sc, &sc->rxq);
1428 for (qid = 0; qid < sc->ntxqs; qid++)
1429 iwn_free_tx_ring(sc, &sc->txq[qid]);
1432 if (sc->ict != NULL)
1436 if (sc->mem != NULL)
1438 rman_get_rid(sc->mem), sc->mem);
1440 if (sc->sc_cdev) {
1441 destroy_dev(sc->sc_cdev);
1442 sc->sc_cdev = NULL;
1445 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__);
1464 ieee80211_suspend_all(&sc->sc_ic);
1473 /* Clear device-specific "PCI retry timeout" register (41h). */
1476 ieee80211_resume_all(&sc->sc_ic);
1537 for (; count > 0; count--, data++, addr += 4)
1574 for (; count > 0; count--, addr += 4)
1582 for (; count > 0; count--, addr += 4)
1604 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__);
1624 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1638 if (sc->base_params->shadow_ram_support) {
1651 if (! sc->base_params->shadow_ram_support) {
1655 for (count = 0; count < sc->base_params->max_ll_items;
1660 if (next == 0) /* End of linked-list. */
1665 if (count == 0 || count == sc->base_params->max_ll_items)
1668 sc->prom_base = prev + 1;
1671 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1683 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1685 addr += sc->prom_base;
1686 for (; count > 0; count -= 2, addr++) {
1695 device_printf(sc->sc_dev,
1699 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1703 device_printf(sc->sc_dev,
1718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
1738 dma->tag = NULL;
1739 dma->size = size;
1741 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1743 1, size, 0, NULL, NULL, &dma->tag);
1747 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1748 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1752 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1753 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1757 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1760 *kvap = dma->vaddr;
1771 if (dma->vaddr != NULL) {
1772 bus_dmamap_sync(dma->tag, dma->map,
1774 bus_dmamap_unload(dma->tag, dma->map);
1775 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1776 dma->vaddr = NULL;
1778 if (dma->tag != NULL) {
1779 bus_dma_tag_destroy(dma->tag);
1780 dma->tag = NULL;
1788 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1789 sc->schedsz, 1024);
1795 iwn_dma_contig_free(&sc->sched_dma);
1802 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1808 iwn_dma_contig_free(&sc->kw_dma);
1815 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1822 iwn_dma_contig_free(&sc->ict_dma);
1828 /* Must be aligned on a 16-byte boundary. */
1829 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1835 iwn_dma_contig_free(&sc->fw_dma);
1844 ring->cur = 0;
1846 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1848 /* Allocate RX descriptors (256-byte aligned). */
1850 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1853 device_printf(sc->sc_dev,
1859 /* Allocate RX status area (16-byte aligned). */
1860 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1863 device_printf(sc->sc_dev,
1870 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1872 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat);
1874 device_printf(sc->sc_dev,
1884 struct iwn_rx_data *data = &ring->data[i];
1887 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1889 device_printf(sc->sc_dev,
1895 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1897 if (data->m == NULL) {
1898 device_printf(sc->sc_dev,
1904 error = bus_dmamap_load(ring->data_dmat, data->map,
1905 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1908 device_printf(sc->sc_dev,
1914 bus_dmamap_sync(ring->data_dmat, data->map,
1917 /* Set physical address of RX buffer (256-byte aligned). */
1918 ring->desc[i] = htole32(paddr >> 8);
1921 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1924 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
1930 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
1940 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
1952 ring->cur = 0;
1953 sc->last_rx_valid = 0;
1961 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
1963 iwn_dma_contig_free(&ring->desc_dma);
1964 iwn_dma_contig_free(&ring->stat_dma);
1967 struct iwn_rx_data *data = &ring->data[i];
1969 if (data->m != NULL) {
1970 bus_dmamap_sync(ring->data_dmat, data->map,
1972 bus_dmamap_unload(ring->data_dmat, data->map);
1973 m_freem(data->m);
1974 data->m = NULL;
1976 if (data->map != NULL)
1977 bus_dmamap_destroy(ring->data_dmat, data->map);
1979 if (ring->data_dmat != NULL) {
1980 bus_dma_tag_destroy(ring->data_dmat);
1981 ring->data_dmat = NULL;
1992 ring->qid = qid;
1993 ring->queued = 0;
1994 ring->cur = 0;
1996 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
1998 /* Allocate TX descriptors (256-byte aligned). */
2000 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
2003 device_printf(sc->sc_dev,
2010 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
2013 device_printf(sc->sc_dev,
2019 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
2021 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
2023 device_printf(sc->sc_dev,
2029 paddr = ring->cmd_dma.paddr;
2031 struct iwn_tx_data *data = &ring->data[i];
2033 data->cmd_paddr = paddr;
2034 data->scratch_paddr = paddr + 12;
2037 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
2039 device_printf(sc->sc_dev,
2046 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2051 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2060 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__);
2063 struct iwn_tx_data *data = &ring->data[i];
2065 if (data->m != NULL) {
2066 bus_dmamap_sync(ring->data_dmat, data->map,
2068 bus_dmamap_unload(ring->data_dmat, data->map);
2069 m_freem(data->m);
2070 data->m = NULL;
2072 if (data->ni != NULL) {
2073 ieee80211_free_node(data->ni);
2074 data->ni = NULL;
2076 data->remapped = 0;
2077 data->long_retries = 0;
2080 memset(ring->desc, 0, ring->desc_dma.size);
2081 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2083 sc->qfullmsk &= ~(1 << ring->qid);
2084 ring->queued = 0;
2085 ring->cur = 0;
2093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__);
2095 iwn_dma_contig_free(&ring->desc_dma);
2096 iwn_dma_contig_free(&ring->cmd_dma);
2099 struct iwn_tx_data *data = &ring->data[i];
2101 if (data->m != NULL) {
2102 bus_dmamap_sync(ring->data_dmat, data->map,
2104 bus_dmamap_unload(ring->data_dmat, data->map);
2105 m_freem(data->m);
2107 if (data->map != NULL)
2108 bus_dmamap_destroy(ring->data_dmat, data->map);
2110 if (ring->data_dmat != NULL) {
2111 bus_dma_tag_destroy(ring->data_dmat);
2112 ring->data_dmat = NULL;
2119 struct iwn_tx_ring *ring = &sc->txq[qid];
2121 KASSERT(ring->queued >= 0, ("%s: ring->queued (%d) for queue %d < 0!",
2122 __func__, ring->queued, qid));
2124 if (qid >= sc->firstaggqueue) {
2125 struct iwn_ops *ops = &sc->ops;
2126 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid];
2128 if (ring->queued == 0 && !IEEE80211_AMPDU_RUNNING(tap)) {
2129 uint16_t ssn = tap->txa_start & 0xfff;
2130 uint8_t tid = tap->txa_tid;
2131 int *res = tap->txa_private;
2134 ops->ampdu_tx_stop(sc, qid, tid, ssn);
2137 sc->qid2tap[qid] = NULL;
2142 if (ring->queued < IWN_TX_RING_LOMARK) {
2143 sc->qfullmsk &= ~(1 << qid);
2145 if (ring->queued == 0)
2146 sc->sc_tx_timer = 0;
2148 sc->sc_tx_timer = 5;
2159 memset(sc->ict, 0, IWN_ICT_SIZE);
2160 sc->ict_cur = 0;
2162 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
2168 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
2171 sc->int_mask |= IWN_INT_RX_PERIODIC;
2173 sc->sc_flags |= IWN_FLAG_USE_ICT;
2175 /* Re-enable interrupts. */
2177 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2183 struct iwn_ops *ops = &sc->ops;
2187 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2190 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
2192 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
2194 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
2198 device_printf(sc->sc_dev,
2205 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
2209 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
2213 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
2215 device_printf(sc->sc_dev,
2226 sc->sc_flags |= IWN_FLAG_HAS_11N;
2229 sc->rfcfg = le16toh(val);
2230 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
2232 if (sc->txchainmask == 0)
2233 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
2234 if (sc->rxchainmask == 0)
2235 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
2240 /* Read adapter-specific information from EEPROM. */
2241 ops->read_eeprom(sc);
2247 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2259 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2262 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
2265 for (i = 0; i < IWN_NBANDS - 1; i++) {
2272 sc->maxpwr2GHz = val & 0xff;
2273 sc->maxpwr5GHz = val >> 8;
2275 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
2276 sc->maxpwr5GHz = 38;
2277 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
2278 sc->maxpwr2GHz = 38;
2280 sc->maxpwr2GHz, sc->maxpwr5GHz);
2283 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
2284 sizeof sc->bands);
2288 sc->eeprom_voltage = (int16_t)le16toh(val);
2290 sc->eeprom_voltage);
2294 if (sc->sc_debug & IWN_DEBUG_ANY) {
2295 for (i = 0; i < IWN_NBANDS - 1; i++)
2300 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2307 struct iwn4965_eeprom_band *band = &sc->bands[i];
2308 struct iwn4965_eeprom_chan_samples *chans = band->chans;
2312 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
2347 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2353 sc->eeprom_domain, 4);
2356 for (i = 0; i < IWN_NBANDS - 1; i++) {
2357 addr = base + sc->base_params->regulatory_bands[i];
2362 if (sc->base_params->enhanced_TX_power)
2371 sc->calib_ver = hdr.version;
2373 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
2374 sc->eeprom_voltage = le16toh(hdr.volt);
2376 sc->eeprom_temp_high=le16toh(val);
2378 sc->eeprom_temp = le16toh(val);
2381 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
2384 sc->eeprom_temp = le16toh(val);
2387 sc->temp_off = sc->eeprom_temp - (volt / -5);
2389 sc->eeprom_temp, volt, sc->temp_off);
2393 &sc->eeprom_crystal, sizeof (uint32_t));
2395 le32toh(sc->eeprom_crystal));
2398 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2411 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
2413 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
2415 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
2428 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2434 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2440 if (sc->sc_flags & IWN_FLAG_HAS_11N)
2444 if (sc->sc_flags & IWN_FLAG_HAS_11N)
2448 for (i = 0; i < band->nchan; i++) {
2452 band->chan[i], channels[i].flags,
2457 chan = band->chan[i];
2466 sc->maxpwr[chan] = channels[i].maxpwr;
2473 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2481 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
2486 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__);
2488 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) {
2489 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__);
2493 for (i = 0; i < band->nchan; i++) {
2497 band->chan[i], channels[i].flags,
2502 chan = band->chan[i];
2509 device_printf(sc->sc_dev,
2518 device_printf(sc->sc_dev,
2531 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2538 struct ieee80211com *ic = &sc->sc_ic;
2540 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
2544 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans,
2545 ic->ic_channels);
2547 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans,
2548 ic->ic_channels);
2550 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
2561 chan = c->ic_extieee;
2563 chan = c->ic_ieee;
2566 return &sc->eeprom_channels[band][i];
2571 if (iwn_bands[j].chan[i] == c->ic_ieee &&
2573 return &sc->eeprom_channels[j][i];
2584 struct iwn_softc *sc = ic->ic_softc;
2590 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++)
2601 struct iwn_softc *sc = ic->ic_softc;
2611 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2614 c->ic_flags |= iwn_eeprom_channel_flags(channel);
2624 struct ieee80211com *ic = &sc->sc_ic;
2631 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2644 if (sc->txchainmask & IWN_ANT_A)
2646 if (sc->txchainmask & IWN_ANT_B)
2648 if (sc->txchainmask & IWN_ANT_C)
2650 if (sc->ntxchains == 2)
2652 else if (sc->ntxchains == 3)
2655 for (j = 0; j < ic->ic_nchans; j++) {
2656 c = &ic->ic_channels[j];
2673 enhinfo[i].chan != c->ic_ieee)
2677 "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2678 c->ic_flags, maxpwr / 2);
2679 c->ic_maxregpower = maxpwr / 2;
2680 c->ic_maxpower = maxpwr;
2684 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__);
2697 wn->id = IWN_ID_UNDEFINED;
2699 return (&wn->ni);
2746 return IWN_LSB(sc->txchainmask);
2769 /* Default - transmit on the other antennas */
2770 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask));
2777 * If the NIC is a two-stream TX NIC, configure the TX mask to
2780 else if (sc->ntxchains == 2)
2781 tx = sc->txchainmask;
2799 struct ieee80211com *ic = ni->ni_ic;
2809 * Set the initial PLCP value to be between 0->31 for
2810 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!"
2821 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2833 plcp |= IWN_RFLAG_ANT(sc->txchainmask);
2840 * Set the initial PLCP - fine for both
2848 * to map the ridx -> phy table entry
2852 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
2855 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2881 struct ieee80211com *ic = vap->iv_ic;
2882 struct iwn_softc *sc = ic->ic_softc;
2885 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
2887 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2888 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2892 callout_stop(&sc->calib_to);
2894 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
2898 if (vap->iv_state != IEEE80211_S_RUN)
2902 if (vap->iv_state == IEEE80211_S_AUTH)
2906 * !AUTH -> AUTH transition requires state reset to handle
2909 sc->rxon->associd = 0;
2910 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS);
2911 sc->calib.state = IWN_CALIB_STATE_INIT;
2914 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan))
2915 sc->sc_beacon_wait = 1;
2918 device_printf(sc->sc_dev,
2925 * RUN -> RUN transition; Just restart the timers.
2927 if (vap->iv_state == IEEE80211_S_RUN) {
2928 sc->calib_cnt = 0;
2933 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan))
2934 sc->sc_beacon_wait = 1;
2937 * !RUN -> RUN requires setting the association id
2942 device_printf(sc->sc_dev,
2948 sc->calib.state = IWN_CALIB_STATE_INIT;
2953 sc->sc_beacon_wait = 0;
2963 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
2967 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
2969 return ivp->iv_newstate(vap, nstate, arg);
2980 if (++sc->calib_cnt >= 120) {
2987 sc->calib_cnt = 0;
2989 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
3005 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
3006 sc->last_rx_valid = 1;
3017 struct iwn_ops *ops = &sc->ops;
3018 struct ieee80211com *ic = &sc->sc_ic;
3019 struct iwn_rx_ring *ring = &sc->rxq;
3029 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3031 if (desc->type == IWN_MPDU_RX_DONE) {
3033 if (!sc->last_rx_valid) {
3038 stat = &sc->last_rx_stat;
3042 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
3043 device_printf(sc->sc_dev,
3045 stat->cfg_phy_len);
3048 if (desc->type == IWN_MPDU_RX_DONE) {
3051 len = le16toh(mpdu->len);
3053 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
3054 len = le16toh(stat->len);
3063 counter_u64_add(ic->ic_ierrors, 1);
3070 counter_u64_add(ic->ic_ierrors, 1);
3078 counter_u64_add(ic->ic_ierrors, 1);
3081 bus_dmamap_unload(ring->data_dmat, data->map);
3083 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
3086 device_printf(sc->sc_dev,
3091 error = bus_dmamap_load(ring->data_dmat, data->map,
3092 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
3097 bus_dmamap_sync(ring->data_dmat, data->map,
3100 ring->desc[ring->cur] = htole32(paddr >> 8);
3101 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3103 counter_u64_add(ic->ic_ierrors, 1);
3107 bus_dmamap_sync(ring->data_dmat, data->map,
3110 m = data->m;
3111 data->m = m1;
3113 ring->desc[ring->cur] = htole32(paddr >> 8);
3114 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3118 m->m_data = head;
3119 m->m_pkthdr.len = m->m_len = len;
3127 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
3128 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
3130 rssi = ops->get_rssi(sc, stat);
3133 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
3134 uint32_t rate = le32toh(stat->rate);
3136 tap->wr_flags = 0;
3137 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
3138 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3139 tap->wr_dbm_antsignal = (int8_t)rssi;
3140 tap->wr_dbm_antnoise = (int8_t)nf;
3141 tap->wr_tsft = stat->tstamp;
3143 tap->wr_rate = rate & IWN_RFLAG_RATE_MCS;
3144 tap->wr_rate |= IEEE80211_RATE_MCS;
3146 tap->wr_rate = plcp2rate(rate & IWN_RFLAG_RATE);
3153 if (sc->sc_beacon_wait) {
3155 /* NB: Re-assign wh */
3157 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3158 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3171 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task);
3179 if (ni->ni_flags & IEEE80211_NODE_HT)
3180 m->m_flags |= M_AMPDU;
3181 (void)ieee80211_input(ni, m, rssi - nf, nf);
3185 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
3189 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3197 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
3198 struct iwn_tx_data *data = &ring->data[idx];
3203 KASSERT(data->ni != NULL, ("idx %d: no node", idx));
3204 KASSERT(data->m != NULL, ("idx %d: no mbuf", idx));
3207 bus_dmamap_sync(ring->data_dmat, data->map,
3209 bus_dmamap_unload(ring->data_dmat, data->map);
3210 m = data->m, data->m = NULL;
3211 ni = data->ni, data->ni = NULL;
3216 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY |
3218 txs->long_retries = data->long_retries - 1;
3220 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY;
3222 txs->short_retries = wn->agg[tid].short_retries;
3224 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
3226 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3228 wn->agg[tid].short_retries = 0;
3229 data->long_retries = 0;
3232 __func__, m, ni, idx, ring->qid);
3251 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3253 qid = le16toh(ba->qid);
3254 tap = sc->qid2tap[qid];
3255 ring = &sc->txq[qid];
3256 tid = tap->txa_tid;
3257 wn = (void *)tap->txa_ni;
3261 __func__, qid, tid, le16toh(ba->seq), le16toh(ba->ssn),
3262 (uintmax_t)le64toh(ba->bitmap), (uintmax_t)wn->agg[tid].bitmap,
3263 wn->agg[tid].startidx);
3265 if (wn->agg[tid].bitmap == 0)
3268 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
3269 if (shift <= -64)
3276 * Yes, the rate control code doesn't know these are A-MPDU
3279 bitmap = le64toh(ba->bitmap);
3283 bitmap <<= -shift;
3284 bitmap &= wn->agg[tid].bitmap;
3285 wn->agg[tid].bitmap = 0;
3287 for (i = wn->agg[tid].startidx;
3293 data = &ring->data[i];
3294 if (__predict_false(data->m == NULL)) {
3311 ring->queued -= tx_ok;
3315 "->%s: end; %d ok\n",__func__, tx_ok);
3326 int len, idx = -1;
3328 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3331 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){
3333 "->%s received after calib done\n", __func__);
3336 len = (le32toh(desc->len) & 0x3fff) - 4;
3338 switch (calib->code) {
3340 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC)
3344 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO)
3348 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ)
3352 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC)
3356 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND)
3360 if (idx == -1) /* Ignore other results. */
3364 if (sc->calibcmd[idx].buf != NULL)
3365 free(sc->calibcmd[idx].buf, M_DEVBUF);
3366 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
3367 if (sc->calibcmd[idx].buf == NULL) {
3370 calib->code);
3374 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len);
3375 sc->calibcmd[idx].len = len;
3376 memcpy(sc->calibcmd[idx].buf, calib, len);
3387 * First - check whether the length is the bluetooth or normal.
3389 * If it's normal - just copy it and bump out.
3394 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3395 sc->last_stat_valid = 1;
3400 * If it's not the bluetooth size - log, then just copy.
3407 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats));
3408 sc->last_stat_valid = 1;
3416 lstats = &sc->last_stat;
3419 lstats->flags = stats_bt->flags;
3421 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm,
3423 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck,
3425 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common,
3427 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht,
3430 memcpy(&lstats->tx, &stats_bt->tx,
3433 memcpy(&lstats->general, &stats_bt->general,
3437 sc->last_stat_valid = 1;
3447 struct iwn_ops *ops = &sc->ops;
3448 struct ieee80211com *ic = &sc->sc_ic;
3449 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3450 struct iwn_calib_state *calib = &sc->calib;
3455 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3458 if (vap->iv_state != IEEE80211_S_RUN ||
3459 (ic->ic_flags & IEEE80211_F_SCAN)){
3460 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n",
3467 __func__, desc->type, le16toh(desc->len));
3468 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
3476 iwn_stats_update(sc, calib, stats, le16toh(desc->len));
3481 lstats = &sc->last_stat;
3484 if (lstats->general.temp != sc->rawtemp) {
3486 sc->rawtemp = stats->general.temp;
3487 temp = ops->get_temperature(sc);
3492 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3496 if (desc->type != IWN_BEACON_STATISTICS)
3499 sc->noise = iwn_get_noise(&lstats->rx.general);
3500 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
3503 if (le32toh(lstats->rx.general.flags) != 1) {
3509 if (calib->state == IWN_CALIB_STATE_ASSOC)
3510 iwn_collect_noise(sc, &lstats->rx.general);
3511 else if (calib->state == IWN_CALIB_STATE_RUN) {
3512 iwn_tune_sensitivity(sc, &lstats->rx);
3520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3530 struct iwn_calib_state *calib = &sc->calib;
3533 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp);
3534 calib->fa_cck = le32toh(rs->rx.cck.fa);
3535 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp);
3536 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp);
3537 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa);
3540 sc->last_calib_ticks = ticks;
3552 int qid = desc->qid & IWN_RX_DESC_QID_MSK;
3556 __func__, desc->qid, desc->idx,
3557 stat->rtsfailcnt,
3558 stat->ackfailcnt,
3559 stat->btkillcnt,
3560 stat->rate, le16toh(stat->duration),
3561 le32toh(stat->status));
3563 if (qid >= sc->firstaggqueue && stat->nframes != 1) {
3564 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt,
3565 &stat->status);
3567 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt,
3568 le32toh(stat->status) & 0xff);
3577 int qid = desc->qid & IWN_RX_DESC_QID_MSK;
3581 __func__, desc->qid, desc->idx,
3582 stat->rtsfailcnt,
3583 stat->ackfailcnt,
3584 stat->btkillcnt,
3585 stat->rate, le16toh(stat->duration),
3586 le32toh(stat->status));
3590 iwn5000_reset_sched(sc, qid, desc->idx);
3593 if (qid >= sc->firstaggqueue && stat->nframes != 1) {
3594 iwn_ampdu_tx_done(sc, qid, stat->nframes, stat->rtsfailcnt,
3595 &stat->status);
3597 iwn_tx_done(sc, desc, stat->rtsfailcnt, stat->ackfailcnt,
3598 le16toh(stat->status) & 0xff);
3607 for (i = ring->read; i != ring->cur; i = (i + 1) % IWN_TX_RING_COUNT) {
3608 struct iwn_tx_data *data = &ring->data[i];
3610 if (data->m != NULL)
3613 data->remapped = 0;
3616 ring->read = i;
3620 * Adapter-independent backend for TX_DONE firmware notifications.
3626 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
3627 struct iwn_tx_ring *ring = &sc->txq[desc->qid & IWN_RX_DESC_QID_MSK];
3628 struct iwn_tx_data *data = &ring->data[desc->idx];
3632 if (__predict_false(data->m == NULL &&
3633 ring->qid >= sc->firstaggqueue)) {
3638 __func__, ring->qid, desc->idx);
3642 KASSERT(data->ni != NULL, ("no node"));
3643 KASSERT(data->m != NULL, ("no mbuf"));
3645 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3648 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
3649 bus_dmamap_unload(ring->data_dmat, data->map);
3650 m = data->m, data->m = NULL;
3651 ni = data->ni, data->ni = NULL;
3653 data->long_retries = 0;
3655 if (ring->qid >= sc->firstaggqueue)
3659 * XXX f/w may hang (device timeout) when desc->idx - ring->read == 64
3663 ring->queued--;
3664 iwn_check_tx_ring(sc, ring->qid);
3669 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY |
3671 txs->short_retries = rtsfailcnt;
3672 txs->long_retries = ackfailcnt;
3674 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
3678 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT;
3681 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG;
3684 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED;
3687 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3708 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
3714 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3728 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
3733 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num)
3736 ring = &sc->txq[cmd_queue_num];
3737 data = &ring->data[desc->idx];
3740 if (data->m != NULL) {
3741 bus_dmamap_sync(ring->data_dmat, data->map,
3743 bus_dmamap_unload(ring->data_dmat, data->map);
3744 m_freem(data->m);
3745 data->m = NULL;
3747 wakeup(&ring->desc[desc->idx]);
3755 bit = idx - start;
3758 shift = 0x100 - bit;
3760 } else if (bit <= -64)
3763 shift = -bit;
3767 if (bit - shift >= 64)
3770 return ((bitmap & (1ULL << (bit - shift))) != 0);
3794 * For even 'seqno' % 4 != 0 overflow is cyclic (0 -> +1 -> 0).
3802 struct ieee80211com *ic = &sc->sc_ic;
3806 new_idx = idx - IWN_LONG_RETRY_LIMIT_LOG;
3815 data = &ring->data[new_idx];
3816 if (data->long_retries > IWN_LONG_RETRY_LIMIT) {
3817 device_printf(sc->sc_dev,
3819 "resetting...\n", __func__, data->long_retries,
3820 ring->qid, new_idx);
3822 return (-1);
3829 data = &ring->data[new_idx];
3830 diff = idx - new_idx;
3841 ((data->long_retries >= min_retries &&
3842 data->long_retries < max_retries) ||
3845 data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW))) {
3847 "%s: correcting index %d -> %d in queue %d"
3849 ring->qid, data->long_retries);
3863 struct iwn_tx_ring *ring = &sc->txq[qid];
3864 struct ieee80211_tx_ampdu *tap = sc->qid2tap[qid];
3865 struct iwn_node *wn = (void *)tap->txa_ni;
3869 uint8_t tid = tap->txa_tid;
3872 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
3883 data = &ring->data[idx];
3884 if (data->remapped) {
3886 if (idx == -1) {
3892 data = &ring->data[idx];
3899 data->long_retries &= ~0x0f;
3900 data->long_retries += IWN_AGG_TX_TRY_COUNT(status) + 1;
3902 if (data->long_retries >= IWN_LONG_RETRY_FW_OVERFLOW) {
3905 diff = data->long_retries / IWN_LONG_RETRY_FW_OVERFLOW;
3912 ring->data[wrong_idx].remapped = 1;
3917 * NB: count retries but postpone - it was not
3923 bit = idx - start;
3926 shift = 0x100 - bit;
3928 } else if (bit <= -64)
3931 shift = -bit;
3937 wn->agg[tid].startidx = start;
3938 wn->agg[tid].bitmap = bitmap;
3939 wn->agg[tid].short_retries = rtsfailcnt;
3944 i = ring->read;
3947 i != wn->agg[tid].startidx;
3949 data = &ring->data[i];
3950 data->remapped = 0;
3951 if (data->m == NULL)
3958 ring->read = wn->agg[tid].startidx;
3959 ring->queued -= tx_err;
3963 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
3972 struct iwn_ops *ops = &sc->ops;
3973 struct ieee80211com *ic = &sc->sc_ic;
3974 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3978 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
3981 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
3982 while (sc->rxq.cur != hw) {
3983 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
3986 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3988 desc = mtod(data->m, struct iwn_rx_desc *);
3992 __func__, sc->rxq.cur, desc->qid & IWN_RX_DESC_QID_MSK,
3993 desc->idx, desc->flags, desc->type,
3994 iwn_intr_str(desc->type), le16toh(desc->len));
3996 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */
3999 switch (desc->type) {
4009 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0;
4022 ops->tx_done(sc, desc, data);
4036 misses = le32toh(miss->consecutive);
4040 misses, le32toh(miss->total));
4045 if (vap->iv_state == IEEE80211_S_RUN &&
4046 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
4049 if (misses >= vap->iv_bmissthreshold) {
4054 is_stopped = (sc->sc_flags &
4070 "subtype=%x alive=%x\n", uc->major, uc->minor,
4071 uc->subtype, le32toh(uc->valid));
4073 if (le32toh(uc->valid) != 1) {
4074 device_printf(sc->sc_dev,
4078 if (uc->subtype == IWN_UCODE_INIT) {
4080 memcpy(&sc->ucode_info, uc, sizeof (*uc));
4083 sc->errptr = le32toh(uc->errptr);
4106 __func__, scan->chan, le32toh(scan->status));
4117 scan->nchan, scan->status, scan->chan);
4119 sc->sc_is_scanning = 0;
4120 callout_stop(&sc->scan_timeout);
4125 is_stopped = (sc->sc_flags & IWN_FLAG_RUNNING) == 0;
4136 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
4141 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
4145 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
4146 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
4151 * from power-down sleep mode.
4158 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
4162 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
4163 for (qid = 0; qid < sc->ntxqs; qid++) {
4164 struct iwn_tx_ring *ring = &sc->txq[qid];
4165 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
4173 struct ieee80211com *ic = &sc->sc_ic;
4180 device_printf(sc->sc_dev, "RF switch: radio %s\n",
4188 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
4208 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
4211 if (sc->errptr < IWN_FW_DATA_BASE ||
4212 sc->errptr + sizeof (dump) >
4213 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
4215 sc->errptr);
4223 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
4248 for (i = 0; i < sc->ntxqs; i++) {
4249 struct iwn_tx_ring *ring = &sc->txq[i];
4250 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
4251 i, ring->qid, ring->cur, ring->queued);
4253 printf(" rx ring: cur=%d\n", sc->rxq.cur);
4268 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4269 bus_dmamap_sync(sc->ict_dma.tag, sc->ict_dma.map,
4272 while (sc->ict[sc->ict_cur] != 0) {
4273 tmp |= sc->ict[sc->ict_cur];
4274 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
4275 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
4301 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
4305 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task);
4309 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
4313 device_printf(sc->sc_dev, "%s: fatal firmware error\n",
4321 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task);
4326 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
4341 if (sc->sc_flags & IWN_FLAG_USE_ICT)
4353 /* Re-enable interrupts. */
4354 if (sc->sc_flags & IWN_FLAG_RUNNING)
4355 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
4368 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
4370 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4373 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4377 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4386 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4388 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4391 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4395 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4404 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
4406 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
4409 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4413 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
4429 struct ieee80211com *ic = vap->iv_ic;
4435 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
4442 if ((vap->iv_flags & IEEE80211_F_USEPROT) == 0)
4446 * If it's an 11n rate - no protection.
4457 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK)
4467 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into
4492 rs = (struct ieee80211_rateset *) &ni->ni_htrates;
4493 nr = ni->ni_htrates.rs_nrates;
4495 rs = &ni->ni_rates;
4496 nr = rs->rs_nrates;
4502 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) {
4507 cmp_rate = rs->rs_rates[(nr - 1) - i];
4525 return (IWN_MAX_TX_RETRIES - 1);
4531 const struct ieee80211_txparam *tp = ni->ni_txparms;
4532 struct ieee80211vap *vap = ni->ni_vap;
4533 struct ieee80211com *ic = ni->ni_ic;
4545 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4550 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4554 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
4564 (m->m_flags & M_EAPOL) != 0)
4565 rate = tp->mgmtrate;
4566 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
4567 rate = tp->mcastrate;
4568 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
4569 rate = tp->ucastrate;
4573 rate = ni->ni_txrate;
4578 * go to the normal non-aggregation queue, and have a NONQOS TID
4583 if (m->m_flags & M_AMPDU_MPDU) {
4584 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
4589 ac = *(int *)tap->txa_private;
4593 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
4602 totlen = m->m_pkthdr.len;
4605 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4607 tap->wt_flags = 0;
4608 tap->wt_rate = rate;
4610 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4616 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4625 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
4628 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
4629 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
4631 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
4634 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4636 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4639 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) {
4646 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4647 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4655 ring = &sc->txq[ac];
4656 if (m->m_flags & M_AMPDU_MPDU) {
4657 uint16_t seqno = ni->ni_txseqs[tid];
4659 if (ring->queued > IWN_TX_RING_COUNT / 2 &&
4660 (ring->cur + 1) % IWN_TX_RING_COUNT == ring->read) {
4663 __func__, ring->queued, ac);
4674 if ((seqno % 256) != ring->cur) {
4675 device_printf(sc->sc_dev,
4681 ring->cur);
4684 ni->ni_txseqs[tid] &= ~0xff;
4685 ni->ni_txseqs[tid] += ring->cur;
4686 seqno = ni->ni_txseqs[tid];
4689 *(uint16_t *)wh->i_seq =
4691 ni->ni_txseqs[tid]++;
4695 cmd = &ring->cmd[ring->cur];
4696 tx = (struct iwn_cmd_data *)cmd->data;
4699 tx->scratch = 0; /* clear "scratch" area */
4701 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
4703 tx->id = sc->broadcast_id;
4705 tx->id = wn->id;
4708 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4715 tx->timeout = htole16(3);
4717 tx->timeout = htole16(2);
4719 tx->timeout = htole16(0);
4721 if (tx->id == sc->broadcast_id) {
4723 tx->linkq = 0;
4725 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate);
4729 tx->tid = tid;
4730 tx->rts_ntries = 60;
4731 tx->data_ntries = 15;
4732 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4733 tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4734 tx->security = 0;
4735 tx->flags = htole32(flags);
4744 struct ieee80211vap *vap = ni->ni_vap;
4753 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
4758 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
4760 ac = params->ibp_pri & 3;
4763 rate = params->ibp_rate0;
4766 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
4768 if (params->ibp_flags & IEEE80211_BPF_RTS) {
4769 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4770 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4776 if (params->ibp_flags & IEEE80211_BPF_CTS) {
4777 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4778 /* 5000 autoselects RTS/CTS or CTS-to-self. */
4786 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
4788 tap->wt_flags = 0;
4789 tap->wt_rate = rate;
4794 ring = &sc->txq[ac];
4795 cmd = &ring->cmd[ring->cur];
4797 tx = (struct iwn_cmd_data *)cmd->data;
4799 tx->scratch = 0; /* clear "scratch" area */
4802 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4810 tx->timeout = htole16(3);
4812 tx->timeout = htole16(2);
4814 tx->timeout = htole16(0);
4816 tx->tid = 0;
4817 tx->id = sc->broadcast_id;
4818 tx->rts_ntries = params->ibp_try1;
4819 tx->data_ntries = params->ibp_try0;
4820 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4821 tx->rate = iwn_rate_to_plcp(sc, ni, rate);
4822 tx->security = 0;
4823 tx->flags = htole32(flags);
4826 tx->linkq = 0;
4835 struct iwn_ops *ops = &sc->ops;
4841 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
4848 totlen = m->m_pkthdr.len;
4850 desc = &ring->desc[ring->cur];
4851 data = &ring->data[ring->cur];
4853 if (__predict_false(data->m != NULL || data->ni != NULL)) {
4854 device_printf(sc->sc_dev, "%s: ni (%p) or m (%p) for idx %d "
4855 "in queue %d is not NULL!\n", __func__, data->ni, data->m,
4856 ring->cur, ring->qid);
4861 cmd = &ring->cmd[ring->cur];
4862 cmd->code = IWN_CMD_TX_DATA;
4863 cmd->flags = 0;
4864 cmd->qid = ring->qid;
4865 cmd->idx = ring->cur;
4867 tx = (struct iwn_cmd_data *)cmd->data;
4868 tx->len = htole16(totlen);
4871 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
4872 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
4875 tx->flags |= htole32(IWN_TX_NEED_PADDING);
4876 pad = 4 - (hdrlen & 3);
4886 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
4890 device_printf(sc->sc_dev,
4895 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1);
4897 device_printf(sc->sc_dev,
4903 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
4911 device_printf(sc->sc_dev,
4914 if_inc_counter(ni->ni_vap->iv_ifp,
4922 data->m = m;
4923 data->ni = ni;
4927 __func__, ring->qid, ring->cur, totlen, nsegs, tx->rate);
4930 desc->nsegs = 1;
4931 if (m->m_len != 0)
4932 desc->nsegs += nsegs;
4934 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
4935 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
4938 seg = &segs[0];
4940 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
4941 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
4942 seg->ds_len << 4);
4943 seg++;
4946 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
4947 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
4949 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
4953 if (ring->qid >= sc->firstaggqueue)
4954 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
4957 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
4958 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4961 if (++ring->queued > IWN_TX_RING_HIMARK)
4962 sc->qfullmsk |= 1 << ring->qid;
4964 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
4986 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) {
4988 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
5004 if_inc_counter(ni->ni_vap->iv_ifp,
5011 sc->sc_beacon_wait = 0;
5016 * raw frame xmit - free node/reference if failed.
5022 struct ieee80211com *ic = ni->ni_ic;
5023 struct iwn_softc *sc = ic->ic_softc;
5026 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5029 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) {
5036 if (sc->sc_beacon_wait) {
5061 sc->sc_tx_timer = 5;
5067 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__);
5073 * transmit - don't free mbuf if failed; don't free node ref if failed.
5078 struct iwn_softc *sc = ic->ic_softc;
5082 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
5085 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) {
5090 if (sc->qfullmsk) {
5097 sc->sc_tx_timer = 5;
5106 struct ieee80211com *ic = &sc->sc_ic;
5116 struct ieee80211com *ic = &sc->sc_ic;
5120 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running"));
5122 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5124 if (sc->sc_tx_timer > 0) {
5125 if (--sc->sc_tx_timer == 0) {
5131 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
5153 struct iwn_softc *sc = dev->si_drv1;
5165 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats));
5170 memset(&sc->last_stat, 0, sizeof(struct iwn_stats));
5190 struct iwn_softc *sc = ic->ic_softc;
5194 if (ic->ic_nrunning > 0) {
5203 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task);
5206 vap = TAILQ_FIRST(&ic->ic_vaps);
5230 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5235 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
5240 ring = &sc->txq[cmd_queue_num];
5241 desc = &ring->desc[ring->cur];
5242 data = &ring->data[ring->cur];
5245 if (size > sizeof cmd->data) {
5253 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
5259 data->m = m;
5261 cmd = &ring->cmd[ring->cur];
5262 paddr = data->cmd_paddr;
5265 cmd->code = code;
5266 cmd->flags = 0;
5267 cmd->qid = ring->qid;
5268 cmd->idx = ring->cur;
5269 memcpy(cmd->data, buf, size);
5271 desc->nsegs = 1;
5272 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
5273 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
5276 __func__, iwn_intr_str(cmd->code), cmd->code,
5277 cmd->flags, cmd->qid, cmd->idx);
5279 if (size > sizeof cmd->data) {
5280 bus_dmamap_sync(ring->data_dmat, data->map,
5283 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map,
5286 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
5290 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
5291 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
5293 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5295 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
5304 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5323 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5338 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5341 linkq.id = wn->id;
5354 sc->ntxchains);
5362 rs = (struct ieee80211_rateset *) &ni->ni_htrates;
5365 rs = &ni->ni_rates;
5369 /* Start at highest available bit-rate. */
5374 txrate = ni->ni_htrates.rs_nrates - 1;
5376 txrate = rs->rs_nrates - 1;
5388 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate];
5390 rate = IEEE80211_RV(rs->rs_rates[txrate]);
5392 /* Do rate -> PLCP config mapping */
5410 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie,
5411 * the next entry.) That way if the next entry is a non-MIMO
5415 IEEE80211_RV(le32toh(plcp)) > 7)
5418 /* Next retry at immediate lower bit-rate. */
5420 txrate--;
5424 * all MIMO rates (eg 5300 doing MCS23-15) then yes,
5432 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5438 * Broadcast node is used to send group-addressed and management frames.
5443 struct iwn_ops *ops = &sc->ops;
5444 struct ieee80211com *ic = &sc->sc_ic;
5450 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5452 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5456 node.id = sc->broadcast_id;
5458 if ((error = ops->add_node(sc, &node, async)) != 0)
5462 txant = IWN_LSB(sc->txchainmask);
5465 linkq.id = sc->broadcast_id;
5472 /* Use lowest mandatory bit-rate. */
5474 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
5479 /* Use same bit-rate for all TX retries. */
5484 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5492 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
5493 struct iwn_softc *sc = ic->ic_softc;
5498 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
5508 cmd.ac[aci].aifsn = ac->wmep_aifsn;
5509 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
5510 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
5512 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
5520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
5529 struct ieee80211com *ic = &sc->sc_ic;
5533 if (ic->ic_promisc > 0 || ic->ic_opmode == IEEE80211_M_MONITOR)
5534 sc->rxon->filter |= htole32(promisc_filter);
5536 sc->rxon->filter &= ~htole32(promisc_filter);
5542 struct iwn_softc *sc = ic->ic_softc;
5545 if (ic->ic_opmode == IEEE80211_M_MONITOR)
5549 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) {
5556 device_printf(sc->sc_dev,
5572 struct iwn_cmd_led led;
5574 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5578 if (sc->sc_is_scanning)
5582 /* Clear microcode LED ownership. */
5585 led.which = which;
5586 led.unit = htole32(10000); /* on/off in unit of 100ms */
5587 led.off = off;
5588 led.on = on;
5589 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
5602 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5606 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
5607 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
5608 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
5624 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5627 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
5628 cmd.bintval = htole16(ni->ni_intval);
5632 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
5634 cmd.binitval = htole32((uint32_t)(val - mod));
5637 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
5646 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5649 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
5650 __func__, sc->temp, temp);
5651 if (abs(temp - sc->temp) >= 3) {
5653 sc->temp = temp;
5666 /* Fixed-point arithmetic division using a n-bit fractional part. */
5671 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
5674 struct iwn_ucode_info *uc = &sc->ucode_info;
5682 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
5684 chan = sc->rxon->chan;
5685 is_chan_5ghz = (sc->rxon->flags & htole32(IWN_RXON_24GHZ)) == 0;
5694 maxpwr = sc->maxpwr5GHz;
5698 maxpwr = sc->maxpwr2GHz;
5704 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
5711 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
5714 if (chan <= 20) /* 1-20 */
5716 else if (chan <= 43) /* 34-43 */
5718 else if (chan <= 70) /* 44-70 */
5720 else if (chan <= 124) /* 71-124 */
5722 else /* 125-200 */
5727 /* Get channel sub-band. */
5729 if (sc->bands[i].lo != 0 &&
5730 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
5732 if (i == IWN_NBANDS) /* Can't happen in real-life. */
5734 chans = sc->bands[i].chans;
5736 "%s: chan %d sub-band=%d\n", __func__, chan, i);
5756 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
5759 __func__, tdiff, sc->temp, temp);
5762 /* Convert dBm to half-dBm. */
5763 maxchpwr = sc->maxpwr[chan] * 2;
5765 maxchpwr -= 6; /* MIMO 2T: -3dB */
5771 pwr -= 15; /* OFDM48: -7.5dB */
5773 pwr -= 17; /* OFDM54: -8.5dB */
5774 else if ((ridx % 8) == 7)
5775 pwr -= 20; /* OFDM60: -10dB */
5777 pwr -= 10; /* Others: -5dB */
5783 idx = gain - (pwr - power) - tdiff - vdiff;
5785 idx += (int32_t)le32toh(uc->atten[grp][c]);
5820 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5833 IWN_UCODE_API(sc->ucode_rev));
5834 if (IWN_UCODE_API(sc->ucode_rev) == 1)
5847 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
5851 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5853 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
5854 agc = (le16toh(phy->agc) >> 7) & 0x7f;
5858 rssi = MAX(rssi, phy->rssi[0]);
5860 rssi = MAX(rssi, phy->rssi[2]);
5862 rssi = MAX(rssi, phy->rssi[4]);
5866 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
5867 rssi - agc - IWN_RSSI_TO_DBM);
5868 return rssi - agc - IWN_RSSI_TO_DBM;
5874 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
5878 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5880 agc = (le32toh(phy->agc) >> 9) & 0x7f;
5882 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
5883 le16toh(phy->rssi[1]) & 0xff);
5884 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
5888 phy->rssi[0], phy->rssi[1], phy->rssi[2],
5889 rssi - agc - IWN_RSSI_TO_DBM);
5890 return rssi - agc - IWN_RSSI_TO_DBM;
5903 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
5909 return (nbant == 0) ? -127 : (total / nbant) - 107;
5918 struct iwn_ucode_info *uc = &sc->ucode_info;
5921 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5923 r1 = le32toh(uc->temp[0].chan20MHz);
5924 r2 = le32toh(uc->temp[1].chan20MHz);
5925 r3 = le32toh(uc->temp[2].chan20MHz);
5926 r4 = le32toh(sc->rawtemp);
5931 /* Sign-extend 23-bit R4 value to 32-bit. */
5932 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
5934 temp = (259 * (r4 - r2)) / (r3 - r1);
5947 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5953 temp = le32toh(sc->rawtemp);
5954 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
5955 temp = (temp / -5) + sc->temp_off;
5967 struct iwn_ops *ops = &sc->ops;
5968 struct iwn_calib_state *calib = &sc->calib;
5972 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
5976 calib->state = IWN_CALIB_STATE_INIT;
5977 calib->cck_state = IWN_CCK_STATE_HIFA;
5979 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
5980 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
5981 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
5982 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
5983 calib->cck_x4 = 125;
5984 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
5985 calib->energy_cck = sc->limits->energy_cck;
5992 if ((error = ops->init_gains(sc)) != 0)
6011 struct iwn_ops *ops = &sc->ops;
6012 struct iwn_calib_state *calib = &sc->calib;
6013 struct ieee80211com *ic = &sc->sc_ic;
6017 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6021 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
6022 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
6025 if (++calib->nbeacons < 20)
6029 val = MAX(calib->rssi[0], calib->rssi[1]);
6030 val = MAX(calib->rssi[2], val);
6033 sc->chainmask = sc->rxchainmask;
6035 if (val - calib->rssi[i] > 15 * 20)
6036 sc->chainmask &= ~(1 << i);
6039 __func__, sc->rxchainmask, sc->chainmask);
6042 if ((sc->chainmask & sc->txchainmask) == 0)
6043 sc->chainmask |= IWN_LSB(sc->txchainmask);
6045 (void)ops->set_gains(sc);
6046 calib->state = IWN_CALIB_STATE_RUN;
6050 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
6051 if (sc->sc_is_scanning)
6052 device_printf(sc->sc_dev,
6055 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1);
6058 /* Enable power-saving mode if requested by user. */
6059 if (ic->ic_flags & IEEE80211_F_PMGTON)
6062 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6071 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6086 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6089 cmd.code = sc->reset_noise_gain;
6100 struct iwn_calib_state *calib = &sc->calib;
6104 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6109 if (sc->chainmask & (1 << i))
6110 noise = MIN(calib->noise[i], noise);
6116 if (sc->chainmask & (1 << i)) {
6118 delta = (noise - (int32_t)calib->noise[i]) / 30;
6120 /* Limit to [-4.5dB,0]. */
6128 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
6135 struct iwn_calib_state *calib = &sc->calib;
6139 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
6142 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
6145 cmd.code = sc->noise_gain;
6149 ant = IWN_LSB(sc->rxchainmask);
6152 if (sc->chainmask & (1 << i)) {
6154 delta = ((int32_t)calib->noise[ant] -
6155 (int32_t)calib->noise[i]) / div;
6156 /* Limit to [-4.5dB,+4.5dB]. */
6157 cmd.gain[i - 1] = MIN(abs(delta), 3);
6159 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
6164 cmd.gain[0], cmd.gain[1], sc->chainmask);
6177 if ((val) < (max) - (inc)) \
6186 (val) -= (dec); \
6192 const struct iwn_sensitivity_limits *limits = sc->limits;
6193 struct iwn_calib_state *calib = &sc->calib;
6199 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6202 if ((rxena = le32toh(stats->general.load)) == 0){
6203 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__);
6208 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6209 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
6216 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
6217 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
6218 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
6219 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
6225 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
6226 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
6227 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
6228 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
6233 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
6237 calib->noise_samples[calib->cur_noise_sample] = val;
6238 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
6241 noise_ref = calib->noise_samples[0];
6243 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
6247 energy[i] = le32toh(stats->general.energy[i]);
6251 calib->energy_samples[calib->cur_energy_sample] = val;
6252 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
6255 energy_min = calib->energy_samples[0];
6257 energy_min = MAX(energy_min, calib->energy_samples[i]);
6261 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
6262 fa += le32toh(stats->cck.fa) - calib->fa_cck;
6269 calib->cck_state = IWN_CCK_STATE_HIFA;
6270 calib->low_fa = 0;
6272 if (calib->cck_x4 > 160) {
6273 calib->noise_ref = noise_ref;
6274 if (calib->energy_cck > 2)
6275 dec(calib->energy_cck, 2, energy_min);
6277 if (calib->cck_x4 < 160) {
6278 calib->cck_x4 = 161;
6281 inc(calib->cck_x4, 3, limits->max_cck_x4);
6283 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
6289 calib->cck_state = IWN_CCK_STATE_LOFA;
6290 calib->low_fa++;
6292 if (calib->cck_state != IWN_CCK_STATE_INIT &&
6293 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
6294 calib->low_fa > 100)) {
6295 inc(calib->energy_cck, 2, limits->min_energy_cck);
6296 dec(calib->cck_x4, 3, limits->min_cck_x4);
6297 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
6303 calib->low_fa = 0;
6304 calib->noise_ref = noise_ref;
6306 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
6308 dec(calib->energy_cck, 8, energy_min);
6310 calib->cck_state = IWN_CCK_STATE_INIT;
6316 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6325 struct iwn_calib_state *calib = &sc->calib;
6333 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
6334 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
6335 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
6336 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
6337 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
6340 cmd.corr_cck_x4 = htole16(calib->cck_x4);
6341 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
6342 cmd.energy_cck = htole16(calib->energy_cck);
6345 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc);
6349 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
6350 calib->ofdm_mrc_x4, calib->cck_x4,
6351 calib->cck_mrc_x4, calib->energy_cck);
6353 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
6377 struct iwn_calib_state *calib = &sc->calib;
6386 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck;
6387 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm;
6388 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht;
6396 * XXX go figure out what to do if ticks rolls over to -ve instead!
6397 * XXX go stab signed integer overflow undefined-ness in the face.
6400 delta_ticks = cur_ticks - sc->last_calib_ticks;
6418 thresh = sc->base_params->plcp_err_threshold * delta_msec;
6483 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
6486 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
6487 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
6493 skip_dtim = pmgt->skip_dtim;
6496 max = pmgt->intval[4];
6497 if (max == (uint32_t)-1)
6504 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
6546 if (sc->base_params->bt_sco_disable)
6559 if (sc->base_params->bt_session_2) {
6652 htflags |= IWN_RXON_HT_PROTMODE(vap->iv_curhtprotmode);
6655 switch (vap->iv_curhtprotmode) {
6673 return ((sc->rxon->filter & htole32(IWN_FILTER_BSS)) != 0);
6680 struct iwn_rxon *rxon = sc->rxon;
6682 cmd.flags = rxon->flags;
6683 cmd.filter = rxon->filter;
6684 cmd.ofdm_mask = rxon->ofdm_mask;
6685 cmd.cck_mask = rxon->cck_mask;
6686 cmd.ht_single_mask = rxon->ht_single_mask;
6687 cmd.ht_dual_mask = rxon->ht_dual_mask;
6688 cmd.rxchain = rxon->rxchain;
6698 struct iwn_rxon *rxon = sc->rxon;
6700 cmd.flags = rxon->flags;
6701 cmd.filter = rxon->filter;
6702 cmd.ofdm_mask = rxon->ofdm_mask;
6703 cmd.cck_mask = rxon->cck_mask;
6705 cmd.ht_single_mask = rxon->ht_single_mask;
6706 cmd.ht_dual_mask = rxon->ht_dual_mask;
6707 cmd.ht_triple_mask = rxon->ht_triple_mask;
6709 cmd.rxchain = rxon->rxchain;
6710 cmd.acquisition = rxon->acquisition;
6719 struct iwn_ops *ops = &sc->ops;
6725 error = ops->rxon_assoc(sc, async);
6727 device_printf(sc->sc_dev,
6733 if (sc->sc_is_scanning)
6734 device_printf(sc->sc_dev,
6738 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, async);
6740 device_printf(sc->sc_dev,
6752 device_printf(sc->sc_dev,
6760 if ((error = ops->set_txpower(sc, async)) != 0) {
6761 device_printf(sc->sc_dev,
6773 struct ieee80211com *ic = &sc->sc_ic;
6774 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6780 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
6782 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET)
6783 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) {
6784 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are"
6787 sc->base_params->calib_need,
6794 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) {
6797 device_printf(sc->sc_dev,
6801 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) {
6804 device_printf(sc->sc_dev,
6811 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
6815 device_printf(sc->sc_dev,
6823 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6824 IWN_UCODE_API(sc->ucode_rev) > 1) {
6825 txmask = htole32(sc->txchainmask);
6831 device_printf(sc->sc_dev,
6842 if (sc->base_params->bt_mode == IWN_BT_ADVANCED)
6844 if (sc->base_params->bt_mode == IWN_BT_SIMPLE)
6848 device_printf(sc->sc_dev,
6855 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
6856 memset(sc->rxon, 0, sizeof (struct iwn_rxon));
6857 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr;
6858 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr);
6859 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr);
6860 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
6861 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
6862 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
6863 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
6865 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST);
6866 switch (ic->ic_opmode) {
6868 sc->rxon->mode = IWN_MODE_STA;
6871 sc->rxon->mode = IWN_MODE_MONITOR;
6878 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */
6879 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */
6880 sc->rxon->ht_single_mask = 0xff;
6881 sc->rxon->ht_dual_mask = 0xff;
6882 sc->rxon->ht_triple_mask = 0xff;
6892 IWN_RXCHAIN_VALID(sc->rxchainmask) |
6893 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) |
6894 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains);
6895 sc->rxon->rxchain = htole16(rxchain);
6899 sc->rxchainmask,
6900 sc->nrxchains);
6902 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan));
6906 __func__, le32toh(sc->rxon->flags));
6908 device_printf(sc->sc_dev, "%s: could not send RXON\n",
6914 device_printf(sc->sc_dev,
6921 device_printf(sc->sc_dev,
6926 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
6954 struct ieee80211com *ic = &sc->sc_ic;
6959 if (! TAILQ_EMPTY(&ic->ic_vaps)) {
6960 vap = TAILQ_FIRST(&ic->ic_vaps);
6961 bintval = vap->iv_bss->ni_intval;
6965 * If it's non-zero, we should calculate the minimum of
7002 struct ieee80211com *ic = &sc->sc_ic;
7003 struct ieee80211_node *ni = vap->iv_bss;
7018 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7024 if (sc->sc_is_scanning) {
7025 device_printf(sc->sc_dev, "%s: called whilst scanning!\n",
7031 c = ic->ic_curchan;
7033 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7036 device_printf(sc->sc_dev,
7046 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
7047 hdr->quiet_threshold = htole16(1); /* min # of packets */
7052 hdr->max_svc = htole32(250 * 1024);
7066 hdr->pause_svc = htole32(scan_service_time);
7070 IWN_RXCHAIN_VALID(sc->rxchainmask) |
7071 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
7074 sc->hw_type == IWN_HW_REV_TYPE_4965) {
7078 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
7079 hdr->rxchain = htole16(rxchain);
7080 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
7083 tx->flags = htole32(IWN_TX_AUTO_SEQ);
7084 tx->id = sc->broadcast_id;
7085 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
7089 tx->rate = htole32(0xd);
7090 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
7092 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
7093 if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
7094 sc->rxon->associd && sc->rxon->chan > 14)
7095 tx->rate = htole32(0xd);
7098 tx->rate = htole32(10 | IWN_RFLAG_CCK);
7100 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
7103 txant = IWN_LSB(sc->txchainmask);
7104 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
7119 if (ss->ss_ssid[0].len != 0) {
7121 essid[0].len = ss->ss_ssid[0].len;
7122 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
7127 ss->ss_ssid[0].len,
7128 ss->ss_ssid[0].len,
7129 ss->ss_ssid[0].ssid);
7131 if (ss->ss_nssid > 0)
7140 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
7142 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
7143 IEEE80211_ADDR_COPY(wh->i_addr1, if_getbroadcastaddr(vap->iv_ifp));
7144 IEEE80211_ADDR_COPY(wh->i_addr2, if_getlladdr(vap->iv_ifp));
7145 IEEE80211_ADDR_COPY(wh->i_addr3, if_getbroadcastaddr(vap->iv_ifp));
7146 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
7147 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
7152 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
7154 if (ic->ic_htcaps & IEEE80211_HTC_HT)
7158 tx->len = htole16(frm - (uint8_t *)wh);
7172 * sending out probes -- setting this to a huge value will
7188 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN)
7189 hdr->crc_threshold = is_active ?
7192 hdr->crc_threshold = is_active ?
7196 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
7197 chan->flags = 0;
7198 if (ss->ss_nssid > 0)
7199 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
7200 chan->dsp_gain = 0x6e;
7206 if (c->ic_flags & IEEE80211_CHAN_PASSIVE)
7207 chan->flags |= htole32(IWN_CHAN_PASSIVE);
7209 chan->flags |= htole32(IWN_CHAN_ACTIVE);
7215 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid);
7222 chan->active = htole16(dwell_active);
7223 chan->passive = htole16(dwell_passive);
7226 chan->rf_gain = 0x3b;
7228 chan->rf_gain = 0x28;
7234 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
7236 hdr->crc_threshold, is_active, ss->ss_nssid);
7238 hdr->nchan++;
7240 buflen = (uint8_t *)chan - buf;
7241 hdr->len = htole16(buflen);
7243 if (sc->sc_is_scanning) {
7244 device_printf(sc->sc_dev,
7248 sc->sc_is_scanning = 1;
7251 hdr->nchan);
7255 callout_reset(&sc->scan_timeout, 5*hz, iwn_scan_timeout, sc);
7257 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7265 struct ieee80211com *ic = &sc->sc_ic;
7266 struct ieee80211_node *ni = vap->iv_bss;
7269 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7271 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7273 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7274 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7275 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7276 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7277 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7283 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
7284 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7285 else if (vap->iv_flags & IEEE80211_F_SHSLOT)
7286 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7288 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE)
7289 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7290 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7291 sc->rxon->cck_mask = 0;
7292 sc->rxon->ofdm_mask = 0x15;
7293 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7294 sc->rxon->cck_mask = 0x03;
7295 sc->rxon->ofdm_mask = 0;
7298 sc->rxon->cck_mask = 0x03;
7299 sc->rxon->ofdm_mask = 0x15;
7303 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ic->ic_curchan));
7306 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask,
7307 sc->rxon->ofdm_mask);
7310 device_printf(sc->sc_dev, "%s: could not send RXON\n",
7315 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7323 struct iwn_ops *ops = &sc->ops;
7324 struct ieee80211com *ic = &sc->sc_ic;
7325 struct ieee80211_node *ni = vap->iv_bss;
7329 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7331 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX];
7332 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
7333 /* Link LED blinks while monitoring. */
7338 device_printf(sc->sc_dev,
7344 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid);
7345 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd));
7346 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan);
7347 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
7348 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
7349 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
7351 /* As previously - short slot only on 5GHz */
7352 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
7353 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7354 else if (vap->iv_flags & IEEE80211_F_SHSLOT)
7355 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT);
7357 if (vap->iv_flags & IEEE80211_F_SHPREAMBLE)
7358 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE);
7359 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
7360 sc->rxon->cck_mask = 0;
7361 sc->rxon->ofdm_mask = 0x15;
7362 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
7363 sc->rxon->cck_mask = 0x03;
7364 sc->rxon->ofdm_mask = 0;
7367 sc->rxon->cck_mask = 0x0f;
7368 sc->rxon->ofdm_mask = 0x15;
7371 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, vap, ni->ni_chan));
7372 sc->rxon->filter |= htole32(IWN_FILTER_BSS);
7374 sc->rxon->chan, le32toh(sc->rxon->flags), vap->iv_curhtprotmode);
7377 device_printf(sc->sc_dev, "%s: could not send RXON\n",
7383 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
7388 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
7390 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
7391 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
7401 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
7405 error = ops->add_node(sc, &node, 1);
7407 device_printf(sc->sc_dev,
7414 device_printf(sc->sc_dev,
7421 device_printf(sc->sc_dev,
7427 sc->calib.state = IWN_CALIB_STATE_ASSOC;
7428 sc->calib_cnt = 0;
7429 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
7432 /* Link LED always on while associated. */
7435 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
7448 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7449 struct iwn_ops *ops = &sc->ops;
7456 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7461 if (wn->id == IWN_ID_UNDEFINED)
7465 node.id = wn->id;
7471 wn->id, tid, ssn);
7472 error = ops->add_node(sc, &node, 1);
7475 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
7479 * This function is called by upper layer on teardown of an HT-immediate
7485 struct ieee80211com *ic = ni->ni_ic;
7486 struct iwn_softc *sc = ic->ic_softc;
7487 struct iwn_ops *ops = &sc->ops;
7492 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7494 if (wn->id == IWN_ID_UNDEFINED)
7499 if (&ni->ni_rx_ampdu[tid] == rap)
7504 node.id = wn->id;
7508 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
7509 (void)ops->add_node(sc, &node, 1);
7511 sc->sc_ampdu_rx_stop(ni, rap);
7518 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7521 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7523 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
7524 if (sc->qid2tap[qid] == NULL)
7527 if (qid == sc->ntxqs) {
7532 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
7533 if (tap->txa_private == NULL) {
7534 device_printf(sc->sc_dev,
7538 sc->qid2tap[qid] = tap;
7539 *(int *)tap->txa_private = qid;
7540 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
7548 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7549 int qid = *(int *)tap->txa_private;
7550 uint8_t tid = tap->txa_tid;
7553 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7556 ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
7557 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
7561 sc->qid2tap[qid] = NULL;
7562 free(tap->txa_private, M_DEVBUF);
7563 tap->txa_private = NULL;
7565 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
7576 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid];
7577 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7578 struct iwn_ops *ops = &sc->ops;
7583 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7585 if (wn->id == IWN_ID_UNDEFINED)
7589 wn->disable_tid &= ~(1 << tid);
7591 node.id = wn->id;
7594 node.disable_tid = htole16(wn->disable_tid);
7595 error = ops->add_node(sc, &node, 1);
7601 qid = *(int *)tap->txa_private;
7603 __func__, wn->id, tid, tap->txa_start, qid);
7604 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
7614 struct iwn_softc *sc = ni->ni_ic->ic_softc;
7615 struct iwn_ops *ops = &sc->ops;
7616 uint8_t tid = tap->txa_tid;
7619 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7621 sc->sc_addba_stop(ni, tap);
7623 if (tap->txa_private == NULL)
7626 qid = *(int *)tap->txa_private;
7627 if (sc->txq[qid].queued != 0)
7631 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
7633 sc->qid2tap[qid] = NULL;
7634 free(tap->txa_private, M_DEVBUF);
7635 tap->txa_private = NULL;
7644 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7651 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
7652 wn->id << 4 | tid);
7654 /* Enable chain-building mode for the queue. */
7658 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7663 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
7666 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
7681 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7703 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7712 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
7713 wn->id << 4 | tid);
7715 /* Enable chain-building mode for the queue. */
7722 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
7727 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
7741 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7784 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
7785 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
7799 if (!(sc->base_params->calib_need & (1<<idx))) {
7805 if (sc->calibcmd[idx].buf == NULL) {
7814 sc->calibcmd[idx].len);
7815 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
7816 sc->calibcmd[idx].len, 0);
7818 device_printf(sc->sc_dev,
7833 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
7863 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
7864 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
7879 if (sc->eeprom_temp != 0)
7880 cmd.offset = htole16(sc->eeprom_temp);
7897 if (sc->eeprom_temp != 0) {
7898 cmd.offset_low = htole16(sc->eeprom_temp);
7899 cmd.offset_high = htole16(sc->eeprom_temp_high);
7904 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage);
7927 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
7930 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7931 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
7935 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
7947 iwn_mem_write(sc, sc->sched_base +
7950 iwn_mem_write(sc, sc->sched_base +
7957 /* Identify TX FIFO rings (0-7). */
7961 for (qid = 0; qid < 7; qid++) {
7979 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
7985 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__);
7990 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
7991 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
7995 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
8000 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT)
8010 iwn_mem_write(sc, sc->sched_base +
8013 iwn_mem_write(sc, sc->sched_base +
8020 /* Identify TX FIFO rings (0-7). */
8024 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) {
8027 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 };
8033 for (qid = 0; qid < 7; qid++) {
8034 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
8044 device_printf(sc->sc_dev,
8049 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
8053 device_printf(sc->sc_dev,
8059 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
8062 device_printf(sc->sc_dev,
8078 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8116 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
8132 struct iwn_fw_info *fw = &sc->fw;
8133 struct iwn_dma_info *dma = &sc->fw_dma;
8136 /* Copy initialization sections into pre-allocated DMA-safe memory. */
8137 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
8138 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8139 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
8140 fw->init.text, fw->init.textsz);
8141 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8146 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
8147 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
8149 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
8150 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
8154 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
8156 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
8164 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
8165 device_printf(sc->sc_dev,
8172 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
8173 sc->temp = iwn4965_get_temperature(sc);
8175 /* Copy runtime sections into pre-allocated DMA-safe memory. */
8176 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
8177 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8178 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
8179 fw->main.text, fw->main.textsz);
8180 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8185 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
8186 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
8188 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
8190 IWN_FW_UPDATED | fw->main.textsz);
8200 struct iwn_dma_info *dma = &sc->fw_dma;
8203 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8205 /* Copy firmware section into pre-allocated DMA-safe memory. */
8206 memcpy(dma->vaddr, section, size);
8207 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
8217 IWN_LOADDR(dma->paddr));
8219 IWN_HIADDR(dma->paddr) << 28 | size);
8232 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
8241 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8244 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
8245 &sc->fw.main : &sc->fw.init;
8248 fw->text, fw->textsz);
8250 device_printf(sc->sc_dev,
8256 fw->data, fw->datasz);
8258 device_printf(sc->sc_dev,
8279 ptr = (const uint32_t *)fw->data;
8282 sc->ucode_rev = rev;
8286 device_printf(sc->sc_dev,
8295 if (fw->size < hdrlen) {
8296 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8297 __func__, fw->size);
8300 fw->main.textsz = le32toh(*ptr++);
8301 fw->main.datasz = le32toh(*ptr++);
8302 fw->init.textsz = le32toh(*ptr++);
8303 fw->init.datasz = le32toh(*ptr++);
8304 fw->boot.textsz = le32toh(*ptr++);
8307 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
8308 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
8309 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8310 __func__, fw->size);
8315 fw->main.text = (const uint8_t *)ptr;
8316 fw->main.data = fw->main.text + fw->main.textsz;
8317 fw->init.text = fw->main.data + fw->main.datasz;
8318 fw->init.data = fw->init.text + fw->init.textsz;
8319 fw->boot.text = fw->init.data + fw->init.datasz;
8336 if (fw->size < sizeof (*hdr)) {
8337 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8338 __func__, fw->size);
8341 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
8342 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
8343 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
8344 __func__, le32toh(hdr->signature));
8347 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
8348 le32toh(hdr->build));
8349 sc->ucode_rev = le32toh(hdr->rev);
8355 altmask = le64toh(hdr->altmask);
8357 alt--; /* Downgrade. */
8361 end = (const uint8_t *)(fw->data + fw->size);
8363 /* Parse type-length-value fields. */
8366 len = le32toh(tlv->len);
8370 device_printf(sc->sc_dev,
8372 fw->size);
8376 if (tlv->alt != 0 && tlv->alt != htole16(alt))
8379 switch (le16toh(tlv->type)) {
8381 fw->main.text = ptr;
8382 fw->main.textsz = len;
8385 fw->main.data = ptr;
8386 fw->main.datasz = len;
8389 fw->init.text = ptr;
8390 fw->init.textsz = len;
8393 fw->init.data = ptr;
8394 fw->init.datasz = len;
8397 fw->boot.text = ptr;
8398 fw->boot.textsz = len;
8402 sc->sc_flags |= IWN_FLAG_ENH_SENS;
8407 sc->reset_noise_gain = tmp;
8408 sc->noise_gain = tmp + 1;
8412 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT;
8421 sc->tlv_feature_flags = le32toh(*ptr);
8425 sc->tlv_feature_flags);
8438 le16toh(tlv->type));
8442 "TLV type %d not handled\n", le16toh(tlv->type));
8445 next: /* TLV fields are 32-bit aligned. */
8454 struct iwn_fw_info *fw = &sc->fw;
8457 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8464 sc->fw_fp = firmware_get(sc->fwname);
8465 if (sc->fw_fp == NULL) {
8466 device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
8467 __func__, sc->fwname);
8473 fw->size = sc->fw_fp->datasize;
8474 fw->data = (const uint8_t *)sc->fw_fp->data;
8475 if (fw->size < sizeof (uint32_t)) {
8476 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
8477 __func__, fw->size);
8483 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
8488 device_printf(sc->sc_dev,
8494 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev);
8497 if (fw->main.textsz > sc->fw_text_maxsz ||
8498 fw->main.datasz > sc->fw_data_maxsz ||
8499 fw->init.textsz > sc->fw_text_maxsz ||
8500 fw->init.datasz > sc->fw_data_maxsz ||
8501 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
8502 (fw->boot.textsz & 3) != 0) {
8503 device_printf(sc->sc_dev, "%s: firmware sections too large\n",
8519 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
8520 sc->fw_fp = NULL;
8537 device_printf(sc->sc_dev,
8548 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8562 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
8563 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
8569 if (sc->base_params->pll_cfg_val)
8570 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val);
8578 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
8589 /* Disable L1-Active. */
8608 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
8626 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8628 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
8635 IWN_RFCFG_TYPE(sc->rfcfg) |
8636 IWN_RFCFG_STEP(sc->rfcfg) |
8637 IWN_RFCFG_DASH(sc->rfcfg));
8650 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8652 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
8654 IWN_RFCFG_TYPE(sc->rfcfg) |
8655 IWN_RFCFG_STEP(sc->rfcfg) |
8656 IWN_RFCFG_DASH(sc->rfcfg));
8665 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
8678 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
8682 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) {
8686 if (sc->base_params->additional_gp_drv_bit)
8688 sc->base_params->additional_gp_drv_bit);
8700 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8736 struct iwn_ops *ops = &sc->ops;
8739 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8745 device_printf(sc->sc_dev,
8757 /* Perform adapter-specific initialization. */
8758 if ((error = ops->nic_config(sc)) != 0)
8766 /* Set physical address of RX ring (256-byte aligned). */
8767 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
8768 /* Set physical address of RX status (16-byte aligned). */
8769 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
8779 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
8785 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8787 /* Set physical address of "keep warm" page (16-byte aligned). */
8788 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
8791 for (qid = 0; qid < sc->ntxqs; qid++) {
8792 struct iwn_tx_ring *txq = &sc->txq[qid];
8794 /* Set physical address of TX ring (256-byte aligned). */
8796 txq->desc_dma.paddr >> 8);
8801 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8816 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
8823 if (sc->base_params->shadow_reg_enable)
8826 if ((error = ops->load_firmware(sc)) != 0) {
8827 device_printf(sc->sc_dev,
8833 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
8834 device_printf(sc->sc_dev,
8839 /* Do post-firmware initialization. */
8841 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8843 return ops->post_alive(sc);
8851 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
8859 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8865 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
8869 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
8882 iwn_reset_rx_ring(sc, &sc->rxq);
8885 for (qid = 0; qid < sc->ntxqs; qid++)
8886 iwn_reset_tx_ring(sc, &sc->txq[qid]);
8902 struct ieee80211com *ic = &sc->sc_ic;
8903 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
8913 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; "
8914 "restarting\n", __func__, vap->iv_state);
8930 device_printf(sc->sc_dev,
8934 if (vap->iv_state >= IEEE80211_S_AUTH &&
8936 device_printf(sc->sc_dev,
8939 if (vap->iv_state >= IEEE80211_S_RUN &&
8941 device_printf(sc->sc_dev,
8955 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
8959 if (sc->sc_flags & IWN_FLAG_RUNNING)
8962 sc->sc_flags |= IWN_FLAG_RUNNING;
8965 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
8971 sc->int_mask = IWN_INT_MASK_DEF;
8972 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
8977 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
8984 device_printf(sc->sc_dev,
8994 device_printf(sc->sc_dev,
9002 device_printf(sc->sc_dev,
9008 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
9011 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__);
9018 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__);
9020 return (-1);
9041 if (!(sc->sc_flags & IWN_FLAG_RUNNING))
9044 sc->sc_is_scanning = 0;
9045 sc->sc_tx_timer = 0;
9046 callout_stop(&sc->watchdog_to);
9047 callout_stop(&sc->scan_timeout);
9048 callout_stop(&sc->calib_to);
9049 sc->sc_flags &= ~IWN_FLAG_RUNNING;
9069 struct iwn_softc *sc = ic->ic_softc;
9072 /* make the link LED blink while we're scanning */
9083 struct iwn_softc *sc = ic->ic_softc;
9084 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
9087 if (vap->iv_state == IEEE80211_S_RUN) {
9088 /* Set link LED to ON status if we are associated */
9100 struct iwn_softc *sc = ic->ic_softc;
9103 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__);
9110 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
9113 device_printf(sc->sc_dev,
9125 struct ieee80211vap *vap = ss->ss_vap;
9126 struct ieee80211com *ic = vap->iv_ic;
9127 struct iwn_softc *sc = ic->ic_softc;
9131 error = iwn_scan(sc, vap, ss, ic->ic_curchan);