75 #define scic_sds_controller_smu_register_read(controller, reg) \  argument
81 #define scic_sds_controller_smu_register_write(controller, reg, value) \  argument
93 #define scu_afe_register_write(controller, reg, value) \  argument
100 #define scu_afe_register_read(controller, reg) \  argument
111 #define scu_sgpio_peg0_register_read(controller, reg) \  argument
117 #define scu_sgpio_peg0_register_write(controller, reg, value) \  argument
129 #define scu_controller_viit_register_write(controller, index, reg, value) \  argument
146 #define scu_controller_scratch_ram_register_write(controller, index, value) \  argument
153 #define scu_controller_scratch_ram_register_read(controller, index) \  argument
159 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \  argument
166 #define scu_controller_scratch_ram_register_read_ext(controller, index) \  argument
182 #define SMU_PCP_WRITE(controller, value) \  argument
187 #define SMU_TCR_READ(controller, value) \  argument
192 #define SMU_TCR_WRITE(controller, value) \  argument
197 #define SMU_HTTBAR_WRITE(controller, address) \  argument
211 #define SMU_CQBAR_WRITE(controller, address) \  argument
225 #define SMU_CQGR_WRITE(controller, value) \  argument
230 #define SMU_CQGR_READ(controller, value) \  argument
235 #define SMU_CQPR_WRITE(controller, value) \  argument
240 #define SMU_RNCBAR_WRITE(controller, address) \  argument
254 #define SMU_AMR_READ(controller) \  argument
259 #define SMU_IMR_READ(controller) \  argument
264 #define SMU_IMR_WRITE(controller, mask) \  argument
269 #define SMU_ISR_READ(controller) \  argument
274 #define SMU_ISR_WRITE(controller, status) \  argument
279 #define SMU_ICC_READ(controller) \  argument
284 #define SMU_ICC_WRITE(controller, value) \  argument
289 #define SMU_CQC_WRITE(controller, value) \  argument
294 #define SMU_SMUSRCR_WRITE(controller, value) \  argument
299 #define SMU_TCA_WRITE(controller, index, value) \  argument
304 #define SMU_TCA_READ(controller, index) \  argument
309 #define SMU_DCC_READ(controller) \  argument
314 #define SMU_DFC_READ(controller) \  argument
319 #define SMU_SMUCSR_READ(controller) \  argument
324 #define SMU_CGUCR_READ(controller) \  argument
329 #define SMU_CGUCR_WRITE(controller, value) \  argument
334 #define SMU_CQPR_READ(controller) \  argument
345 #define scic_sds_controller_scu_register_read(controller, reg) \  argument
351 #define scic_sds_controller_scu_register_write(controller, reg, value) \  argument
368 #define scu_sdma_register_read(controller, reg) \  argument
374 #define scu_sdma_register_write(controller, reg, value) \  argument
386 #define SCU_PUFATHAR_WRITE(controller, address) \  argument
400 #define SCU_UFHBAR_WRITE(controller, address) \  argument
414 #define SCU_UFQC_READ(controller) \  argument
420 #define SCU_UFQC_WRITE(controller, value) \  argument
427 #define SCU_UFQPP_READ(controller) \  argument
433 #define SCU_UFQPP_WRITE(controller, value) \  argument
440 #define SCU_UFQGP_WRITE(controller, value) \  argument
447 #define SCU_PDMACR_READ(controller) \  argument
453 #define SCU_PDMACR_WRITE(controller, value) \  argument
460 #define SCU_CDMACR_READ(controller) \  argument
466 #define SCU_CDMACR_WRITE(controller, value) \  argument
481 #define scu_cram_register_read(controller, reg) \  argument
487 #define scu_cram_register_write(controller, reg, value) \  argument
499 #define scu_fbram_register_read(controller, reg) \  argument
505 #define scu_fbram_register_write(controller, reg, value) \  argument
525 #define SCU_SECR0_WRITE(controller, value) \  argument
539 #define SCU_SECR1_WRITE(controller, value) \  argument
556 #define scu_ptsg_register_read(controller, reg) \  argument
562 #define scu_ptsg_register_write(controller, reg, value) \  argument
574 #define SCU_PTSGCR_READ(controller) \  argument
580 #define SCU_PTSGCR_WRITE(controller, value) \  argument
587 #define SCU_PTSGRTC_READ(controller) \  argument