Lines Matching +full:slave +full:- +full:addr
1 /*-
62 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
63 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
64 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
73 static int intsmb_quick(device_t dev, u_char slave, int how);
74 static int intsmb_sendb(device_t dev, u_char slave, char byte);
75 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
76 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
77 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
78 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
79 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
80 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
81 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
82 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
116 if (isd->devid == devid) {
117 device_set_desc(dev, isd->description);
139 uint32_t addr;
149 * Comment from Linux i2c-piix4.c:
156 sc->type = SYS_RES_MEMORY;
157 addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_PM_OFF;
159 sc->type = SYS_RES_IOPORT;
160 addr = AMDSB_PMIO_INDEX;
164 rc = bus_set_resource(dev, sc->type, rid, addr,
170 res = bus_alloc_resource_any(dev, sc->type, &rid,
180 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
181 addr <<= 8;
182 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
183 enabled = (addr & AMDSB8_SMBUS_EN) != 0;
184 addr &= AMDSB8_SMBUS_ADDR_MASK;
186 addr = bus_read_1(res, AMDFCH41_PM_DECODE_EN0);
187 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
188 addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_SMBUS_OFF;
190 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
191 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
192 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
193 addr <<= 8;
196 bus_release_resource(dev, sc->type, rid, res);
197 bus_delete_resource(dev, sc->type, rid);
204 sc->io_rid = 0;
205 rc = bus_set_resource(dev, sc->type, sc->io_rid, addr,
211 sc->io_res = bus_alloc_resource_any(dev, sc->type, &sc->io_rid,
213 if (sc->io_res == NULL) {
217 sc->poll = 1;
227 if (sc->irq_hand)
228 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
229 if (sc->irq_res)
230 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
231 if (sc->io_res)
232 bus_release_resource(dev, sc->type, sc->io_rid,
233 sc->io_res);
234 mtx_destroy(&sc->lock);
245 sc->dev = dev;
247 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
249 sc->cfg_irq9 = 0;
250 sc->type = SYS_RES_IOPORT;
256 sc->cfg_irq9 = 1;
261 sc->sb8xx = 1;
266 sc->sb8xx = 1;
270 if (sc->sb8xx) {
278 sc->io_rid = PCI_BASE_ADDR_SMB;
279 sc->io_res = bus_alloc_resource_any(dev, sc->type, &sc->io_rid,
281 if (sc->io_res == NULL) {
287 if (sc->cfg_irq9) {
293 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
310 sc->poll == 0 ? "enabled" : "disabled");
313 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
316 sc->poll = 1;
319 if (sc->poll)
330 if (sc->cfg_irq9)
333 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
335 if (sc->irq_res == NULL) {
341 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
342 NULL, intsmb_rawintr, sc, &sc->irq_hand);
349 sc->isbusy = 0;
350 sc->smbus = device_add_child(dev, "smbus", DEVICE_UNIT_ANY);
351 if (sc->smbus == NULL) {
356 error = device_probe_and_attach(sc->smbus);
364 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
422 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
424 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
426 sc->isbusy)
429 sc->isbusy = 1;
430 /* Disable Interrupt in slave part. */
432 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
435 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
446 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
453 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
454 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
456 if (sc->isbusy) {
457 sc->isbusy = 0;
470 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
480 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
492 uint8_t addr;
496 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
498 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
509 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
513 device_printf(sc->dev, "ALART: ERROR\n");
515 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
516 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
519 /* Re-enable INTR from ALART. */
520 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
532 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
538 if (!sc->poll && !cold && !nointr)
540 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
550 * - SMB_ENOACK ("Unclaimed cycle"),
551 * - SMB_ETIMEOUT ("Host device time-out"),
552 * - SMB_EINVAL ("Illegal command field").
585 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
591 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
593 sc->isbusy = 0;
594 error = intsmb_error(sc->dev, status);
600 sc->isbusy = 0;
601 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
602 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
616 if (sc->poll || cold)
620 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
622 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
624 error = intsmb_error(sc->dev, status);
626 device_printf(sc->dev, "unknown cause why?\n");
628 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
636 sc->isbusy = 0;
638 /* Re-enable suppressed interrupt from slave part. */
639 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
647 intsmb_quick(device_t dev, u_char slave, int how)
653 data = slave;
673 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
681 intsmb_sendb(device_t dev, u_char slave, char byte)
692 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
693 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
701 intsmb_recvb(device_t dev, u_char slave, char *byte)
712 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
721 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
723 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
731 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
742 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
743 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
744 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
752 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
763 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
764 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
765 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
766 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
774 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
785 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
786 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
790 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
796 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
807 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
808 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
812 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
813 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
820 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
827 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
843 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
845 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
846 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
848 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
849 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
857 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
871 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
873 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
874 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
878 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
882 bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);