Lines Matching +full:memory +full:- +full:controllers

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
6  * Copyright (c) 2017-2018 Panasas
52 /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two
53  * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
54  * SMBus controllers. These are used for reading SPD data from the DIMMs, and
55  * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
57  * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
59  * The publicly available documentation for the iMC SMBus controllers can be
60  * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and
61  * (Has,broad)well-Xeon, respectively:
64  *      Sandybridge     xeon-e5-1600-2600-vol-2-datasheet.pdf
65  *      Ivybridge       xeon-e5-v2-datasheet-vol-2.pdf
66  *      Haswell         xeon-e5-v3-datasheet-vol-2.pdf
67  *      Broadwell       xeon-e5-v4-datasheet-vol-2.pdf
71  * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html
73  * The iMC SMBus controllers do not support interrupts (thus, they must be
78  * Because there are multiple SMBus controllers sharing the same PCI device,
81  * - "imcsmb" is an smbus(4)-compliant SMBus controller driver
83  * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of
88  * firmware. Therefore, when this driver accesses these SMBus controllers, the
90  * re-enabled when releasing the bus. Unfortunately, the details of how to do
91  * this are vendor-specific. Contact your motherboard vendor to get the
95  * manages the NVDIMM; for those which pre-date the standard, the operating
96  * system interacts with the NVDIMM controller using a vendor-proprietary API
102 /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */
108 /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
112 /* There are two SMBus controllers in each device. These define the registers
133 	    "Intel Sandybridge Xeon iMC 0 SMBus controllers"	},
135 	    "Intel Ivybridge Xeon iMC 0 SMBus controllers"	},
137 	    "Intel Haswell Xeon iMC 0 SMBus controllers"	},
139 	    "Intel Haswell Xeon iMC 1 SMBus controllers"	},
141 	    "Intel Broadwell Xeon iMC 0 SMBus controllers"	},
143 	    "Intel Broadwell Xeon iMC 1 SMBus controllers"	},
153  * children for the actual imcsmbX controllers. Set up the child's ivars to
171 	sc->dev = dev;
172 	sc->semaphore = 0;
220 	    pci_device->name != NULL;
222 		if (pci_dev_id == pci_device->id) {
223 			device_set_desc(dev, pci_device->name);
234  * Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and
235  * re-enable motherboard-specific DIMM temperature monitoring if needed. This
251 	 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM
255 	atomic_store_rel_int(&sc->semaphore, 0);
259  * Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and
260  * disable motherboard-specific DIMM temperature monitoring if needed. This gets
277 	/* We don't want to block. Use a simple test-and-set semaphore to
280 	if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) {
285 	 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM