Lines Matching full:controllers

53  * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
54  * SMBus controllers. These are used for reading SPD data from the DIMMs, and
55  * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
57  * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
59  * The publicly available documentation for the iMC SMBus controllers can be
73  * The iMC SMBus controllers do not support interrupts (thus, they must be
78  * Because there are multiple SMBus controllers sharing the same PCI device,
88  * firmware. Therefore, when this driver accesses these SMBus controllers, the
112 /* There are two SMBus controllers in each device. These define the registers
133 	    "Intel Sandybridge Xeon iMC 0 SMBus controllers"	},
135 	    "Intel Ivybridge Xeon iMC 0 SMBus controllers"	},
137 	    "Intel Haswell Xeon iMC 0 SMBus controllers"	},
139 	    "Intel Haswell Xeon iMC 1 SMBus controllers"	},
141 	    "Intel Broadwell Xeon iMC 0 SMBus controllers"	},
143 	    "Intel Broadwell Xeon iMC 1 SMBus controllers"	},
153  * children for the actual imcsmbX controllers. Set up the child's ivars to