Lines Matching +full:low +full:- +full:to +full:- +full:high
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * Generic I2C bit-banging code
42 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
136 device_set_desc(dev, "I2C bit-banging driver");
146 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
147 if (!sc->iicbus)
150 sc->scl_low_timeout = DEFAULT_SCL_LOW_TIMEOUT;
154 "delay", CTLFLAG_RD, &sc->udelay,
159 "scl_low_timeout", CTLFLAG_RWTUN, &sc->scl_low_timeout,
160 0, "SCL low timeout, microseconds");
163 "io_latency", CTLFLAG_RWTUN, &sc->io_latency,
185 if (child == sc->iicbus)
186 sc->iicbus = NULL;
200 retval += printf(" on %s master-only\n",
219 &i2c_debug, 0, "Enable i2c bit-banging driver debug");
240 /* Spin for up to 1 ms, then switch to pause. */
243 timeout = now + sc->scl_low_timeout * SBT_1US;
252 pause_sbt("iicbb-scl-low", SBT_1MS, 0, C_PREL(2));
262 /* Start the high phase of the clock. */
268 * Precondition: SCL is low.
270 * - set SDA to the value;
271 * - release SCL and wait until it's high.
272 * The caller is responsible for keeping SCL high for udelay.
274 * There should be a data set-up time, 250 ns minimum, between setting
284 * End the high phase of the clock and wait out the low phase
293 * Precondition: SCL is high.
295 * - pull SCL low and hold for udelay.
298 DELAY(sc->udelay);
310 DELAY(sc->udelay);
320 * (set it to high level) and then release the CLOCK line.
321 * Now it must wait for the SLAVE to pull the DATA line low.
326 * When the SLAVE has pulled this line low the MASTER will take the CLOCK
327 * line low and then the SLAVE will release the SDA (data) line.
343 /* Sample SDA until ACK (low) or udelay runs out. */
344 for (t = 0; t < sc->udelay; t++) {
351 DELAY(sc->udelay - t);
354 I2C_DEBUG(printf("%c ", noack ? '-' : '+'));
363 for (i = 7; i >= 0; i--) {
382 * We do not use iicbb_clockin() here because we need to release SDA
387 for (i = 7; i >= 0; i--) {
394 DELAY((sc->udelay + 1) / 2);
397 DELAY((sc->udelay + 1) / 2);
402 * Send master->slave ACK (low) for more data,
403 * NoACK (high) otherwise.
406 I2C_DEBUG(printf("r%02x%c ", *data, last ? '-' : '+'));
432 /* SCL must be high on the idle bus. */
443 /* SDA will go low in the middle of the SCL high phase. */
444 DELAY((sc->udelay + 1) / 2);
448 * SDA must be high after the earlier stop condition or the end
456 /* Start: SDA high->low. */
459 /* Wait the second half of the SCL high phase. */
460 DELAY((sc->udelay + 1) / 2);
462 /* Pull SCL low to keep the bus reserved. */
497 * Stop: SDA goes from low to high in the middle of the SCL high phase.
502 DELAY((sc->udelay + 1) / 2);
504 DELAY((sc->udelay + 1) / 2);
527 len--;
548 len--;
577 * udelay is half a period, the clock is held high or low for this long.
579 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
580 period = 1000000 / 2 / busfreq; /* Hz -> uS */
581 period -= sc->io_latency;
582 sc->udelay = MAX(period, 1);