Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 static s32 igc_wait_autoneg(struct igc_hw *hw);
13 * igc_init_phy_ops_generic - Initialize PHY function pointers
14 * @hw: pointer to the HW structure
16 * Setups up the function pointers to no-op functions
18 void igc_init_phy_ops_generic(struct igc_hw *hw) in igc_init_phy_ops_generic() argument
20 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic()
24 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
30 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
32 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
33 phy->ops.release = igc_null_phy_generic; in igc_init_phy_ops_generic()
34 phy->ops.reset = igc_null_ops_generic; in igc_init_phy_ops_generic()
35 phy->ops.set_d0_lplu_state = igc_null_lplu_state; in igc_init_phy_ops_generic()
36 phy->ops.set_d3_lplu_state = igc_null_lplu_state; in igc_init_phy_ops_generic()
37 phy->ops.write_reg = igc_null_write_reg; in igc_init_phy_ops_generic()
38 phy->ops.write_reg_locked = igc_null_write_reg; in igc_init_phy_ops_generic()
39 phy->ops.write_reg_page = igc_null_write_reg; in igc_init_phy_ops_generic()
40 phy->ops.power_up = igc_null_phy_generic; in igc_init_phy_ops_generic()
41 phy->ops.power_down = igc_null_phy_generic; in igc_init_phy_ops_generic()
45 * igc_null_set_page - No-op function, return 0
46 * @hw: pointer to the HW structure
49 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_set_page() argument
57 * igc_null_read_reg - No-op function, return 0
58 * @hw: pointer to the HW structure
62 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_read_reg() argument
70 * igc_null_phy_generic - No-op function, return void
71 * @hw: pointer to the HW structure
73 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw) in igc_null_phy_generic() argument
80 * igc_null_lplu_state - No-op function, return 0
81 * @hw: pointer to the HW structure
84 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_lplu_state() argument
92 * igc_null_write_reg - No-op function, return 0
93 * @hw: pointer to the HW structure
97 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_write_reg() argument
105 * igc_check_reset_block_generic - Check if PHY reset is blocked
106 * @hw: pointer to the HW structure
112 s32 igc_check_reset_block_generic(struct igc_hw *hw) in igc_check_reset_block_generic() argument
118 manc = IGC_READ_REG(hw, IGC_MANC); in igc_check_reset_block_generic()
125 * igc_get_phy_id - Retrieve the PHY ID and revision
126 * @hw: pointer to the HW structure
131 s32 igc_get_phy_id(struct igc_hw *hw) in igc_get_phy_id() argument
133 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
139 if (!phy->ops.read_reg) in igc_get_phy_id()
142 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
146 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
148 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
152 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
153 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
159 * igc_read_phy_reg_mdic - Read MDI control register
160 * @hw: pointer to the HW structure
167 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) in igc_read_phy_reg_mdic() argument
169 struct igc_phy_info *phy = &hw->phy; in igc_read_phy_reg_mdic()
176 return -IGC_ERR_PARAM; in igc_read_phy_reg_mdic()
179 /* Set up Op-code, Phy Address, and register offset in the MDI in igc_read_phy_reg_mdic()
184 (phy->addr << IGC_MDIC_PHY_SHIFT) | in igc_read_phy_reg_mdic()
187 IGC_WRITE_REG(hw, IGC_MDIC, mdic); in igc_read_phy_reg_mdic()
195 mdic = IGC_READ_REG(hw, IGC_MDIC); in igc_read_phy_reg_mdic()
201 return -IGC_ERR_PHY; in igc_read_phy_reg_mdic()
205 return -IGC_ERR_PHY; in igc_read_phy_reg_mdic()
208 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", in igc_read_phy_reg_mdic()
211 return -IGC_ERR_PHY; in igc_read_phy_reg_mdic()
219 * igc_write_phy_reg_mdic - Write MDI control register
220 * @hw: pointer to the HW structure
226 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) in igc_write_phy_reg_mdic() argument
228 struct igc_phy_info *phy = &hw->phy; in igc_write_phy_reg_mdic()
235 return -IGC_ERR_PARAM; in igc_write_phy_reg_mdic()
238 /* Set up Op-code, Phy Address, and register offset in the MDI in igc_write_phy_reg_mdic()
244 (phy->addr << IGC_MDIC_PHY_SHIFT) | in igc_write_phy_reg_mdic()
247 IGC_WRITE_REG(hw, IGC_MDIC, mdic); in igc_write_phy_reg_mdic()
255 mdic = IGC_READ_REG(hw, IGC_MDIC); in igc_write_phy_reg_mdic()
261 return -IGC_ERR_PHY; in igc_write_phy_reg_mdic()
265 return -IGC_ERR_PHY; in igc_write_phy_reg_mdic()
268 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", in igc_write_phy_reg_mdic()
271 return -IGC_ERR_PHY; in igc_write_phy_reg_mdic()
278 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
279 * @hw: pointer to the HW structure
281 * Reads the MII auto-neg advertisement register and/or the 1000T control
282 * register and if the PHY is already setup for auto-negotiation, then
283 * return successful. Otherwise, setup advertisement and flow control to
284 * the appropriate values for the wanted auto-negotiation.
286 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) in igc_phy_setup_autoneg() argument
288 struct igc_phy_info *phy = &hw->phy; in igc_phy_setup_autoneg()
296 phy->autoneg_advertised &= phy->autoneg_mask; in igc_phy_setup_autoneg()
298 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ in igc_phy_setup_autoneg()
299 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
303 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { in igc_phy_setup_autoneg()
304 /* Read the MII 1000Base-T Control Register (Address 9). */ in igc_phy_setup_autoneg()
305 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
311 if (phy->autoneg_mask & ADVERTISE_2500_FULL) { in igc_phy_setup_autoneg()
312 /* Read the MULTI GBT AN Control Register - reg 7.32 */ in igc_phy_setup_autoneg()
313 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << in igc_phy_setup_autoneg()
329 /* First we clear all the 10/100 mb speed bits in the Auto-Neg in igc_phy_setup_autoneg()
331 * the 1000Base-T Control Register (Address 9). in igc_phy_setup_autoneg()
339 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); in igc_phy_setup_autoneg()
342 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { in igc_phy_setup_autoneg()
348 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { in igc_phy_setup_autoneg()
354 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { in igc_phy_setup_autoneg()
360 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { in igc_phy_setup_autoneg()
366 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) in igc_phy_setup_autoneg()
370 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { in igc_phy_setup_autoneg()
376 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) in igc_phy_setup_autoneg()
380 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { in igc_phy_setup_autoneg()
387 /* Check for a software override of the flow control settings, and in igc_phy_setup_autoneg()
389 * auto-negotiation is enabled, then software will have to set the in igc_phy_setup_autoneg()
390 * "PAUSE" bits to the correct value in the Auto-Negotiation in igc_phy_setup_autoneg()
391 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- in igc_phy_setup_autoneg()
395 * 0: Flow control is completely disabled in igc_phy_setup_autoneg()
396 * 1: Rx flow control is enabled (we can receive pause frames in igc_phy_setup_autoneg()
398 * 2: Tx flow control is enabled (we can send pause frames in igc_phy_setup_autoneg()
400 * 3: Both Rx and Tx flow control (symmetric) are enabled. in igc_phy_setup_autoneg()
401 * other: No software override. The flow control configuration in igc_phy_setup_autoneg()
404 switch (hw->fc.current_mode) { in igc_phy_setup_autoneg()
406 /* Flow control (Rx & Tx) is completely disabled by a in igc_phy_setup_autoneg()
407 * software over-ride. in igc_phy_setup_autoneg()
412 /* Rx Flow control is enabled, and Tx Flow control is in igc_phy_setup_autoneg()
413 * disabled, by a software over-ride. in igc_phy_setup_autoneg()
419 * hw's ability to send PAUSE frames. in igc_phy_setup_autoneg()
424 /* Tx Flow control is enabled, and Rx Flow control is in igc_phy_setup_autoneg()
425 * disabled, by a software over-ride. in igc_phy_setup_autoneg()
431 /* Flow control (both Rx and Tx) is enabled by a software in igc_phy_setup_autoneg()
432 * over-ride. in igc_phy_setup_autoneg()
437 DEBUGOUT("Flow control param set incorrectly\n"); in igc_phy_setup_autoneg()
438 return -IGC_ERR_CONFIG; in igc_phy_setup_autoneg()
441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
445 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
447 if (phy->autoneg_mask & ADVERTISE_1000_FULL) in igc_phy_setup_autoneg()
448 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
451 if (phy->autoneg_mask & ADVERTISE_2500_FULL) in igc_phy_setup_autoneg()
452 ret_val = phy->ops.write_reg(hw, in igc_phy_setup_autoneg()
462 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
463 * @hw: pointer to the HW structure
470 static s32 igc_copper_link_autoneg(struct igc_hw *hw) in igc_copper_link_autoneg() argument
472 struct igc_phy_info *phy = &hw->phy; in igc_copper_link_autoneg()
481 phy->autoneg_advertised &= phy->autoneg_mask; in igc_copper_link_autoneg()
486 if (!phy->autoneg_advertised) in igc_copper_link_autoneg()
487 phy->autoneg_advertised = phy->autoneg_mask; in igc_copper_link_autoneg()
489 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); in igc_copper_link_autoneg()
490 ret_val = igc_phy_setup_autoneg(hw); in igc_copper_link_autoneg()
492 DEBUGOUT("Error Setting up Auto-Negotiation\n"); in igc_copper_link_autoneg()
495 DEBUGOUT("Restarting Auto-Neg\n"); in igc_copper_link_autoneg()
497 /* Restart auto-negotiation by setting the Auto Neg Enable bit and in igc_copper_link_autoneg()
500 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igc_copper_link_autoneg()
505 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igc_copper_link_autoneg()
509 /* Does the user want to wait for Auto-Neg to complete here, or in igc_copper_link_autoneg()
512 if (phy->autoneg_wait_to_complete) { in igc_copper_link_autoneg()
513 ret_val = igc_wait_autoneg(hw); in igc_copper_link_autoneg()
520 hw->mac.get_link_status = true; in igc_copper_link_autoneg()
526 * igc_setup_copper_link_generic - Configure copper link settings
527 * @hw: pointer to the HW structure
529 * Calls the appropriate function to configure the link for auto-neg or forced
531 * to configure collision distance and flow control are called. If link is
532 * not established, we return -IGC_ERR_PHY (-2).
534 s32 igc_setup_copper_link_generic(struct igc_hw *hw) in igc_setup_copper_link_generic() argument
541 if (hw->mac.autoneg) { in igc_setup_copper_link_generic()
542 /* Setup autoneg and flow control advertisement and perform in igc_setup_copper_link_generic()
545 ret_val = igc_copper_link_autoneg(hw); in igc_setup_copper_link_generic()
553 ret_val = hw->phy.ops.force_speed_duplex(hw); in igc_setup_copper_link_generic()
563 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, in igc_setup_copper_link_generic()
570 hw->mac.ops.config_collision_dist(hw); in igc_setup_copper_link_generic()
571 ret_val = igc_config_fc_after_link_up_generic(hw); in igc_setup_copper_link_generic()
580 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
581 * @hw: pointer to the HW structure
584 * Forces speed and duplex on the PHY by doing the following: disable flow
586 * disable auto-negotiation, configure duplex, configure speed, configure
587 * the collision distance, write configuration to CTRL register. The
591 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl) in igc_phy_force_speed_duplex_setup() argument
593 struct igc_mac_info *mac = &hw->mac; in igc_phy_force_speed_duplex_setup()
594 u32 ctrl; in igc_phy_force_speed_duplex_setup() local
598 /* Turn off flow control when forcing speed/duplex */ in igc_phy_force_speed_duplex_setup()
599 hw->fc.current_mode = igc_fc_none; in igc_phy_force_speed_duplex_setup()
602 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_phy_force_speed_duplex_setup()
603 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); in igc_phy_force_speed_duplex_setup()
604 ctrl &= ~IGC_CTRL_SPD_SEL; in igc_phy_force_speed_duplex_setup()
607 ctrl &= ~IGC_CTRL_ASDE; in igc_phy_force_speed_duplex_setup()
613 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) { in igc_phy_force_speed_duplex_setup()
614 ctrl &= ~IGC_CTRL_FD; in igc_phy_force_speed_duplex_setup()
618 ctrl |= IGC_CTRL_FD; in igc_phy_force_speed_duplex_setup()
624 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) { in igc_phy_force_speed_duplex_setup()
625 ctrl |= IGC_CTRL_SPD_100; in igc_phy_force_speed_duplex_setup()
630 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100); in igc_phy_force_speed_duplex_setup()
635 hw->mac.ops.config_collision_dist(hw); in igc_phy_force_speed_duplex_setup()
637 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_phy_force_speed_duplex_setup()
641 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3
642 * @hw: pointer to the HW structure
654 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active) in igc_set_d3_lplu_state_generic() argument
656 struct igc_phy_info *phy = &hw->phy; in igc_set_d3_lplu_state_generic()
662 if (!hw->phy.ops.read_reg) in igc_set_d3_lplu_state_generic()
665 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data); in igc_set_d3_lplu_state_generic()
671 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
680 if (phy->smart_speed == igc_smart_speed_on) { in igc_set_d3_lplu_state_generic()
681 ret_val = phy->ops.read_reg(hw, in igc_set_d3_lplu_state_generic()
688 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
693 } else if (phy->smart_speed == igc_smart_speed_off) { in igc_set_d3_lplu_state_generic()
694 ret_val = phy->ops.read_reg(hw, in igc_set_d3_lplu_state_generic()
701 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
707 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) || in igc_set_d3_lplu_state_generic()
708 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) || in igc_set_d3_lplu_state_generic()
709 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) { in igc_set_d3_lplu_state_generic()
711 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
717 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG, in igc_set_d3_lplu_state_generic()
723 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG, in igc_set_d3_lplu_state_generic()
731 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
732 * @hw: pointer to the HW structure
738 s32 igc_check_downshift_generic(struct igc_hw *hw) in igc_check_downshift_generic() argument
740 struct igc_phy_info *phy = &hw->phy; in igc_check_downshift_generic()
745 switch (phy->type) { in igc_check_downshift_generic()
749 phy->speed_downgraded = false; in igc_check_downshift_generic()
757 * igc_wait_autoneg - Wait for auto-neg completion
758 * @hw: pointer to the HW structure
760 * Waits for auto-negotiation to complete or for the auto-negotiation time
763 static s32 igc_wait_autoneg(struct igc_hw *hw) in igc_wait_autoneg() argument
770 if (!hw->phy.ops.read_reg) in igc_wait_autoneg()
774 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { in igc_wait_autoneg()
775 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
778 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
786 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation in igc_wait_autoneg()
793 * igc_phy_has_link_generic - Polls PHY for link
794 * @hw: pointer to the HW structure
801 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations, in igc_phy_has_link_generic() argument
809 if (!hw->phy.ops.read_reg) in igc_phy_has_link_generic()
817 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link_generic()
828 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link_generic()
845 * igc_phy_hw_reset_generic - PHY hardware reset
846 * @hw: pointer to the HW structure
853 s32 igc_phy_hw_reset_generic(struct igc_hw *hw) in igc_phy_hw_reset_generic() argument
855 struct igc_phy_info *phy = &hw->phy; in igc_phy_hw_reset_generic()
857 u32 ctrl, timeout = 10000, phpm = 0; in igc_phy_hw_reset_generic() local
861 if (phy->ops.check_reset_block) { in igc_phy_hw_reset_generic()
862 ret_val = phy->ops.check_reset_block(hw); in igc_phy_hw_reset_generic()
867 ret_val = phy->ops.acquire(hw); in igc_phy_hw_reset_generic()
871 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_phy_hw_reset_generic()
873 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_phy_hw_reset_generic()
874 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); in igc_phy_hw_reset_generic()
875 IGC_WRITE_FLUSH(hw); in igc_phy_hw_reset_generic()
877 usec_delay(phy->reset_delay_us); in igc_phy_hw_reset_generic()
879 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_phy_hw_reset_generic()
880 IGC_WRITE_FLUSH(hw); in igc_phy_hw_reset_generic()
885 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_phy_hw_reset_generic()
886 timeout--; in igc_phy_hw_reset_generic()
893 phy->ops.release(hw); in igc_phy_hw_reset_generic()
899 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
900 * @hw: pointer to the HW structure
906 void igc_power_up_phy_copper(struct igc_hw *hw) in igc_power_up_phy_copper() argument
911 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_up_phy_copper()
913 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igc_power_up_phy_copper()
918 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
919 * @hw: pointer to the HW structure
925 void igc_power_down_phy_copper(struct igc_hw *hw) in igc_power_down_phy_copper() argument
930 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_down_phy_copper()
932 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igc_power_down_phy_copper()
936 * igc_write_phy_reg_gpy - Write GPY PHY register
937 * @hw: pointer to the HW structure
944 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) in igc_write_phy_reg_gpy() argument
954 ret_val = hw->phy.ops.acquire(hw); in igc_write_phy_reg_gpy()
957 ret_val = igc_write_phy_reg_mdic(hw, offset, data); in igc_write_phy_reg_gpy()
960 hw->phy.ops.release(hw); in igc_write_phy_reg_gpy()
962 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, in igc_write_phy_reg_gpy()
969 * igc_read_phy_reg_gpy - Read GPY PHY register
970 * @hw: pointer to the HW structure
978 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) in igc_read_phy_reg_gpy() argument
988 ret_val = hw->phy.ops.acquire(hw); in igc_read_phy_reg_gpy()
991 ret_val = igc_read_phy_reg_mdic(hw, offset, data); in igc_read_phy_reg_gpy()
994 hw->phy.ops.release(hw); in igc_read_phy_reg_gpy()
996 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, in igc_read_phy_reg_gpy()
1004 * __igc_access_xmdio_reg - Read/write XMDIO register
1005 * @hw: pointer to the HW structure
1011 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, in __igc_access_xmdio_reg() argument
1018 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); in __igc_access_xmdio_reg()
1022 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); in __igc_access_xmdio_reg()
1026 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | in __igc_access_xmdio_reg()
1032 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); in __igc_access_xmdio_reg()
1034 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); in __igc_access_xmdio_reg()
1039 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); in __igc_access_xmdio_reg()
1047 * igc_read_xmdio_reg - Read XMDIO register
1048 * @hw: pointer to the HW structure
1053 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data) in igc_read_xmdio_reg() argument
1057 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); in igc_read_xmdio_reg()
1061 * igc_write_xmdio_reg - Write XMDIO register
1062 * @hw: pointer to the HW structure
1067 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data) in igc_write_xmdio_reg() argument
1071 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); in igc_write_xmdio_reg()