Lines Matching +full:rx +full:- +full:threshold
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
154 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
161 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
162 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
163 #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
164 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
166 #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
167 #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
168 #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
212 #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 /* 1000/H is not supported, nor spec-compliant. */
327 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
346 /* GPY211 - I225 defines */
450 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */
451 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
452 #define IGC_ICR_RXO 0x00000040 /* Rx overrun */
453 #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
454 #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
471 #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
472 #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
473 #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
474 #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
491 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
505 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
506 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
509 #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */
510 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
521 #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
522 #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
523 #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
524 #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
534 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
535 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
538 #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
539 #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
540 #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
541 #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
555 #define IGC_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
556 #define IGC_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
557 #define IGC_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
638 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
639 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
645 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
735 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
777 #define IGC_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
778 #define IGC_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
779 #define IGC_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
788 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
792 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
871 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
881 /* 1000BASE-T Control Register */
897 /* 1000BASE-T Status Register */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1224 /* DMA Coalescing Rx Threshold */
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1234 /* DMA Coalescing Transmit Threshold */
1239 /* Rx Traffic Rate Threshold */
1241 /* Rx packet rate in current window */
1244 /* DMA Coal Rx Traffic Current Count */
1247 /* Flow ctrl Rx Threshold High val */
1253 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1254 #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out
1288 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */