Lines Matching +full:asym +full:- +full:pause
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
172 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 /* 1000/H is not supported, nor spec-compliant. */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
346 /* GPY211 - I225 defines */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
624 #define IGC_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
625 #define IGC_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
626 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
856 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
857 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
868 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
869 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
881 /* 1000BASE-T Control Register */
882 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
897 /* 1000BASE-T Status Register */
899 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out