Lines Matching +full:num +full:- +full:vectors
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2023-2024 Google LLC
37 return (be32toh(bus_read_4(priv->reg_bar, offset)));
43 bus_write_4(priv->reg_bar, offset, htobe32(val));
49 bus_write_4(priv->db_bar, offset, htobe32(val));
55 bus_write_4(priv->db_bar, offset, val);
90 device_t dev = priv->dev;
104 &dma->tag);
111 err = bus_dmamem_alloc(dma->tag, (void **) &dma->cpu_addr,
113 &dma->map);
120 /* An address set by the callback will never be -1 */
121 dma->bus_addr = (bus_addr_t)-1;
122 err = bus_dmamap_load(dma->tag, dma->map, dma->cpu_addr, size,
123 gve_dmamap_load_callback, &dma->bus_addr, BUS_DMA_NOWAIT);
124 if (err != 0 || dma->bus_addr == (bus_addr_t)-1) {
132 bus_dmamem_free(dma->tag, dma->cpu_addr, dma->map);
134 bus_dma_tag_destroy(dma->tag);
136 dma->tag = NULL;
144 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
145 bus_dmamap_unload(dma->tag, dma->map);
146 bus_dmamem_free(dma->tag, dma->cpu_addr, dma->map);
147 bus_dma_tag_destroy(dma->tag);
155 device_t dev = priv->dev;
169 &dma->tag);
176 err = bus_dmamap_create(dma->tag, BUS_DMA_COHERENT, &dma->map);
183 /* An address set by the callback will never be -1 */
184 dma->bus_addr = (bus_addr_t)-1;
185 err = bus_dmamap_load(dma->tag, dma->map, dma->cpu_addr, size,
186 gve_dmamap_load_callback, &dma->bus_addr, BUS_DMA_WAITOK);
187 if (err != 0 || dma->bus_addr == (bus_addr_t)-1) {
196 bus_dmamap_destroy(dma->tag, dma->map);
198 bus_dma_tag_destroy(dma->tag);
200 dma->tag = NULL;
208 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
209 bus_dmamap_unload(dma->tag, dma->map);
210 bus_dmamap_destroy(dma->tag, dma->map);
211 bus_dma_tag_destroy(dma->tag);
219 taskqueue_enqueue(priv->service_tq, &priv->service_task);
232 if (priv->irq_tbl == NULL) {
233 device_printf(priv->dev, "No irq table, nothing to free\n");
237 num_irqs = priv->tx_cfg.num_queues + priv->rx_cfg.num_queues + 1;
240 irq = &priv->irq_tbl[i];
241 if (irq->res == NULL)
244 rid = rman_get_rid(irq->res);
246 rc = bus_teardown_intr(priv->dev, irq->res, irq->cookie);
248 device_printf(priv->dev, "Failed to teardown irq num %d\n",
251 rc = bus_release_resource(priv->dev, SYS_RES_IRQ,
252 rid, irq->res);
254 device_printf(priv->dev, "Failed to release irq num %d\n",
257 irq->res = NULL;
258 irq->cookie = NULL;
261 free(priv->irq_tbl, M_GVE);
262 priv->irq_tbl = NULL;
265 pci_release_msi(priv->dev);
271 int num_tx = priv->tx_cfg.num_queues;
272 int num_rx = priv->rx_cfg.num_queues;
284 if (pci_alloc_msix(priv->dev, &got_nvecs) != 0) {
285 device_printf(priv->dev, "Failed to acquire any msix vectors\n");
289 device_printf(priv->dev, "Tried to acquire %d msix vectors, got only %d\n",
296 device_printf(priv->dev, "Enabled MSIX with %d vectors\n", got_nvecs);
298 priv->irq_tbl = malloc(sizeof(struct gve_irq) * req_nvecs, M_GVE,
302 irq = &priv->irq_tbl[i];
303 tx = &priv->tx[i];
304 com = &tx->com;
307 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
309 if (irq->res == NULL) {
310 device_printf(priv->dev, "Failed to alloc irq %d for Tx queue %d\n",
316 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
318 &priv->tx[i], &irq->cookie);
320 device_printf(priv->dev, "Failed to setup irq %d for Tx queue %d, "
325 bus_describe_intr(priv->dev, irq->res, irq->cookie, "tx%d", i);
326 com->ntfy_id = i;
330 irq = &priv->irq_tbl[i + j];
331 rx = &priv->rx[j];
332 com = &rx->com;
335 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
337 if (irq->res == NULL) {
338 device_printf(priv->dev,
344 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
346 &priv->rx[j], &irq->cookie);
348 device_printf(priv->dev, "Failed to setup irq %d for Rx queue %d, "
353 bus_describe_intr(priv->dev, irq->res, irq->cookie, "rx%d", j);
354 com->ntfy_id = i + j;
359 irq = &priv->irq_tbl[m];
361 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
363 if (irq->res == NULL) {
364 device_printf(priv->dev, "Failed to allocate irq %d for mgmnt queue\n", rid);
369 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
370 gve_mgmnt_intr, NULL, priv, &irq->cookie);
372 device_printf(priv->dev, "Failed to setup irq %d for mgmnt queue, err: %d\n",
377 bus_describe_intr(priv->dev, irq->res, irq->cookie, "mgmnt");
411 for (idx = 0; idx < priv->tx_cfg.num_queues; idx++) {
412 tx = &priv->tx[idx];
414 gve_db_bar_write_4(priv, tx->com.irq_db_offset, 0);
416 gve_db_bar_dqo_write_4(priv, tx->com.irq_db_offset,
420 for (idx = 0; idx < priv->rx_cfg.num_queues; idx++) {
421 rx = &priv->rx[idx];
423 gve_db_bar_write_4(priv, rx->com.irq_db_offset, 0);
425 gve_db_bar_dqo_write_4(priv, rx->com.irq_db_offset,
433 for (int idx = 0; idx < priv->tx_cfg.num_queues; idx++) {
434 struct gve_tx_ring *tx = &priv->tx[idx];
435 gve_db_bar_write_4(priv, tx->com.irq_db_offset, GVE_IRQ_MASK);
437 for (int idx = 0; idx < priv->rx_cfg.num_queues; idx++) {
438 struct gve_rx_ring *rx = &priv->rx[idx];
439 gve_db_bar_write_4(priv, rx->com.irq_db_offset, GVE_IRQ_MASK);