Lines Matching defs:priv
35 gve_reg_bar_read_4(struct gve_priv *priv, bus_size_t offset)
37 return (be32toh(bus_read_4(priv->reg_bar, offset)));
41 gve_reg_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val)
43 bus_write_4(priv->reg_bar, offset, htobe32(val));
47 gve_db_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val)
49 bus_write_4(priv->db_bar, offset, htobe32(val));
53 gve_db_bar_dqo_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val)
55 bus_write_4(priv->db_bar, offset, val);
86 gve_dma_alloc_coherent(struct gve_priv *priv, int size, int align,
90 device_t dev = priv->dev;
151 gve_dmamap_create(struct gve_priv *priv, int size, int align,
155 device_t dev = priv->dev;
217 struct gve_priv *priv = arg;
219 taskqueue_enqueue(priv->service_tq, &priv->service_task);
224 gve_free_irqs(struct gve_priv *priv)
232 if (priv->irq_tbl == NULL) {
233 device_printf(priv->dev, "No irq table, nothing to free\n");
237 num_irqs = priv->tx_cfg.num_queues + priv->rx_cfg.num_queues + 1;
240 irq = &priv->irq_tbl[i];
246 rc = bus_teardown_intr(priv->dev, irq->res, irq->cookie);
248 device_printf(priv->dev, "Failed to teardown irq num %d\n",
251 rc = bus_release_resource(priv->dev, SYS_RES_IRQ,
254 device_printf(priv->dev, "Failed to release irq num %d\n",
261 free(priv->irq_tbl, M_GVE);
262 priv->irq_tbl = NULL;
265 pci_release_msi(priv->dev);
269 gve_alloc_irqs(struct gve_priv *priv)
271 int num_tx = priv->tx_cfg.num_queues;
272 int num_rx = priv->rx_cfg.num_queues;
284 if (pci_alloc_msix(priv->dev, &got_nvecs) != 0) {
285 device_printf(priv->dev, "Failed to acquire any msix vectors\n");
289 device_printf(priv->dev, "Tried to acquire %d msix vectors, got only %d\n",
296 device_printf(priv->dev, "Enabled MSIX with %d vectors\n", got_nvecs);
298 priv->irq_tbl = malloc(sizeof(struct gve_irq) * req_nvecs, M_GVE,
302 irq = &priv->irq_tbl[i];
303 tx = &priv->tx[i];
307 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
310 device_printf(priv->dev, "Failed to alloc irq %d for Tx queue %d\n",
316 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
317 gve_is_gqi(priv) ? gve_tx_intr : gve_tx_intr_dqo, NULL,
318 &priv->tx[i], &irq->cookie);
320 device_printf(priv->dev, "Failed to setup irq %d for Tx queue %d, "
325 bus_describe_intr(priv->dev, irq->res, irq->cookie, "tx%d", i);
330 irq = &priv->irq_tbl[i + j];
331 rx = &priv->rx[j];
335 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
338 device_printf(priv->dev,
344 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
345 gve_is_gqi(priv) ? gve_rx_intr : gve_rx_intr_dqo, NULL,
346 &priv->rx[j], &irq->cookie);
348 device_printf(priv->dev, "Failed to setup irq %d for Rx queue %d, "
353 bus_describe_intr(priv->dev, irq->res, irq->cookie, "rx%d", j);
359 irq = &priv->irq_tbl[m];
361 irq->res = bus_alloc_resource_any(priv->dev, SYS_RES_IRQ,
364 device_printf(priv->dev, "Failed to allocate irq %d for mgmnt queue\n", rid);
369 err = bus_setup_intr(priv->dev, irq->res, INTR_TYPE_NET | INTR_MPSAFE,
370 gve_mgmnt_intr, NULL, priv, &irq->cookie);
372 device_printf(priv->dev, "Failed to setup irq %d for mgmnt queue, err: %d\n",
377 bus_describe_intr(priv->dev, irq->res, irq->cookie, "mgmnt");
382 gve_free_irqs(priv);
405 gve_unmask_all_queue_irqs(struct gve_priv *priv)
411 for (idx = 0; idx < priv->tx_cfg.num_queues; idx++) {
412 tx = &priv->tx[idx];
413 if (gve_is_gqi(priv))
414 gve_db_bar_write_4(priv, tx->com.irq_db_offset, 0);
416 gve_db_bar_dqo_write_4(priv, tx->com.irq_db_offset,
420 for (idx = 0; idx < priv->rx_cfg.num_queues; idx++) {
421 rx = &priv->rx[idx];
422 if (gve_is_gqi(priv))
423 gve_db_bar_write_4(priv, rx->com.irq_db_offset, 0);
425 gve_db_bar_dqo_write_4(priv, rx->com.irq_db_offset,
431 gve_mask_all_queue_irqs(struct gve_priv *priv)
433 for (int idx = 0; idx < priv->tx_cfg.num_queues; idx++) {
434 struct gve_tx_ring *tx = &priv->tx[idx];
435 gve_db_bar_write_4(priv, tx->com.irq_db_offset, GVE_IRQ_MASK);
437 for (int idx = 0; idx < priv->rx_cfg.num_queues; idx++) {
438 struct gve_rx_ring *rx = &priv->rx[idx];
439 gve_db_bar_write_4(priv, rx->com.irq_db_offset, GVE_IRQ_MASK);