Lines Matching +full:0 +full:x414

58 #if 0
61 } while (0)
67 #define PL061_DATA		0x3FC
68 #define PL061_DIR		0x400
69 #define PL061_INTSENSE  	0x404
70 #define PL061_INTBOTHEDGES	0x408
71 #define PL061_INTEVENT		0x40C
72 #define PL061_INTMASK		0x410
73 #define PL061_RAWSTATUS		0x414
74 #define PL061_STATUS		0x418
75 #define PL061_INTCLR		0x41C
76 #define PL061_MODECTRL		0x420
97 	return (0);
107 	name[GPIOMAXNAME - 1] = '\0';
109 	return (0);
123 	*flags = 0;
131 	return (0);
142 	return (0);
177 	mask_and_set(sc, PL061_DIR, mask, flags & GPIO_PIN_OUTPUT ? mask : 0);
179 	return (0);
198 	return (0);
205 	uint8_t d = (value == GPIO_PIN_HIGH) ? 0xff : 0x00;
215 	return (0);
233 	return (0);
247 	mask_and_set(sc, PL061_INTMASK, mask, 0);
291 	return (0);
321 	if (isrc->isrc_handlers != 0) {
323 		return (irqsrc->mode == mode ? 0 : EINVAL);
331 		mask_and_set(sc, PL061_INTSENSE, mask, 0);
333 		mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
334 		mask_and_set(sc, PL061_INTSENSE, mask, 0);
337 		mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
338 		mask_and_set(sc, PL061_INTSENSE, mask, 0);
339 		mask_and_set(sc, PL061_INTEVENT, mask, 0);
341 		mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
345 		mask_and_set(sc, PL061_INTBOTHEDGES, mask, 0);
347 		mask_and_set(sc, PL061_INTEVENT, mask, 0);
350 	return (0);
366 	if (isrc->isrc_handlers == 0) {
369 		mask_and_set(sc, PL061_INTMASK, mask, 0);
372 	return (0);
421 	while (status != 0) {
425 		if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, pin), tf) != 0)
446 	sc->sc_mem_rid = 0;
454 	sc->sc_irq_rid = 0;
464 	bus_write_1(sc->sc_mem_res, PL061_INTMASK, 0);
475 	for (irq = 0; irq < PL061_NUM_GPIO; irq++) {
482 		ret = intr_isrc_register(PIC_INTR_ISRC(sc, irq), dev, 0,
498 	return (0);
503 	 * for (irq = 0; irq < PL061_NUM_GPIO; irq++)
511          * intr_pic_deregister(dev, 0);
542 	return (0);