Lines Matching +full:de +full:- +full:noise
5 * Copyright (c) 2003, 2004 Theo de Raadt
59 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */
60 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */
61 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */
62 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */
63 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */
64 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */
65 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */
76 #define SB_GMC_T_SEL0 0x0000 /* RNG post-proc: none */
77 #define SB_GMC_T_SEL1 0x0100 /* RNG post-proc: LFSR */
78 #define SB_GMC_T_SEL2 0x0200 /* RNG post-proc: whitener */
81 #define SB_GMC_T_NE 0x0400 /* Noise (generator) Enable */
86 #define SB_CTL_A 0x0000 /* RW - SB Control A */
87 #define SB_CTL_B 0x0004 /* RW - SB Control B */
88 #define SB_AES_INT 0x0008 /* RW - SB AES Interrupt */
89 #define SB_SOURCE_A 0x0010 /* RW - Source A */
90 #define SB_DEST_A 0x0014 /* RW - Destination A */
91 #define SB_LENGTH_A 0x0018 /* RW - Length A */
92 #define SB_SOURCE_B 0x0020 /* RW - Source B */
93 #define SB_DEST_B 0x0024 /* RW - Destination B */
94 #define SB_LENGTH_B 0x0028 /* RW - Length B */
95 #define SB_WKEY 0x0030 /* WO - Writable Key 0-3 */
96 #define SB_WKEY_0 0x0030 /* WO - Writable Key 0 */
97 #define SB_WKEY_1 0x0034 /* WO - Writable Key 1 */
98 #define SB_WKEY_2 0x0038 /* WO - Writable Key 2 */
99 #define SB_WKEY_3 0x003C /* WO - Writable Key 3 */
100 #define SB_CBC_IV 0x0040 /* RW - CBC IV 0-3 */
101 #define SB_CBC_IV_0 0x0040 /* RW - CBC IV 0 */
102 #define SB_CBC_IV_1 0x0044 /* RW - CBC IV 1 */
103 #define SB_CBC_IV_2 0x0048 /* RW - CBC IV 2 */
104 #define SB_CBC_IV_3 0x004C /* RW - CBC IV 3 */
105 #define SB_RANDOM_NUM 0x0050 /* RW - Random Number */
106 #define SB_RANDOM_NUM_STATUS 0x0054 /* RW - Random Number Status */
107 #define SB_EEPROM_COMM 0x0800 /* RW - EEPROM Command */
108 #define SB_EEPROM_ADDR 0x0804 /* RW - EEPROM Address */
109 #define SB_EEPROM_DATA 0x0808 /* RW - EEPROM Data */
110 #define SB_EEPROM_SEC_STATE 0x080C /* RW - EEPROM Security State */
142 /* must be 16-byte aligned */
146 * The Geode LX security block AES acceleration doesn't perform scatter-
148 * plain- and ciphertexts need to be contiguous. To this end, we allocate
247 "AMD Geode LX Security Block (AES-128-CBC, RNG)"); in glxsb_probe()
260 sc->sc_dev = dev; in glxsb_attach()
272 sc->sc_rid = PCIR_BAR(0); in glxsb_attach()
273 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, in glxsb_attach()
275 if (sc->sc_sr == NULL) { in glxsb_attach()
283 * We want to enable the noise generator (T_NE), and enable the in glxsb_attach()
284 * linear feedback shift register and whitener post-processing in glxsb_attach()
297 bus_write_4(sc->sc_sr, SB_AES_INT, SB_AI_CLEAR_INTR); in glxsb_attach()
299 /* Allocate a contiguous DMA-able buffer to work in */ in glxsb_attach()
304 sc->sc_tq = taskqueue_create("glxsb_taskq", M_NOWAIT | M_ZERO, in glxsb_attach()
305 taskqueue_thread_enqueue, &sc->sc_tq); in glxsb_attach()
306 if (sc->sc_tq == NULL) { in glxsb_attach()
310 if (taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", in glxsb_attach()
315 TASK_INIT(&sc->sc_cryptotask, 0, glxsb_crypto_task, sc); in glxsb_attach()
323 sc->sc_rnghz = hz / 100; in glxsb_attach()
325 sc->sc_rnghz = 1; in glxsb_attach()
326 callout_init(&sc->sc_rngco, 1); in glxsb_attach()
332 taskqueue_free(sc->sc_tq); in glxsb_attach()
334 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); in glxsb_attach()
343 crypto_unregister_all(sc->sc_cid); in glxsb_detach()
345 callout_drain(&sc->sc_rngco); in glxsb_detach()
346 taskqueue_drain(sc->sc_tq, &sc->sc_cryptotask); in glxsb_detach()
348 glxsb_dma_free(sc, &sc->sc_dma); in glxsb_detach()
349 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_sr); in glxsb_detach()
350 taskqueue_free(sc->sc_tq); in glxsb_detach()
351 mtx_destroy(&sc->sc_task_mtx); in glxsb_detach()
369 struct glxsb_dma_map *dma = &sc->sc_dma; in glxsb_dma_alloc()
372 dma->dma_nsegs = 1; in glxsb_dma_alloc()
373 dma->dma_size = GLXSB_MAX_AES_LEN * 2; in glxsb_dma_alloc()
376 rc = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ in glxsb_dma_alloc()
381 dma->dma_size, /* maxsize */ in glxsb_dma_alloc()
382 dma->dma_nsegs, /* nsegments */ in glxsb_dma_alloc()
383 dma->dma_size, /* maxsegsize */ in glxsb_dma_alloc()
386 &sc->sc_dmat); in glxsb_dma_alloc()
388 device_printf(sc->sc_dev, in glxsb_dma_alloc()
393 rc = bus_dmamem_alloc(sc->sc_dmat, (void **)&dma->dma_vaddr, in glxsb_dma_alloc()
394 BUS_DMA_NOWAIT, &dma->dma_map); in glxsb_dma_alloc()
396 device_printf(sc->sc_dev, in glxsb_dma_alloc()
398 dma->dma_size, rc); in glxsb_dma_alloc()
402 rc = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, in glxsb_dma_alloc()
403 dma->dma_size, glxsb_dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); in glxsb_dma_alloc()
405 device_printf(sc->sc_dev, in glxsb_dma_alloc()
407 dma->dma_size, rc); in glxsb_dma_alloc()
414 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); in glxsb_dma_alloc()
416 bus_dma_tag_destroy(sc->sc_dmat); in glxsb_dma_alloc()
424 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, in glxsb_dma_pre_op()
432 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, in glxsb_dma_post_op()
440 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); in glxsb_dma_free()
441 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); in glxsb_dma_free()
442 bus_dma_tag_destroy(sc->sc_dmat); in glxsb_dma_free()
451 status = bus_read_4(sc->sc_sr, SB_RANDOM_NUM_STATUS); in glxsb_rnd()
453 value = bus_read_4(sc->sc_sr, SB_RANDOM_NUM); in glxsb_rnd()
459 callout_reset(&sc->sc_rngco, sc->sc_rnghz, glxsb_rnd, sc); in glxsb_rnd()
466 sc->sc_cid = crypto_get_driverid(sc->sc_dev, in glxsb_crypto_setup()
469 if (sc->sc_cid < 0) { in glxsb_crypto_setup()
470 device_printf(sc->sc_dev, "cannot get crypto driver id\n"); in glxsb_crypto_setup()
474 mtx_init(&sc->sc_task_mtx, "glxsb_crypto_mtx", NULL, MTX_DEF); in glxsb_crypto_setup()
483 if (csp->csp_flags != 0) in glxsb_crypto_probesession()
491 switch (csp->csp_mode) { in glxsb_crypto_probesession()
493 switch (csp->csp_auth_alg) { in glxsb_crypto_probesession()
506 switch (csp->csp_cipher_alg) { in glxsb_crypto_probesession()
508 if (csp->csp_cipher_klen * 8 != 128) in glxsb_crypto_probesession()
531 if (csp->csp_cipher_key != NULL) in glxsb_crypto_newsession()
532 bcopy(csp->csp_cipher_key, ses->ses_key, sizeof(ses->ses_key)); in glxsb_crypto_newsession()
534 if (csp->csp_auth_alg != 0) { in glxsb_crypto_newsession()
537 glxsb_crypto_freesession(sc->sc_dev, cses); in glxsb_crypto_newsession()
562 device_printf(sc->sc_dev, in glxsb_aes()
568 bus_write_4(sc->sc_sr, SB_SOURCE_A, psrc); in glxsb_aes()
571 bus_write_4(sc->sc_sr, SB_DEST_A, pdst); in glxsb_aes()
574 bus_write_4(sc->sc_sr, SB_LENGTH_A, len); in glxsb_aes()
578 bus_write_region_4(sc->sc_sr, SB_CBC_IV, iv, 4); in glxsb_aes()
583 bus_write_region_4(sc->sc_sr, SB_WKEY, key, 4); in glxsb_aes()
586 bus_write_4(sc->sc_sr, SB_CTL_A, in glxsb_aes()
612 status = bus_read_4(sc->sc_sr, SB_CTL_A); in glxsb_aes()
617 device_printf(sc->sc_dev, "operation failed to complete\n"); in glxsb_aes()
634 if ((crp->crp_payload_length % SB_AES_BLOCK_SIZE) != 0) in glxsb_crypto_encdec()
638 xlen = crp->crp_payload_length > GLXSB_MAX_AES_LEN ? in glxsb_crypto_encdec()
639 GLXSB_MAX_AES_LEN : crp->crp_payload_length; in glxsb_crypto_encdec()
645 op_src = sc->sc_dma.dma_vaddr; in glxsb_crypto_encdec()
646 op_dst = (char *)sc->sc_dma.dma_vaddr + xlen; in glxsb_crypto_encdec()
648 op_psrc = sc->sc_dma.dma_paddr; in glxsb_crypto_encdec()
649 op_pdst = sc->sc_dma.dma_paddr + xlen; in glxsb_crypto_encdec()
651 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) in glxsb_crypto_encdec()
659 tlen = crp->crp_payload_length; in glxsb_crypto_encdec()
661 if (crp->crp_cipher_key != NULL) in glxsb_crypto_encdec()
662 key = crp->crp_cipher_key; in glxsb_crypto_encdec()
664 key = ses->ses_key; in glxsb_crypto_encdec()
669 crypto_copydata(crp, crp->crp_payload_start + offset, len, in glxsb_crypto_encdec()
672 glxsb_dma_pre_op(sc, &sc->sc_dma); in glxsb_crypto_encdec()
677 glxsb_dma_post_op(sc, &sc->sc_dma); in glxsb_crypto_encdec()
681 crypto_copyback(crp, crp->crp_payload_start + offset, len, in glxsb_crypto_encdec()
685 tlen -= len; in glxsb_crypto_encdec()
690 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) in glxsb_crypto_encdec()
691 bcopy(op_dst + len - sizeof(op_iv), op_iv, in glxsb_crypto_encdec()
694 bcopy(op_src + len - sizeof(op_iv), op_iv, in glxsb_crypto_encdec()
699 bzero(sc->sc_dma.dma_vaddr, xlen * 2); in glxsb_crypto_encdec()
713 crp = sc->sc_to.to_crp; in glxsb_crypto_task()
714 ses = sc->sc_to.to_ses; in glxsb_crypto_task()
715 csp = crypto_get_params(crp->crp_session); in glxsb_crypto_task()
718 if (csp->csp_mode == CSP_MODE_ETA && in glxsb_crypto_task()
719 !CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { in glxsb_crypto_task()
730 if (csp->csp_mode == CSP_MODE_ETA && in glxsb_crypto_task()
731 CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { in glxsb_crypto_task()
737 mtx_lock(&sc->sc_task_mtx); in glxsb_crypto_task()
738 sc->sc_task_count--; in glxsb_crypto_task()
739 mtx_unlock(&sc->sc_task_mtx); in glxsb_crypto_task()
741 crp->crp_etype = error; in glxsb_crypto_task()
742 crypto_unblock(sc->sc_cid, CRYPTO_SYMQ); in glxsb_crypto_task()
752 ses = crypto_get_driver_session(crp->crp_session); in glxsb_crypto_process()
754 mtx_lock(&sc->sc_task_mtx); in glxsb_crypto_process()
755 if (sc->sc_task_count != 0) { in glxsb_crypto_process()
756 mtx_unlock(&sc->sc_task_mtx); in glxsb_crypto_process()
759 sc->sc_task_count++; in glxsb_crypto_process()
761 sc->sc_to.to_crp = crp; in glxsb_crypto_process()
762 sc->sc_to.to_ses = ses; in glxsb_crypto_process()
763 mtx_unlock(&sc->sc_task_mtx); in glxsb_crypto_process()
765 taskqueue_enqueue(sc->sc_tq, &sc->sc_cryptotask); in glxsb_crypto_process()