Lines Matching +full:rx +full:- +full:frame +full:- +full:sync +full:- +full:delay +full:- +full:bits
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 /* Note: Reading the status reg clears bits 0-6. */
45 /* Bits in GEM_SEB register */
49 /* Bits in GEM_CONFIG register */
58 #define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */
68 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
69 * Bits 0-6 auto-clear when read.
71 #define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */
78 #define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */
90 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */
98 /* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */
104 /* GEM_PCI_BIF_CONFIG register bits */
106 #define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */
107 #define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */
112 /* GEM_PCI_BIF_DIAG register bits */
116 /* GEM_RESET register bits -- TX and RX self clear when complete. */
118 #define GEM_RESET_RX 0x00000002 /* Reset RX half. */
146 /* GEM_TX_CONFIG register bits */
162 /* GEM_TX_COMPLETION register bits */
165 /* RX DMA registers */
167 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */
168 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */
192 /* GEM_RX_CONFIG register bits */
193 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
194 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
211 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
215 /* GEM_RX_BLANKING register bits */
216 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
217 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
238 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */
293 /* GEM_MAC_SEND_PAUSE_CMD register bits */
297 /* GEM_MAC_TX_STATUS and _MASK register bits */
308 /* GEM_MAC_RX_STATUS and _MASK register bits */
317 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */
328 /* GEM_MAC_XIF_CONFIG register bits */
348 /* GEM_MAC_TX_CONFIG register bits */
352 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
366 /* GEM_MAC_RX_CONFIG register bits */
367 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */
375 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
385 /* GEM_MAC_CONTROL_CONFIG bits */
398 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */
404 /* GEM_MIF_FRAME bits */
410 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */
411 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */
419 /* GEM_MIF_CONFIG register bits */
431 /* GEM_MIF_STATUS and GEM_MIF_MASK bits */
439 * The status part indicates the bits that have changed.
455 /* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */
458 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */
459 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */
462 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */
464 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
470 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
474 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */
476 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
481 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */
482 #define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */
483 #define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */
486 #define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
487 #define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
499 #define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */
500 #define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */
501 #define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */
502 #define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */
505 #define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */
516 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
525 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
528 #define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */
583 #define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */