Lines Matching +full:0 +full:x1032
117 0x0, 0x0, /* cb_status */
118 0x0, 0x0, /* cb_command */
119 0x0, 0x0, 0x0, 0x0, /* link_addr */
120 0x0, /* 0 */
121 0x0, /* 1 */
122 0x0, /* 2 */
123 0x0, /* 3 */
124 0x0, /* 4 */
125 0x0, /* 5 */
126 0x32, /* 6 */
127 0x0, /* 7 */
128 0x0, /* 8 */
129 0x0, /* 9 */
130 0x6, /* 10 */
131 0x0, /* 11 */
132 0x0, /* 12 */
133 0x0, /* 13 */
134 0xf2, /* 14 */
135 0x48, /* 15 */
136 0x0, /* 16 */
137 0x40, /* 17 */
138 0xf0, /* 18 */
139 0x0, /* 19 */
140 0x3f, /* 20 */
141 0x5, /* 21 */
142 0x0, /* 22 */
143 0x0, /* 23 */
144 0x0, /* 24 */
145 0x0, /* 25 */
146 0x0, /* 26 */
147 0x0, /* 27 */
148 0x0, /* 28 */
149 0x0, /* 29 */
150 0x0, /* 30 */
151 0x0 /* 31 */
161 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
162 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
163 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
165 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
171 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
174 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
176 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
177 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
178 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
179 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
180 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
181 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
182 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
183 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
184 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
185 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
186 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
187 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
188 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
189 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
190 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
191 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
204 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
205 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
206 { 0, 0, -1, 0, NULL },
311 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
312 { -1, 0 }
317 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
318 { -1, 0 }
336 if (i == 0) {
337 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
339 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
363 for (i = 10000; i > 0; i--) {
367 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
370 if (i == 0)
436 error = 0;
441 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
442 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
457 prefer_iomap = 0;
504 if (sc->ident->ich > 0) {
521 if ((data & 0x20) != 0 &&
522 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
534 if ((data & 0x0400) == 0)
541 if ((data & 0x03) != 0x03) {
551 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
569 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
571 if (data & 0x02) { /* STB enable */
577 data &= ~0x02;
580 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
581 cksum = 0;
582 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
585 cksum = 0xBABA - cksum;
588 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
610 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
626 if (sc->ident->device != 0x1209)
657 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
660 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag);
666 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
668 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag);
674 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
676 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
697 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
699 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag);
720 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
722 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
752 for (i = 0; i < FXP_NTXCB; i++) {
754 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
760 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
770 for (i = 0; i < FXP_NRFABUFS; i++) {
772 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
777 if (fxp_new_rfabuf(sc, rxp) != 0) {
787 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
789 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
791 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
799 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
813 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
826 if (error != 0) {
840 if_setcapabilities(ifp, 0);
841 if_setcapenable(ifp, 0);
846 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
847 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
851 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
852 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
856 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
857 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
862 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
876 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
877 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
878 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
880 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
882 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
907 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
911 fxp_init_body(sc, 0);
953 for (i = 0; i < FXP_NRFABUFS; i++) {
967 for (i = 0; i < FXP_NTXCB; i++) {
1027 return (0);
1063 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1066 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1071 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1072 fxp_init_body(sc, 0);
1081 return (0);
1098 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1104 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1116 sc->suspended = 0;
1119 return (0);
1166 data = 0;
1180 if (autosize && reg == 0) {
1188 data = 0;
1198 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1213 fxp_eeprom_shiftin(sc, 0x4, 3);
1214 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1215 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1231 for (i = 0; i < 1000; i++) {
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1242 fxp_eeprom_shiftin(sc, 0x4, 3);
1243 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1244 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1276 (void) fxp_eeprom_getword(sc, 0, 1);
1284 for (i = 0; i < words; i++)
1285 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1293 for (i = 0; i < words; i++)
1303 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1304 cksum = 0;
1305 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1307 cksum = 0xBABA - cksum;
1310 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1353 txqueued = 0;
1367 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1380 if (txqueued > 0) {
1405 tcp_payload = 0;
1439 if (M_WRITABLE(*m_head) == 0) {
1490 ip->ip_sum = 0;
1555 segs, &nseg, 0);
1565 *m_head, segs, &nseg, 0);
1566 if (error != 0) {
1571 } else if (error != 0)
1573 if (nseg == 0) {
1583 for (i = 0; i < nseg; i++) {
1607 cbp->tbd_number = 0xFF;
1608 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1621 if ((m->m_flags & M_VLANTAG) != 0) {
1628 txp->tx_cb->cb_status = 0;
1629 txp->tx_cb->byte_count = 0;
1638 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1652 if (sc->tx_queued == 0)
1657 return (0);
1668 int rx_npkts = 0;
1682 if (tmp == 0xff || tmp == 0) {
1688 if (tmp != 0)
1720 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1723 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1727 if (statack == 0xff) {
1736 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1752 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1761 txp->tx_cb->tbd[0].tb_addr = 0;
1764 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1769 if (sc->tx_queued == 0)
1770 sc->watchdog_timer = 0;
1783 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1784 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1793 m->m_pkthdr.csum_data = 0xffff;
1829 if (uh->uh_sum == 0)
1839 if (len > 0) {
1841 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1858 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1862 rx_npkts = 0;
1900 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1923 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1924 if (count >= 0 && count-- == 0) {
1928 rnr = 0;
1935 if ((status & FXP_RFA_STATUS_C) == 0)
1938 if ((status & FXP_RFA_STATUS_RNR) != 0)
1950 if (fxp_new_rfabuf(sc, rxp) == 0) {
1959 total_len = le16toh(rfa->actual_size) & 0x3fff;
1960 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1961 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1979 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1981 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1982 (status & FXP_RFA_STATUS_VLAN) != 0) {
1999 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2067 sc->rx_idle_secs = 0;
2089 *status = 0;
2137 sc->rx_idle_secs = 0;
2138 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2139 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2148 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2179 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2180 sc->watchdog_timer = 0;
2202 for (i = 0; i < FXP_NTXCB; i++) {
2210 txp[i].tx_cb->tbd[0].tb_addr = 0;
2215 sc->tx_queued = 0;
2231 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2237 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2288 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2294 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2314 if (sc->ident->ich == 0) {
2316 (sc->flags & FXP_FLAG_UCODE) == 0)
2340 cbp->cb_status = 0;
2343 cbp->link_addr = 0xffffffff; /* (no) next command */
2346 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2347 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2348 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2349 cbp->type_enable = 0; /* actually reserved */
2350 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2351 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2352 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2353 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2354 cbp->dma_mbce = 0; /* (disable) dma max counters */
2355 cbp->late_scb = 0; /* (don't) defer SCB update */
2357 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2359 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2361 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2365 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2366 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2367 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2368 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2369 cbp->csma_dis = 0; /* (don't) disable link */
2370 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2371 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2372 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2373 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2374 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2375 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2378 cbp->loopback = 0; /* (don't) loopback */
2379 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2380 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2383 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2384 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2385 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2386 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2387 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2391 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2392 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2393 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2394 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2395 cbp->force_fdx = 0; /* (don't) force full duplex */
2397 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2399 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2400 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2401 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2408 cbp->fc_delay_lsb = 0;
2409 cbp->fc_delay_msb = 0x40;
2411 cbp->tx_fc_dis = 0;
2412 cbp->rx_fc_restop = 0;
2413 cbp->rx_fc_restart = 0;
2414 cbp->fc_filter = 0;
2420 cbp->fc_delay_lsb = 0xff;
2421 cbp->fc_delay_msb = 0xff;
2425 IFM_ETH_TXPAUSE) != 0)
2427 cbp->tx_fc_dis = 0;
2432 IFM_ETH_RXPAUSE) != 0) {
2438 cbp->rx_fc_restart = 0;
2439 cbp->rx_fc_restop = 0;
2458 cbp->ext_stats_dis = 0;
2477 cb_ias->cb_status = 0;
2479 cb_ias->link_addr = 0xffffffff;
2504 for (i = 0; i < FXP_NTXCB; i++) {
2515 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2539 if (sc->miibus != NULL && setmedia != 0)
2556 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2568 return (0);
2594 return (0);
2616 * Return 0 if successful, 1 for failure. A failure results in
2647 rfa->rfa_status = 0;
2649 rfa->actual_size = 0;
2659 le32enc(&rfa->link_addr, 0xffffffff);
2660 le32enc(&rfa->rbd_addr, 0xffffffff);
2680 return (0);
2699 p_rfa->rfa_control = 0;
2731 rfa->rfa_status = 0;
2733 rfa->actual_size = 0;
2741 le32enc(&rfa->link_addr, 0xffffffff);
2742 le32enc(&rfa->rbd_addr, 0xffffffff);
2758 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2762 if (count <= 0)
2765 return (value & 0xffff);
2776 (value & 0xffff));
2778 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2782 if (count <= 0)
2784 return (0);
2798 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2807 sc->cu_resume_bug = 0;
2814 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2815 fxp_init_body(sc, 0);
2824 int flag, mask, error = 0, reinit;
2836 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2838 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2839 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2840 fxp_init_body(sc, 0);
2841 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2844 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2854 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2855 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2856 fxp_init_body(sc, 0);
2873 reinit = 0;
2884 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2890 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2891 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2897 if ((mask & IFCAP_TXCSUM) != 0 &&
2898 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2900 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2901 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2903 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2905 if ((mask & IFCAP_RXCSUM) != 0 &&
2906 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2908 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2911 if ((mask & IFCAP_TSO4) != 0 &&
2912 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2914 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2915 if_sethwassistbits(ifp, CSUM_TSO, 0);
2917 if_sethwassistbits(ifp, 0, CSUM_TSO);
2919 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2920 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2922 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2923 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2933 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2934 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2936 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2937 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2939 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2940 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2942 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2943 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2947 if (reinit > 0 &&
2948 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2949 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2950 fxp_init_body(sc, 0);
2984 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2985 mcsp->mc_cnt = 0;
2988 if_setflagbits(ifp, IFF_ALLMULTI, 0);
2989 mcsp->mc_cnt = 0;
3016 mcsp->cb_status = 0;
3018 mcsp->link_addr = 0xffffffff;
3029 if (count == 0) {
3063 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3064 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3077 { 0, NULL, 0, 0, 0 }
3096 cbp->cb_status = 0;
3098 cbp->link_addr = 0xffffffff; /* (no) next command */
3099 for (i = 0; i < uc->length; i++)
3120 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3126 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3141 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3145 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3147 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3159 sc->rnr = 0;
3232 error = sysctl_handle_int(oidp, &value, 0, req);
3238 return (0);
3256 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));