Lines Matching defs:pidx
653 desc = &queue->ring[queue->pidx];
655 if (++queue->pidx == ENETC_MIN_DESC)
656 queue->pidx = 0;
670 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx);
674 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx)
732 queue->pidx = 0;
733 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx);
734 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx);
959 qidx_t cidx, pidx;
963 pidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBPIR);
966 while (pidx != cidx && timeout--) {
1097 qidx_t pidx, queue_len;
1102 pidx = ipi->ipi_pidx;
1109 desc = &queue->ring[pidx];
1118 if (++pidx == queue_len)
1119 pidx = 0;
1124 desc = &queue->ring[pidx];
1128 if (++pidx == queue_len)
1129 pidx = 0;
1134 desc = &queue->ring[pidx];
1139 if (++pidx == queue_len)
1140 pidx = 0;
1144 ipi->ipi_new_pidx = pidx;
1150 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx)
1154 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx);
1170 * Thanks to that we can assume that the ring is empty if cidx == pidx.
1194 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget)
1203 desc = &queue->ring[pidx];
1213 while (pidx != hw_pidx && count < budget) {
1214 desc = &queue->ring[pidx];
1218 if (++pidx == queue_len)
1219 pidx = 0;
1295 qidx_t pidx, queue_len;
1301 pidx = iru->iru_pidx;
1306 desc = &queue->ring[pidx];
1310 if (++pidx == queue_len)
1311 pidx = 0;
1316 * refilled when cidx == pidx.
1319 if (!queue->enabled && pidx >= 8) {
1326 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx)
1330 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx);