Lines Matching +full:7 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
10 #define BIT(x) (1UL << (x)) macro
11 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
25 #define ENETC_SIMR_EN BIT(31)
26 #define ENETC_SIMR_DRXG BIT(16)
27 #define ENETC_SIMR_RSSE BIT(0)
31 #define ENETC_SIPCAPR0_QBV BIT(4)
32 #define ENETC_SIPCAPR0_PSFP BIT(9)
33 #define ENETC_SIPCAPR0_RSS BIT(8)
52 /* VF-PF Message passing */
57 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
62 #define ENETC_VSIMSGSR_MB BIT(0)
63 #define ENETC_VSIMSGSR_MS BIT(1)
83 #define ENETC_SICBDRMR_EN BIT(31)
109 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
111 /** SI BDR sub-blocks, n = 0..7 */
117 #define ENETC_RBMR_AL BIT(0)
118 #define ENETC_RBMR_BDS BIT(2)
119 #define ENETC_RBMR_VTE BIT(5)
120 #define ENETC_RBMR_EN BIT(31)
129 #define ENETC_RBIER_RXTIE BIT(0)
132 #define ENETC_RBICR0_ICEN BIT(31)
139 #define ENETC_TBSR_BUSY BIT(0)
140 #define ENETC_TBMR_VIH BIT(9)
143 #define ENETC_TBMR_EN BIT(31)
152 #define ENETC_TBIER_TXT BIT(0)
153 #define ENETC_TBIER_TXF BIT(1)
156 #define ENETC_TBICR0_ICEN BIT(31)
166 #define ENETC_PMR_SI0EN BIT(16)
170 #define ENETC_PMR_PSPEED_100M BIT(8)
171 #define ENETC_PMR_PSPEED_1000M BIT(9)
172 #define ENETC_PMR_PSPEED_2500M BIT(10)
175 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
176 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
186 #define ENETC_VLAN_TYPE_C BIT(0)
187 #define ENETC_VLAN_TYPE_S BIT(1)
190 #define ENETC_PSIVLAN_EN BIT(31)
200 #define ENETC_PSICFGR0_VTE BIT(12)
201 #define ENETC_PSICFGR0_SIVIE BIT(14)
202 #define ENETC_PSICFGR0_ASE BIT(15)
205 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
206 #define ENETC_CBSE BIT(31)
208 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
211 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
214 #define ENETC_PSIVLANFMR_VS BIT(0)
216 #define ENETC_PRFSMR_RFSE BIT(31)
221 #define ENETC_PFPMR_PMACE BIT(1)
222 #define ENETC_PFPMR_MWLM BIT(0)
231 #define ENETC_MMCSR_ME BIT(16)
232 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
235 #define ENETC_PAR_PORT_L4CD BIT(0)
236 #define ENETC_PAR_PORT_L3CD BIT(1)
240 #define ENETC_PM0_TX_EN BIT(0)
241 #define ENETC_PM0_RX_EN BIT(1)
242 #define ENETC_PM0_PROMISC BIT(4)
243 #define ENETC_PM0_CMD_XGLP BIT(10)
244 #define ENETC_PM0_CMD_TXP BIT(11)
245 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
246 #define ENETC_PM0_CMD_SFD BIT(21)
256 #define ENETC_PM0_IFM_RG BIT(2)
257 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
258 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
263 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
379 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
380 ENETC_TXBD_FLAGS_TSE = BIT(1),
381 ENETC_TXBD_FLAGS_W = BIT(2),
382 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */
383 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
384 ENETC_TXBD_FLAGS_FI = BIT(5),
385 ENETC_TXBD_FLAGS_EX = BIT(6),
386 ENETC_TXBD_FLAGS_F = BIT(7)
397 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
398 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
425 #define ENETC_RXBD_PARSER_ERROR BIT(15)
427 #define ENETC_RXBD_LSTATUS_R BIT(30)
428 #define ENETC_RXBD_LSTATUS_F BIT(31)
431 #define ENETC_RXBD_FLAG_RSSV BIT(8)
432 #define ENETC_RXBD_FLAG_VLAN BIT(9)
433 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
440 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
448 uint32_t sip_h[4]; /* Big-endian */
449 uint32_t sip_m[4]; /* Big-endian */
450 uint32_t dip_h[4]; /* Big-endian */
451 uint32_t dip_m[4]; /* Big-endian */
469 #define ENETC_RFSE_EN BIT(15)
484 /* VSI-PSI command message types */
491 /* VSI-PSI command action types */
497 /* PSI-VSI command header format */
516 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
527 uint8_t res[7];
551 /* class 7, command 0, Stream Identity Entry Configuration */
562 #define ENETC_CBDR_SID_VIDM BIT(12)
574 #define ENETC_CBDR_SFI_PRIM BIT(3)
575 #define ENETC_CBDR_SFI_BLOV BIT(4)
576 #define ENETC_CBDR_SFI_BLEN BIT(5)
577 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
578 #define ENETC_CBDR_SFI_FMITEN BIT(7)
579 #define ENETC_CBDR_SFI_ENABLE BIT(7)
618 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
619 #define ENETC_CBDR_SGI_CGTST BIT(6)
620 #define ENETC_CBDR_SGI_OGTST BIT(7)
621 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
622 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
623 #define ENETC_CBDR_SGI_OEX BIT(4)
624 #define ENETC_CBDR_SGI_OEXEN BIT(5)
625 #define ENETC_CBDR_SGI_IRX BIT(6)
626 #define ENETC_CBDR_SGI_IRXEN BIT(7)
629 #define ENETC_CBDR_SGI_EN BIT(7)
639 uint8_t res1[7];
647 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
648 #define ENETC_CBDR_SGI_AGTST BIT(7)
666 #define ENETC_CBDR_SGL_IOMEN BIT(0)
667 #define ENETC_CBDR_SGL_IPVEN BIT(3)
668 #define ENETC_CBDR_SGL_GTST BIT(4)
686 #define ENETC_CBDR_FMI_MR BIT(0)
687 #define ENETC_CBDR_FMI_MREN BIT(1)
688 #define ENETC_CBDR_FMI_DOY BIT(2)
689 #define ENETC_CBDR_FMI_CM BIT(3)
690 #define ENETC_CBDR_FMI_CF BIT(4)
691 #define ENETC_CBDR_FMI_NDOR BIT(5)
692 #define ENETC_CBDR_FMI_OALEN BIT(6)
736 #define ENETC_QBV_TGE BIT(31)
737 #define ENETC_QBV_TGPE BIT(30)
745 #define ENETC_TSDE BIT(31)
749 #define ENETC_PPSFPMR_PSFPEN BIT(0)
750 #define ENETC_PPSFPMR_VS BIT(1)
751 #define ENETC_PPSFPMR_PVC BIT(2)
752 #define ENETC_PPSFPMR_PVZC BIT(3)