Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
116 * e1000_null_read_reg - No-op function, return 0
117 * @hw: pointer to the HW structure
121 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
129 * e1000_null_phy_generic - No-op function, return void
130 * @hw: pointer to the HW structure
132 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
139 * e1000_null_lplu_state - No-op function, return 0
140 * @hw: pointer to the HW structure
143 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
151 * e1000_null_write_reg - No-op function, return 0
152 * @hw: pointer to the HW structure
156 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
164 * e1000_read_i2c_byte_null - No-op function, return 0
165 * @hw: pointer to hardware structure
171 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
181 * e1000_write_i2c_byte_null - No-op function, return 0
182 * @hw: pointer to hardware structure
188 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
198 * e1000_check_reset_block_generic - Check if PHY reset is blocked
199 * @hw: pointer to the HW structure
205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
211 manc = E1000_READ_REG(hw, E1000_MANC);
218 * e1000_get_phy_id - Retrieve the PHY ID and revision
219 * @hw: pointer to the HW structure
224 s32 e1000_get_phy_id(struct e1000_hw *hw)
226 struct e1000_phy_info *phy = &hw->phy;
233 if (!phy->ops.read_reg)
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
241 phy->id = (u32)(phy_id << 16);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
260 * e1000_phy_reset_dsp_generic - Reset PHY DSP
261 * @hw: pointer to the HW structure
265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
271 if (!hw->phy.ops.write_reg)
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
282 * e1000_read_phy_reg_mdic - Read MDI control register
283 * @hw: pointer to the HW structure
290 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
292 struct e1000_phy_info *phy = &hw->phy;
299 return -E1000_ERR_PARAM;
302 /* Set up Op-code, Phy Address, and register offset in the MDI
307 (phy->addr << E1000_MDIC_PHY_SHIFT) |
310 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
318 mdic = E1000_READ_REG(hw, E1000_MDIC);
324 return -E1000_ERR_PHY;
328 return -E1000_ERR_PHY;
331 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
334 return -E1000_ERR_PHY;
341 if (hw->mac.type == e1000_pch2lan)
348 * e1000_write_phy_reg_mdic - Write MDI control register
349 * @hw: pointer to the HW structure
355 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
357 struct e1000_phy_info *phy = &hw->phy;
364 return -E1000_ERR_PARAM;
367 /* Set up Op-code, Phy Address, and register offset in the MDI
373 (phy->addr << E1000_MDIC_PHY_SHIFT) |
376 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
384 mdic = E1000_READ_REG(hw, E1000_MDIC);
390 return -E1000_ERR_PHY;
394 return -E1000_ERR_PHY;
397 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
400 return -E1000_ERR_PHY;
406 if (hw->mac.type == e1000_pch2lan)
413 * e1000_read_phy_reg_i2c - Read PHY register using i2c
414 * @hw: pointer to the HW structure
421 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
423 struct e1000_phy_info *phy = &hw->phy;
428 /* Set up Op-code, Phy Address, and register address in the I2CCMD
433 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
447 return -E1000_ERR_PHY;
451 return -E1000_ERR_PHY;
454 /* Need to byte-swap the 16-bit value. */
461 * e1000_write_phy_reg_i2c - Write PHY register using i2c
462 * @hw: pointer to the HW structure
468 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
470 struct e1000_phy_info *phy = &hw->phy;
477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
479 hw->phy.addr);
480 return -E1000_ERR_CONFIG;
486 /* Set up Op-code, Phy Address, and register address in the I2CCMD
491 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
500 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
506 return -E1000_ERR_PHY;
510 return -E1000_ERR_PHY;
517 * e1000_read_sfp_data_byte - Reads SFP module data.
518 * @hw: pointer to the HW structure
529 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
539 return -E1000_ERR_PHY;
542 /* Set up Op-code, EEPROM Address,in the I2CCMD
549 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
554 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
560 return -E1000_ERR_PHY;
564 return -E1000_ERR_PHY;
572 * e1000_write_sfp_data_byte - Writes SFP module data.
573 * @hw: pointer to the HW structure
584 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
594 return -E1000_ERR_PHY;
601 /* Set up Op-code, EEPROM Address,in the I2CCMD
608 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
614 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
627 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
635 return -E1000_ERR_PHY;
639 return -E1000_ERR_PHY;
645 * e1000_read_phy_reg_m88 - Read m88 PHY register
646 * @hw: pointer to the HW structure
654 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
660 if (!hw->phy.ops.acquire)
663 ret_val = hw->phy.ops.acquire(hw);
667 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
670 hw->phy.ops.release(hw);
676 * e1000_write_phy_reg_m88 - Write m88 PHY register
677 * @hw: pointer to the HW structure
684 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
690 if (!hw->phy.ops.acquire)
693 ret_val = hw->phy.ops.acquire(hw);
697 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
700 hw->phy.ops.release(hw);
706 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
707 * @hw: pointer to the HW structure
714 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
720 hw->phy.addr = 1;
722 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
726 * __e1000_read_phy_reg_igp - Read igp PHY register
727 * @hw: pointer to the HW structure
736 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
744 if (!hw->phy.ops.acquire)
747 ret_val = hw->phy.ops.acquire(hw);
753 ret_val = e1000_write_phy_reg_mdic(hw,
757 ret_val = e1000_read_phy_reg_mdic(hw,
761 hw->phy.ops.release(hw);
767 * e1000_read_phy_reg_igp - Read igp PHY register
768 * @hw: pointer to the HW structure
776 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
778 return __e1000_read_phy_reg_igp(hw, offset, data, false);
782 * e1000_read_phy_reg_igp_locked - Read igp PHY register
783 * @hw: pointer to the HW structure
790 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
792 return __e1000_read_phy_reg_igp(hw, offset, data, true);
796 * e1000_write_phy_reg_igp - Write igp PHY register
797 * @hw: pointer to the HW structure
805 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
813 if (!hw->phy.ops.acquire)
816 ret_val = hw->phy.ops.acquire(hw);
822 ret_val = e1000_write_phy_reg_mdic(hw,
826 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
830 hw->phy.ops.release(hw);
836 * e1000_write_phy_reg_igp - Write igp PHY register
837 * @hw: pointer to the HW structure
844 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
846 return __e1000_write_phy_reg_igp(hw, offset, data, false);
850 * e1000_write_phy_reg_igp_locked - Write igp PHY register
851 * @hw: pointer to the HW structure
858 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
860 return __e1000_write_phy_reg_igp(hw, offset, data, true);
864 * __e1000_read_kmrn_reg - Read kumeran register
865 * @hw: pointer to the HW structure
874 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
884 if (!hw->phy.ops.acquire)
887 ret_val = hw->phy.ops.acquire(hw);
894 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
895 E1000_WRITE_FLUSH(hw);
899 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
903 hw->phy.ops.release(hw);
909 * e1000_read_kmrn_reg_generic - Read kumeran register
910 * @hw: pointer to the HW structure
918 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
920 return __e1000_read_kmrn_reg(hw, offset, data, false);
924 * e1000_read_kmrn_reg_locked - Read kumeran register
925 * @hw: pointer to the HW structure
933 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
935 return __e1000_read_kmrn_reg(hw, offset, data, true);
939 * __e1000_write_kmrn_reg - Write kumeran register
940 * @hw: pointer to the HW structure
949 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
959 if (!hw->phy.ops.acquire)
962 ret_val = hw->phy.ops.acquire(hw);
969 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
970 E1000_WRITE_FLUSH(hw);
975 hw->phy.ops.release(hw);
981 * e1000_write_kmrn_reg_generic - Write kumeran register
982 * @hw: pointer to the HW structure
989 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
991 return __e1000_write_kmrn_reg(hw, offset, data, false);
995 * e1000_write_kmrn_reg_locked - Write kumeran register
996 * @hw: pointer to the HW structure
1003 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1005 return __e1000_write_kmrn_reg(hw, offset, data, true);
1009 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1010 * @hw: pointer to the HW structure
1014 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1030 switch (hw->phy.ms_type) {
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1049 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1050 * @hw: pointer to the HW structure
1052 * Sets up Carrier-sense on Transmit and downshift values.
1054 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1061 if (hw->phy.type == e1000_phy_82580) {
1062 ret_val = hw->phy.ops.reset(hw);
1069 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1089 * 0 - Auto (default)
1090 * 1 - MDI mode
1091 * 2 - MDI-X mode
1093 switch (hw->phy.mdix) {
1105 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1109 return e1000_set_master_slave_mode(hw);
1113 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1114 * @hw: pointer to the HW structure
1116 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1119 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1121 struct e1000_phy_info *phy = &hw->phy;
1128 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1129 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1134 if (phy->type != e1000_phy_bm)
1138 * MDI/MDI-X = 0 (default)
1139 * 0 - Auto for all speeds
1140 * 1 - MDI mode
1141 * 2 - MDI-X mode
1142 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1146 switch (phy->mdix) {
1166 * 0 - Disabled
1167 * 1 - Enabled
1170 if (phy->disable_polarity_correction)
1174 if (phy->type == e1000_phy_bm) {
1176 if (phy->id == BME1000_E_PHY_ID_R2) {
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1183 ret_val = phy->ops.commit(hw);
1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1197 if ((phy->type == e1000_phy_m88) &&
1198 (phy->revision < E1000_REVISION_4) &&
1199 (phy->id != BME1000_E_PHY_ID_R2)) {
1203 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1210 if ((phy->revision == E1000_REVISION_2) &&
1211 (phy->id == M88E1111_I_PHY_ID)) {
1212 /* 82573L PHY - set the downshift counter to 5x. */
1222 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1228 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1230 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1235 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1241 ret_val = phy->ops.commit(hw);
1247 if (phy->type == e1000_phy_82578) {
1248 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1253 /* 82578 PHY - set the downshift count to 1x. */
1256 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1266 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1267 * @hw: pointer to the HW structure
1269 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1272 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1274 struct e1000_phy_info *phy = &hw->phy;
1281 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1282 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1287 * MDI/MDI-X = 0 (default)
1288 * 0 - Auto for all speeds
1289 * 1 - MDI mode
1290 * 2 - MDI-X mode
1291 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1295 switch (phy->mdix) {
1304 if (phy->id != M88E1112_E_PHY_ID) {
1319 * 0 - Disabled
1320 * 1 - Enabled
1323 if (phy->disable_polarity_correction)
1327 if (phy->id == M88E1543_E_PHY_ID) {
1330 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1334 ret_val = phy->ops.commit(hw);
1345 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1350 ret_val = phy->ops.commit(hw);
1356 ret_val = e1000_set_master_slave_mode(hw);
1364 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1365 * @hw: pointer to the HW structure
1367 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1370 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1372 struct e1000_phy_info *phy = &hw->phy;
1379 ret_val = hw->phy.ops.reset(hw);
1391 * non-IGP1 PHYs.
1393 if (phy->type == e1000_phy_igp) {
1395 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1403 if (hw->phy.ops.set_d0_lplu_state) {
1404 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1410 /* Configure mdi-mdix settings */
1411 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1417 switch (phy->mdix) {
1430 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1434 /* set auto-master slave resolution settings */
1435 if (hw->mac.autoneg) {
1440 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1442 ret_val = phy->ops.read_reg(hw,
1449 ret_val = phy->ops.write_reg(hw,
1456 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1461 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1466 ret_val = e1000_set_master_slave_mode(hw);
1473 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1474 * @hw: pointer to the HW structure
1476 * Reads the MII auto-neg advertisement register and/or the 1000T control
1477 * register and if the PHY is already setup for auto-negotiation, then
1478 * return successful. Otherwise, setup advertisement and flow control to
1479 * the appropriate values for the wanted auto-negotiation.
1481 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1483 struct e1000_phy_info *phy = &hw->phy;
1490 phy->autoneg_advertised &= phy->autoneg_mask;
1492 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1493 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1497 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1498 /* Read the MII 1000Base-T Control Register (Address 9). */
1499 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1512 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1514 * the 1000Base-T Control Register (Address 9).
1522 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1525 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1531 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1537 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1543 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1549 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1553 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1558 /* Check for a software override of the flow control settings, and
1560 * auto-negotiation is enabled, then software will have to set the
1561 * "PAUSE" bits to the correct value in the Auto-Negotiation
1562 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1566 * 0: Flow control is completely disabled
1567 * 1: Rx flow control is enabled (we can receive pause frames
1569 * 2: Tx flow control is enabled (we can send pause frames
1571 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1572 * other: No software override. The flow control configuration
1575 switch (hw->fc.current_mode) {
1577 /* Flow control (Rx & Tx) is completely disabled by a
1578 * software over-ride.
1583 /* Rx Flow control is enabled, and Tx Flow control is
1584 * disabled, by a software over-ride.
1590 * hw's ability to send PAUSE frames.
1595 /* Tx Flow control is enabled, and Rx Flow control is
1596 * disabled, by a software over-ride.
1602 /* Flow control (both Rx and Tx) is enabled by a software
1603 * over-ride.
1608 DEBUGOUT("Flow control param set incorrectly\n");
1609 return -E1000_ERR_CONFIG;
1612 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1616 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1618 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1619 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1626 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1627 * @hw: pointer to the HW structure
1634 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1636 struct e1000_phy_info *phy = &hw->phy;
1645 phy->autoneg_advertised &= phy->autoneg_mask;
1650 if (!phy->autoneg_advertised)
1651 phy->autoneg_advertised = phy->autoneg_mask;
1653 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1654 ret_val = e1000_phy_setup_autoneg(hw);
1656 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1659 DEBUGOUT("Restarting Auto-Neg\n");
1661 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1664 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1669 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1673 /* Does the user want to wait for Auto-Neg to complete here, or
1676 if (phy->autoneg_wait_to_complete) {
1677 ret_val = e1000_wait_autoneg(hw);
1684 hw->mac.get_link_status = true;
1690 * e1000_setup_copper_link_generic - Configure copper link settings
1691 * @hw: pointer to the HW structure
1693 * Calls the appropriate function to configure the link for auto-neg or forced
1695 * to configure collision distance and flow control are called. If link is
1696 * not established, we return -E1000_ERR_PHY (-2).
1698 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1705 if (hw->mac.autoneg) {
1706 /* Setup autoneg and flow control advertisement and perform
1709 ret_val = e1000_copper_link_autoneg(hw);
1710 if (ret_val && !hw->mac.forced_speed_duplex)
1713 if (!hw->mac.autoneg || (ret_val && hw->mac.forced_speed_duplex)) {
1718 ret_val = hw->phy.ops.force_speed_duplex(hw);
1728 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1735 hw->mac.ops.config_collision_dist(hw);
1736 ret_val = e1000_config_fc_after_link_up_generic(hw);
1745 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1746 * @hw: pointer to the HW structure
1749 * auto-crossover to force MDI manually. Waits for link and returns
1750 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1752 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1754 struct e1000_phy_info *phy = &hw->phy;
1761 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1765 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1767 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1771 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1789 if (phy->autoneg_wait_to_complete) {
1792 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1801 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1809 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1810 * @hw: pointer to the HW structure
1813 * auto-crossover to force MDI manually. Resets the PHY to commit the
1818 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1820 struct e1000_phy_info *phy = &hw->phy;
1827 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1828 if (phy->type != e1000_phy_i210) {
1829 /* Clear Auto-Crossover to force MDI manually. M88E1000
1832 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1850 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1857 ret_val = hw->phy.ops.commit(hw);
1861 if (phy->autoneg_wait_to_complete) {
1864 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1872 switch (hw->phy.id) {
1882 if (hw->phy.type != e1000_phy_m88)
1893 ret_val = phy->ops.write_reg(hw,
1898 ret_val = e1000_phy_reset_dsp_generic(hw);
1905 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1911 if (hw->phy.type != e1000_phy_m88)
1914 if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 hw->phy.id == M88E1340M_E_PHY_ID ||
1916 hw->phy.id == M88E1112_E_PHY_ID)
1918 if (hw->phy.id == I210_I_PHY_ID)
1920 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 (hw->phy.id == M88E1512_E_PHY_ID))
1923 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1927 /* Resetting the phy means we need to re-force TX_CLK in the
1932 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1936 /* In addition, we must re-enable CRS on Tx for both half and full
1939 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1944 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1950 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1951 * @hw: pointer to the HW structure
1957 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1959 struct e1000_phy_info *phy = &hw->phy;
1966 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1970 e1000_phy_force_speed_duplex_setup(hw, &data);
1972 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1976 /* Disable MDI-X support for 10/100 */
1977 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1984 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1992 if (phy->autoneg_wait_to_complete) {
1995 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2004 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2014 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2015 * @hw: pointer to the HW structure
2018 * Forces speed and duplex on the PHY by doing the following: disable flow
2020 * disable auto-negotiation, configure duplex, configure speed, configure
2021 * the collision distance, write configuration to CTRL register. The
2025 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2027 struct e1000_mac_info *mac = &hw->mac;
2028 u32 ctrl;
2032 /* Turn off flow control when forcing speed/duplex */
2033 hw->fc.current_mode = e1000_fc_none;
2036 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2037 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2038 ctrl &= ~E1000_CTRL_SPD_SEL;
2041 ctrl &= ~E1000_CTRL_ASDE;
2047 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2048 ctrl &= ~E1000_CTRL_FD;
2052 ctrl |= E1000_CTRL_FD;
2058 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2059 ctrl |= E1000_CTRL_SPD_100;
2064 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2069 hw->mac.ops.config_collision_dist(hw);
2071 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2075 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2076 * @hw: pointer to the HW structure
2088 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2090 struct e1000_phy_info *phy = &hw->phy;
2096 if (!hw->phy.ops.read_reg)
2099 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2105 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2114 if (phy->smart_speed == e1000_smart_speed_on) {
2115 ret_val = phy->ops.read_reg(hw,
2122 ret_val = phy->ops.write_reg(hw,
2127 } else if (phy->smart_speed == e1000_smart_speed_off) {
2128 ret_val = phy->ops.read_reg(hw,
2135 ret_val = phy->ops.write_reg(hw,
2141 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2142 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2143 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2145 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2165 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2166 * @hw: pointer to the HW structure
2172 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2174 struct e1000_phy_info *phy = &hw->phy;
2180 switch (phy->type) {
2197 phy->speed_downgraded = false;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2204 phy->speed_downgraded = !!(phy_data & mask);
2210 * e1000_check_polarity_m88 - Checks the polarity.
2211 * @hw: pointer to the HW structure
2213 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2217 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2219 struct e1000_phy_info *phy = &hw->phy;
2225 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2228 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2236 * e1000_check_polarity_igp - Checks the polarity.
2237 * @hw: pointer to the HW structure
2239 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2244 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2246 struct e1000_phy_info *phy = &hw->phy;
2255 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2271 ret_val = phy->ops.read_reg(hw, offset, &data);
2274 phy->cable_polarity = ((data & mask)
2282 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2283 * @hw: pointer to the HW structure
2287 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2289 struct e1000_phy_info *phy = &hw->phy;
2297 if (phy->polarity_correction) {
2305 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2308 phy->cable_polarity = ((phy_data & mask)
2316 * e1000_wait_autoneg - Wait for auto-neg completion
2317 * @hw: pointer to the HW structure
2319 * Waits for auto-negotiation to complete or for the auto-negotiation time
2322 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2329 if (!hw->phy.ops.read_reg)
2333 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2334 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2345 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2352 * e1000_phy_has_link_generic - Polls PHY for link
2353 * @hw: pointer to the HW structure
2360 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2368 if (!hw->phy.ops.read_reg)
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2404 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2405 * @hw: pointer to the HW structure
2413 * 1 50 - 80 meters
2414 * 2 80 - 110 meters
2415 * 3 110 - 140 meters
2418 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2420 struct e1000_phy_info *phy = &hw->phy;
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2433 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2434 return -E1000_ERR_PHY;
2436 phy->min_cable_length = e1000_m88_cable_length_table[index];
2437 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2439 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2444 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2446 struct e1000_phy_info *phy = &hw->phy;
2453 switch (hw->phy.id) {
2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2457 (I347AT4_PCDL + phy->addr),
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2471 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2472 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2473 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2480 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2490 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2496 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2503 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2504 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2505 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2516 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2521 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2525 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2533 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2534 return -E1000_ERR_PHY;
2536 phy->min_cable_length = e1000_m88_cable_length_table[index];
2537 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2539 phy->cable_length = (phy->min_cable_length +
2540 phy->max_cable_length) / 2;
2543 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2550 return -E1000_ERR_PHY;
2557 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2558 * @hw: pointer to the HW structure
2567 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2569 struct e1000_phy_info *phy = &hw->phy;
2573 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2585 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2600 return -E1000_ERR_PHY;
2613 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2615 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2617 /* Calculate cable length with the error range of +/- 10 meters. */
2618 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2619 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2620 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2622 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2628 * e1000_get_phy_info_m88 - Retrieve PHY information
2629 * @hw: pointer to the HW structure
2633 * determine the polarity and 10base-T extended distance. Read the PHY
2637 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2639 struct e1000_phy_info *phy = &hw->phy;
2646 if (phy->media_type != e1000_media_type_copper) {
2648 return -E1000_ERR_CONFIG;
2651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2657 return -E1000_ERR_CONFIG;
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2664 phy->polarity_correction = !!(phy_data &
2667 ret_val = e1000_check_polarity_m88(hw);
2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2675 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2678 ret_val = hw->phy.ops.get_cable_length(hw);
2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2686 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2690 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2695 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2696 phy->local_rx = e1000_1000t_rx_status_undefined;
2697 phy->remote_rx = e1000_1000t_rx_status_undefined;
2704 * e1000_get_phy_info_igp - Retrieve igp PHY information
2705 * @hw: pointer to the HW structure
2708 * set/determine 10base-T extended distance and polarity correction. Read
2712 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2714 struct e1000_phy_info *phy = &hw->phy;
2721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2727 return -E1000_ERR_CONFIG;
2730 phy->polarity_correction = true;
2732 ret_val = e1000_check_polarity_igp(hw);
2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2740 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2744 ret_val = phy->ops.get_cable_length(hw);
2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2752 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2756 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2761 phy->local_rx = e1000_1000t_rx_status_undefined;
2762 phy->remote_rx = e1000_1000t_rx_status_undefined;
2769 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2770 * @hw: pointer to the HW structure
2774 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2776 struct e1000_phy_info *phy = &hw->phy;
2783 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2789 return -E1000_ERR_CONFIG;
2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2795 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2797 if (phy->polarity_correction) {
2798 ret_val = e1000_check_polarity_ife(hw);
2803 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2812 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2815 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2816 phy->local_rx = e1000_1000t_rx_status_undefined;
2817 phy->remote_rx = e1000_1000t_rx_status_undefined;
2823 * e1000_phy_sw_reset_generic - PHY software reset
2824 * @hw: pointer to the HW structure
2829 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2836 if (!hw->phy.ops.read_reg)
2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2854 * e1000_phy_hw_reset_generic - PHY hardware reset
2855 * @hw: pointer to the HW structure
2862 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2864 struct e1000_phy_info *phy = &hw->phy;
2866 u32 ctrl;
2870 if (phy->ops.check_reset_block) {
2871 ret_val = phy->ops.check_reset_block(hw);
2876 ret_val = phy->ops.acquire(hw);
2880 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2882 E1000_WRITE_FLUSH(hw);
2884 usec_delay(phy->reset_delay_us);
2886 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2887 E1000_WRITE_FLUSH(hw);
2891 phy->ops.release(hw);
2893 return phy->ops.get_cfg_done(hw);
2897 * e1000_get_cfg_done_generic - Generic configuration done
2898 * @hw: pointer to the HW structure
2900 * Generic function to wait 10 milli-seconds for configuration to complete
2903 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2913 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2914 * @hw: pointer to the HW structure
2918 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2923 /* Enable rise/fall, 10-mode work in class-A */
2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2978 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2980 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2981 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2984 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2986 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2988 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2990 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2996 * e1000_get_phy_type_from_id - Get PHY type from id
3061 * e1000_determine_phy_address - Determines PHY address.
3062 * @hw: pointer to the HW structure
3068 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3074 hw->phy.id = phy_type;
3077 hw->phy.addr = phy_addr;
3081 e1000_get_phy_id(hw);
3082 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3084 /* If phy_type is valid, break - we found our
3095 return -E1000_ERR_PHY_TYPE;
3099 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3116 * e1000_write_phy_reg_bm - Write BM PHY register
3117 * @hw: pointer to the HW structure
3124 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3131 ret_val = hw->phy.ops.acquire(hw);
3137 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3151 if (hw->phy.addr == 1) {
3160 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3166 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3170 hw->phy.ops.release(hw);
3175 * e1000_read_phy_reg_bm - Read BM PHY register
3176 * @hw: pointer to the HW structure
3184 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3191 ret_val = hw->phy.ops.acquire(hw);
3197 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3202 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3211 if (hw->phy.addr == 1) {
3220 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3226 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3229 hw->phy.ops.release(hw);
3234 * e1000_read_phy_reg_bm2 - Read BM PHY register
3235 * @hw: pointer to the HW structure
3243 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3250 ret_val = hw->phy.ops.acquire(hw);
3256 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3261 hw->phy.addr = 1;
3265 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3272 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3275 hw->phy.ops.release(hw);
3280 * e1000_write_phy_reg_bm2 - Write BM PHY register
3281 * @hw: pointer to the HW structure
3288 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3295 ret_val = hw->phy.ops.acquire(hw);
3301 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3306 hw->phy.addr = 1;
3310 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3317 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3321 hw->phy.ops.release(hw);
3326 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3327 * @hw: pointer to the HW structure
3333 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3341 return -E1000_ERR_PARAM;
3343 /* All page select, port ctrl and wakeup registers use phy address 1 */
3344 hw->phy.addr = 1;
3347 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3353 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3367 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3374 /* Select Host Wakeup Registers page - caller now able to write
3377 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3381 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3382 * @hw: pointer to the HW structure
3391 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3398 return -E1000_ERR_PARAM;
3401 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3408 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3417 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3418 * @hw: pointer to the HW structure
3441 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3452 if ((hw->mac.type == e1000_pchlan) &&
3453 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3459 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3477 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3481 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3491 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3497 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3498 * @hw: pointer to the HW structure
3504 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3509 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3511 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3515 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3516 * @hw: pointer to the HW structure
3522 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3527 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3529 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3534 * __e1000_read_phy_reg_hv - Read HV PHY register
3535 * @hw: pointer to the HW structure
3545 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3551 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3556 ret_val = hw->phy.ops.acquire(hw);
3562 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3568 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3579 ret_val = e1000_set_page_igp(hw,
3582 hw->phy.addr = phy_addr;
3592 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3596 hw->phy.ops.release(hw);
3602 * e1000_read_phy_reg_hv - Read HV PHY register
3603 * @hw: pointer to the HW structure
3611 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3613 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3617 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3618 * @hw: pointer to the HW structure
3625 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3627 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3631 * e1000_read_phy_reg_page_hv - Read HV PHY register
3632 * @hw: pointer to the HW structure
3639 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3641 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3645 * __e1000_write_phy_reg_hv - Write HV PHY register
3646 * @hw: pointer to the HW structure
3655 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3661 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3666 ret_val = hw->phy.ops.acquire(hw);
3672 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3678 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3690 if ((hw->phy.type == e1000_phy_82578) &&
3691 (hw->phy.revision >= 1) &&
3692 (hw->phy.addr == 2) &&
3696 ret_val = e1000_access_phy_debug_regs_hv(hw,
3705 ret_val = e1000_set_page_igp(hw,
3708 hw->phy.addr = phy_addr;
3718 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3723 hw->phy.ops.release(hw);
3729 * e1000_write_phy_reg_hv - Write HV PHY register
3730 * @hw: pointer to the HW structure
3737 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3739 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3743 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3744 * @hw: pointer to the HW structure
3751 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3753 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3757 * e1000_write_phy_reg_page_hv - Write HV PHY register
3758 * @hw: pointer to the HW structure
3765 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3767 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3771 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3785 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3786 * @hw: pointer to the HW structure
3796 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3806 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3811 hw->phy.addr = 2;
3814 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3822 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3824 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3833 * e1000_link_stall_workaround_hv - Si workaround
3834 * @hw: pointer to the HW structure
3843 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3850 if (hw->phy.type != e1000_phy_82578)
3854 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3859 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3873 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3879 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3884 * e1000_check_polarity_82577 - Checks the polarity.
3885 * @hw: pointer to the HW structure
3887 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3891 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3893 struct e1000_phy_info *phy = &hw->phy;
3899 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3902 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3910 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3911 * @hw: pointer to the HW structure
3915 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3917 struct e1000_phy_info *phy = &hw->phy;
3924 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3928 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3930 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3936 if (phy->autoneg_wait_to_complete) {
3939 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3948 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3956 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3957 * @hw: pointer to the HW structure
3960 * set/determine 10base-T extended distance and polarity correction. Read
3964 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3966 struct e1000_phy_info *phy = &hw->phy;
3973 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3979 return -E1000_ERR_CONFIG;
3982 phy->polarity_correction = true;
3984 ret_val = e1000_check_polarity_82577(hw);
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3992 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3996 ret_val = hw->phy.ops.get_cable_length(hw);
4000 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4004 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4008 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4012 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4013 phy->local_rx = e1000_1000t_rx_status_undefined;
4014 phy->remote_rx = e1000_1000t_rx_status_undefined;
4021 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4022 * @hw: pointer to the HW structure
4027 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4029 struct e1000_phy_info *phy = &hw->phy;
4035 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4043 return -E1000_ERR_PHY;
4045 phy->cable_length = length;
4051 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4052 * @hw: pointer to the HW structure
4059 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4067 ret_val = hw->phy.ops.acquire(hw);
4071 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4074 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4077 hw->phy.ops.release(hw);
4082 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4083 * @hw: pointer to the HW structure
4091 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4099 ret_val = hw->phy.ops.acquire(hw);
4103 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4106 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4109 hw->phy.ops.release(hw);
4114 * e1000_read_phy_reg_mphy - Read mPHY control register
4115 * @hw: pointer to the HW structure
4122 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4131 ready = e1000_is_mphy_ready(hw);
4133 return -E1000_ERR_PHY;
4136 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4139 ready = e1000_is_mphy_ready(hw);
4141 return -E1000_ERR_PHY;
4143 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4147 ready = e1000_is_mphy_ready(hw);
4149 return -E1000_ERR_PHY;
4155 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4158 ready = e1000_is_mphy_ready(hw);
4160 return -E1000_ERR_PHY;
4161 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4165 ready = e1000_is_mphy_ready(hw);
4167 return -E1000_ERR_PHY;
4168 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4175 * e1000_write_phy_reg_mphy - Write mPHY control register
4176 * @hw: pointer to the HW structure
4183 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4193 ready = e1000_is_mphy_ready(hw);
4195 return -E1000_ERR_PHY;
4198 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4201 ready = e1000_is_mphy_ready(hw);
4203 return -E1000_ERR_PHY;
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4209 ready = e1000_is_mphy_ready(hw);
4211 return -E1000_ERR_PHY;
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4223 ready = e1000_is_mphy_ready(hw);
4225 return -E1000_ERR_PHY;
4226 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4230 ready = e1000_is_mphy_ready(hw);
4232 return -E1000_ERR_PHY;
4233 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4240 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4241 * @hw: pointer to the HW structure
4245 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4252 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4269 * __e1000_access_xmdio_reg - Read/write XMDIO register
4270 * @hw: pointer to the HW structure
4276 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4283 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4287 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4291 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4297 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4299 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4304 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4312 * e1000_read_xmdio_reg - Read XMDIO register
4313 * @hw: pointer to the HW structure
4318 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4322 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4326 * e1000_write_xmdio_reg - Write XMDIO register
4327 * @hw: pointer to the HW structure
4332 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4336 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,