Lines Matching full:hw
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
66 * @hw: pointer to the HW structure
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
105 * @hw: pointer to the HW structure
108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
117 * @hw: pointer to the HW structure
121 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
130 * @hw: pointer to the HW structure
132 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
140 * @hw: pointer to the HW structure
143 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
152 * @hw: pointer to the HW structure
156 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
165 * @hw: pointer to hardware structure
171 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
182 * @hw: pointer to hardware structure
188 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
199 * @hw: pointer to the HW structure
205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
211 manc = E1000_READ_REG(hw, E1000_MANC);
219 * @hw: pointer to the HW structure
224 s32 e1000_get_phy_id(struct e1000_hw *hw)
226 struct e1000_phy_info *phy = &hw->phy;
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
261 * @hw: pointer to the HW structure
265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
271 if (!hw->phy.ops.write_reg)
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
283 * @hw: pointer to the HW structure
290 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
292 struct e1000_phy_info *phy = &hw->phy;
310 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
318 mdic = E1000_READ_REG(hw, E1000_MDIC);
341 if (hw->mac.type == e1000_pch2lan)
349 * @hw: pointer to the HW structure
355 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
357 struct e1000_phy_info *phy = &hw->phy;
376 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
384 mdic = E1000_READ_REG(hw, E1000_MDIC);
406 if (hw->mac.type == e1000_pch2lan)
414 * @hw: pointer to the HW structure
421 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
423 struct e1000_phy_info *phy = &hw->phy;
436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
462 * @hw: pointer to the HW structure
468 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
470 struct e1000_phy_info *phy = &hw->phy;
477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
479 hw->phy.addr);
495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
500 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
518 * @hw: pointer to the HW structure
529 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
549 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
554 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
573 * @hw: pointer to the HW structure
584 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
608 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
614 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
627 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
646 * @hw: pointer to the HW structure
654 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
660 if (!hw->phy.ops.acquire)
663 ret_val = hw->phy.ops.acquire(hw);
667 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
670 hw->phy.ops.release(hw);
677 * @hw: pointer to the HW structure
684 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
690 if (!hw->phy.ops.acquire)
693 ret_val = hw->phy.ops.acquire(hw);
697 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
700 hw->phy.ops.release(hw);
707 * @hw: pointer to the HW structure
714 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
720 hw->phy.addr = 1;
722 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
727 * @hw: pointer to the HW structure
736 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
744 if (!hw->phy.ops.acquire)
747 ret_val = hw->phy.ops.acquire(hw);
753 ret_val = e1000_write_phy_reg_mdic(hw,
757 ret_val = e1000_read_phy_reg_mdic(hw,
761 hw->phy.ops.release(hw);
768 * @hw: pointer to the HW structure
776 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
778 return __e1000_read_phy_reg_igp(hw, offset, data, false);
783 * @hw: pointer to the HW structure
790 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
792 return __e1000_read_phy_reg_igp(hw, offset, data, true);
797 * @hw: pointer to the HW structure
805 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
813 if (!hw->phy.ops.acquire)
816 ret_val = hw->phy.ops.acquire(hw);
822 ret_val = e1000_write_phy_reg_mdic(hw,
826 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
830 hw->phy.ops.release(hw);
837 * @hw: pointer to the HW structure
844 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
846 return __e1000_write_phy_reg_igp(hw, offset, data, false);
851 * @hw: pointer to the HW structure
858 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
860 return __e1000_write_phy_reg_igp(hw, offset, data, true);
865 * @hw: pointer to the HW structure
874 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
884 if (!hw->phy.ops.acquire)
887 ret_val = hw->phy.ops.acquire(hw);
894 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
895 E1000_WRITE_FLUSH(hw);
899 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
903 hw->phy.ops.release(hw);
910 * @hw: pointer to the HW structure
918 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
920 return __e1000_read_kmrn_reg(hw, offset, data, false);
925 * @hw: pointer to the HW structure
933 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
935 return __e1000_read_kmrn_reg(hw, offset, data, true);
940 * @hw: pointer to the HW structure
949 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
959 if (!hw->phy.ops.acquire)
962 ret_val = hw->phy.ops.acquire(hw);
969 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
970 E1000_WRITE_FLUSH(hw);
975 hw->phy.ops.release(hw);
982 * @hw: pointer to the HW structure
989 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
991 return __e1000_write_kmrn_reg(hw, offset, data, false);
996 * @hw: pointer to the HW structure
1003 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1005 return __e1000_write_kmrn_reg(hw, offset, data, true);
1010 * @hw: pointer to the HW structure
1014 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1030 switch (hw->phy.ms_type) {
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1050 * @hw: pointer to the HW structure
1054 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1061 if (hw->phy.type == e1000_phy_82580) {
1062 ret_val = hw->phy.ops.reset(hw);
1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1093 switch (hw->phy.mdix) {
1105 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1109 return e1000_set_master_slave_mode(hw);
1114 * @hw: pointer to the HW structure
1119 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1121 struct e1000_phy_info *phy = &hw->phy;
1129 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1183 ret_val = phy->ops.commit(hw);
1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1203 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1222 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1230 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1235 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1241 ret_val = phy->ops.commit(hw);
1248 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1256 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1267 * @hw: pointer to the HW structure
1272 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1274 struct e1000_phy_info *phy = &hw->phy;
1282 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1330 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1334 ret_val = phy->ops.commit(hw);
1345 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1350 ret_val = phy->ops.commit(hw);
1356 ret_val = e1000_set_master_slave_mode(hw);
1365 * @hw: pointer to the HW structure
1370 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1372 struct e1000_phy_info *phy = &hw->phy;
1379 ret_val = hw->phy.ops.reset(hw);
1395 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1403 if (hw->phy.ops.set_d0_lplu_state) {
1404 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1411 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1430 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1435 if (hw->mac.autoneg) {
1442 ret_val = phy->ops.read_reg(hw,
1449 ret_val = phy->ops.write_reg(hw,
1456 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1461 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1466 ret_val = e1000_set_master_slave_mode(hw);
1474 * @hw: pointer to the HW structure
1481 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1483 struct e1000_phy_info *phy = &hw->phy;
1493 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1499 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1575 switch (hw->fc.current_mode) {
1590 * hw's ability to send PAUSE frames.
1612 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1619 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1627 * @hw: pointer to the HW structure
1634 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1636 struct e1000_phy_info *phy = &hw->phy;
1654 ret_val = e1000_phy_setup_autoneg(hw);
1664 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1669 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1677 ret_val = e1000_wait_autoneg(hw);
1684 hw->mac.get_link_status = true;
1691 * @hw: pointer to the HW structure
1698 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1705 if (hw->mac.autoneg) {
1709 ret_val = e1000_copper_link_autoneg(hw);
1710 if (ret_val && !hw->mac.forced_speed_duplex)
1713 if (!hw->mac.autoneg || (ret_val && hw->mac.forced_speed_duplex)) {
1718 ret_val = hw->phy.ops.force_speed_duplex(hw);
1728 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1735 hw->mac.ops.config_collision_dist(hw);
1736 ret_val = e1000_config_fc_after_link_up_generic(hw);
1746 * @hw: pointer to the HW structure
1752 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1754 struct e1000_phy_info *phy = &hw->phy;
1761 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1765 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1767 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1781 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1792 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1801 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1810 * @hw: pointer to the HW structure
1818 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1820 struct e1000_phy_info *phy = &hw->phy;
1832 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1838 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1850 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1852 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1857 ret_val = hw->phy.ops.commit(hw);
1864 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1872 switch (hw->phy.id) {
1882 if (hw->phy.type != e1000_phy_m88)
1893 ret_val = phy->ops.write_reg(hw,
1898 ret_val = e1000_phy_reset_dsp_generic(hw);
1905 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1911 if (hw->phy.type != e1000_phy_m88)
1914 if (hw->phy.id == I347AT4_E_PHY_ID ||
1915 hw->phy.id == M88E1340M_E_PHY_ID ||
1916 hw->phy.id == M88E1112_E_PHY_ID)
1918 if (hw->phy.id == I210_I_PHY_ID)
1920 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1921 (hw->phy.id == M88E1512_E_PHY_ID))
1923 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1932 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1939 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1944 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1951 * @hw: pointer to the HW structure
1957 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1959 struct e1000_phy_info *phy = &hw->phy;
1966 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1970 e1000_phy_force_speed_duplex_setup(hw, &data);
1972 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1977 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1984 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1995 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2004 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2015 * @hw: pointer to the HW structure
2025 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2027 struct e1000_mac_info *mac = &hw->mac;
2033 hw->fc.current_mode = e1000_fc_none;
2036 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2069 hw->mac.ops.config_collision_dist(hw);
2071 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2076 * @hw: pointer to the HW structure
2088 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2090 struct e1000_phy_info *phy = &hw->phy;
2096 if (!hw->phy.ops.read_reg)
2099 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2105 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2115 ret_val = phy->ops.read_reg(hw,
2122 ret_val = phy->ops.write_reg(hw,
2128 ret_val = phy->ops.read_reg(hw,
2135 ret_val = phy->ops.write_reg(hw,
2145 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2151 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2157 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2166 * @hw: pointer to the HW structure
2172 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2174 struct e1000_phy_info *phy = &hw->phy;
2201 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2211 * @hw: pointer to the HW structure
2217 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2219 struct e1000_phy_info *phy = &hw->phy;
2225 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2237 * @hw: pointer to the HW structure
2244 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2246 struct e1000_phy_info *phy = &hw->phy;
2255 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2271 ret_val = phy->ops.read_reg(hw, offset, &data);
2283 * @hw: pointer to the HW structure
2287 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2289 struct e1000_phy_info *phy = &hw->phy;
2305 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2317 * @hw: pointer to the HW structure
2322 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2329 if (!hw->phy.ops.read_reg)
2334 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2337 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2353 * @hw: pointer to the HW structure
2360 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2368 if (!hw->phy.ops.read_reg)
2376 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2405 * @hw: pointer to the HW structure
2418 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2420 struct e1000_phy_info *phy = &hw->phy;
2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2444 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2446 struct e1000_phy_info *phy = &hw->phy;
2453 switch (hw->phy.id) {
2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2480 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2485 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2490 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2496 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2508 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2516 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2521 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2525 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2543 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2558 * @hw: pointer to the HW structure
2567 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2569 struct e1000_phy_info *phy = &hw->phy;
2585 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2629 * @hw: pointer to the HW structure
2637 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2639 struct e1000_phy_info *phy = &hw->phy;
2651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2667 ret_val = e1000_check_polarity_m88(hw);
2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2678 ret_val = hw->phy.ops.get_cable_length(hw);
2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2705 * @hw: pointer to the HW structure
2712 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2714 struct e1000_phy_info *phy = &hw->phy;
2721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2732 ret_val = e1000_check_polarity_igp(hw);
2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2744 ret_val = phy->ops.get_cable_length(hw);
2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2770 * @hw: pointer to the HW structure
2774 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2776 struct e1000_phy_info *phy = &hw->phy;
2783 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2798 ret_val = e1000_check_polarity_ife(hw);
2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2824 * @hw: pointer to the HW structure
2829 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2836 if (!hw->phy.ops.read_reg)
2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2855 * @hw: pointer to the HW structure
2862 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2864 struct e1000_phy_info *phy = &hw->phy;
2871 ret_val = phy->ops.check_reset_block(hw);
2876 ret_val = phy->ops.acquire(hw);
2880 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2882 E1000_WRITE_FLUSH(hw);
2886 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2887 E1000_WRITE_FLUSH(hw);
2891 phy->ops.release(hw);
2893 return phy->ops.get_cfg_done(hw);
2898 * @hw: pointer to the HW structure
2903 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2914 * @hw: pointer to the HW structure
2918 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2978 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2980 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2984 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2986 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2988 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2990 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
3062 * @hw: pointer to the HW structure
3068 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3074 hw->phy.id = phy_type;
3077 hw->phy.addr = phy_addr;
3081 e1000_get_phy_id(hw);
3082 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3117 * @hw: pointer to the HW structure
3124 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3131 ret_val = hw->phy.ops.acquire(hw);
3137 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3142 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3151 if (hw->phy.addr == 1) {
3160 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3166 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3170 hw->phy.ops.release(hw);
3176 * @hw: pointer to the HW structure
3184 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3191 ret_val = hw->phy.ops.acquire(hw);
3197 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3202 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3211 if (hw->phy.addr == 1) {
3220 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3226 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3229 hw->phy.ops.release(hw);
3235 * @hw: pointer to the HW structure
3243 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3250 ret_val = hw->phy.ops.acquire(hw);
3256 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3261 hw->phy.addr = 1;
3265 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3272 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3275 hw->phy.ops.release(hw);
3281 * @hw: pointer to the HW structure
3288 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3295 ret_val = hw->phy.ops.acquire(hw);
3301 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3306 hw->phy.addr = 1;
3310 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3317 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3321 hw->phy.ops.release(hw);
3327 * @hw: pointer to the HW structure
3333 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3344 hw->phy.addr = 1;
3347 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3353 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3367 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3377 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3382 * @hw: pointer to the HW structure
3391 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3401 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3408 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3418 * @hw: pointer to the HW structure
3441 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3452 if ((hw->mac.type == e1000_pchlan) &&
3453 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3459 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3469 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3477 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3481 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3491 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3498 * @hw: pointer to the HW structure
3504 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3509 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3511 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3516 * @hw: pointer to the HW structure
3522 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3527 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3529 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3535 * @hw: pointer to the HW structure
3545 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3551 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3556 ret_val = hw->phy.ops.acquire(hw);
3562 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3568 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3579 ret_val = e1000_set_page_igp(hw,
3582 hw->phy.addr = phy_addr;
3592 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3596 hw->phy.ops.release(hw);
3603 * @hw: pointer to the HW structure
3611 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3613 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3618 * @hw: pointer to the HW structure
3625 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3627 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3632 * @hw: pointer to the HW structure
3639 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3641 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3646 * @hw: pointer to the HW structure
3655 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3661 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3666 ret_val = hw->phy.ops.acquire(hw);
3672 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3678 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3690 if ((hw->phy.type == e1000_phy_82578) &&
3691 (hw->phy.revision >= 1) &&
3692 (hw->phy.addr == 2) &&
3696 ret_val = e1000_access_phy_debug_regs_hv(hw,
3705 ret_val = e1000_set_page_igp(hw,
3708 hw->phy.addr = phy_addr;
3718 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3723 hw->phy.ops.release(hw);
3730 * @hw: pointer to the HW structure
3737 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3739 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3744 * @hw: pointer to the HW structure
3751 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3753 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3758 * @hw: pointer to the HW structure
3765 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3767 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3786 * @hw: pointer to the HW structure
3796 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3806 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3811 hw->phy.addr = 2;
3814 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3822 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3824 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3834 * @hw: pointer to the HW structure
3843 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3850 if (hw->phy.type != e1000_phy_82578)
3854 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3859 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3873 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3879 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3885 * @hw: pointer to the HW structure
3891 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3893 struct e1000_phy_info *phy = &hw->phy;
3899 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3911 * @hw: pointer to the HW structure
3915 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3917 struct e1000_phy_info *phy = &hw->phy;
3924 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3928 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3930 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3939 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3948 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3957 * @hw: pointer to the HW structure
3964 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3966 struct e1000_phy_info *phy = &hw->phy;
3973 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3984 ret_val = e1000_check_polarity_82577(hw);
3988 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3996 ret_val = hw->phy.ops.get_cable_length(hw);
4000 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4022 * @hw: pointer to the HW structure
4027 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4029 struct e1000_phy_info *phy = &hw->phy;
4035 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4052 * @hw: pointer to the HW structure
4059 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4067 ret_val = hw->phy.ops.acquire(hw);
4071 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4074 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4077 hw->phy.ops.release(hw);
4083 * @hw: pointer to the HW structure
4091 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4099 ret_val = hw->phy.ops.acquire(hw);
4103 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4106 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4109 hw->phy.ops.release(hw);
4115 * @hw: pointer to the HW structure
4122 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4131 ready = e1000_is_mphy_ready(hw);
4136 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4139 ready = e1000_is_mphy_ready(hw);
4143 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4147 ready = e1000_is_mphy_ready(hw);
4155 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4158 ready = e1000_is_mphy_ready(hw);
4161 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4165 ready = e1000_is_mphy_ready(hw);
4168 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4176 * @hw: pointer to the HW structure
4183 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4193 ready = e1000_is_mphy_ready(hw);
4198 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4201 ready = e1000_is_mphy_ready(hw);
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4209 ready = e1000_is_mphy_ready(hw);
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4223 ready = e1000_is_mphy_ready(hw);
4226 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4230 ready = e1000_is_mphy_ready(hw);
4233 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4241 * @hw: pointer to the HW structure
4245 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4252 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4270 * @hw: pointer to the HW structure
4276 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4283 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4287 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4291 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4297 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4299 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4304 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4313 * @hw: pointer to the HW structure
4318 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4322 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4327 * @hw: pointer to the HW structure
4332 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4336 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,