Lines Matching defs:mphy_ctrl
4124 u32 mphy_ctrl = 0;
4136 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4137 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4142 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4143 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4152 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4155 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4186 u32 mphy_ctrl = 0;
4198 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4199 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4204 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4215 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4217 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4218 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4248 u32 mphy_ctrl = 0;
4252 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4253 if (mphy_ctrl & E1000_MPHY_BUSY) {