Lines Matching +full:tx +full:- +full:threshold
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
413 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
417 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
419 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
425 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
548 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
567 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
568 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
590 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
591 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
592 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
593 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
606 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
618 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
623 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
633 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
634 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
645 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
646 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
647 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
648 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
655 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
662 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
663 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
664 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
665 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
675 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
676 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
677 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
760 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
761 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
856 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
857 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
858 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
865 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
871 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
959 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
960 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
971 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
972 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
984 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
985 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1010 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1024 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1311 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1461 /* DMA Coalescing Rx Threshold */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1471 /* DMA Coalescing Transmit Threshold */
1476 /* Rx Traffic Rate Threshold */
1484 /* Flow ctrl Rx Threshold High val */
1492 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1496 #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */