Lines Matching +full:bit +full:- +full:banging
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
93 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
114 /* Receive Descriptor bit definitions */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
338 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
393 /* Transmit Descriptor bit definitions */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
537 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
538 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
539 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
541 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
562 /* If this bit asserted, the driver should claim the interrupt */
583 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
603 * Set/Read Register. Each bit is documented below:
728 /* Loop limit on how long we wait for auto-negotiation to complete */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
808 /* ETQF register bit definitions */
823 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
825 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
827 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
829 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
834 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
836 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
849 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
963 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
975 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
987 /* 1000BASE-T Control Register */
988 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1003 /* 1000BASE-T Status Register */
1005 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1015 /* PHY 1000 MII Register/Bit Definitions */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1041 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1044 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1075 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1259 /* Bit definitions for valid PHY IDs.
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1518 /* Lan ID bit field offset in status register */