Lines Matching +full:queue +full:- +full:pkt +full:- +full:tx

2   SPDX-License-Identifier: BSD-3-Clause
4   Copyright (c) 2001-2020, Intel Corporation
46  * These entries are also used for MAC-based filtering.
193 #define E1000_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
250 #define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
252 #define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
253 #define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
259 /* 1st & Last TSO-full iSCSI PDU*/
265 #define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
266 #define E1000_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wbk flushing */
267 /* Tx Queue Arbitration Priority 0=low, 1=high */
271 #define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
287 #define E1000_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
288 #define E1000_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
289 #define E1000_DCA_TXCTRL_DESC_RRO_EN	(1 << 9) /* Tx rd Desc Relax Order */
290 #define E1000_DCA_TXCTRL_TX_WB_RO_EN	(1 << 11) /* Tx Desc writeback RO bit */
291 #define E1000_DCA_TXCTRL_DATA_RRO_EN	(1 << 13) /* Tx rd data Relax Order */
293 #define E1000_DCA_TXCTRL_CPUID_MASK_82576	0xFF000000 /* Tx CPUID Mask */
295 #define E1000_DCA_TXCTRL_CPUID_SHIFT_82576	24 /* Tx CPUID */
299 #define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
300 #define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
301 #define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */