Lines Matching +full:queue +full:- +full:pkt +full:- +full:rx

2   SPDX-License-Identifier: BSD-3-Clause
4   Copyright (c) 2001-2020, Intel Corporation
46  * These entries are also used for MAC-based filtering.
177 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
193 #define E1000_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
226 #define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
250 #define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
252 #define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
253 #define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
259 /* 1st & Last TSO-full iSCSI PDU*/
265 #define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
267 /* Tx Queue Arbitration Priority 0=low, 1=high */
271 #define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
272 #define E1000_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
281 #define E1000_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
282 #define E1000_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
283 #define E1000_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
284 #define E1000_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
285 #define E1000_DCA_RXCTRL_DESC_RRO_EN	(1 << 9) /* DCA Rx Desc Relax Order */
294 #define E1000_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
296 #define E1000_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
299 #define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
300 #define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
301 #define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
354 #define E1000_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
355 #define E1000_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
391 /* Rx packet buffer size defines */