Lines Matching +full:config +full:- +full:complete +full:- +full:timeout +full:- +full:us
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
121 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
134 switch (hw->mac.type) {
155 * e1000_init_phy_params_82575 - Initialize PHY function ptrs
160 struct e1000_phy_info *phy = &hw->phy;
166 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
167 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
169 if (hw->phy.media_type != e1000_media_type_copper) {
170 phy->type = e1000_phy_none;
174 phy->ops.power_up = e1000_power_up_phy_copper;
175 phy->ops.power_down = e1000_power_down_phy_copper_base;
177 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
178 phy->reset_delay_us = 100;
180 phy->ops.acquire = e1000_acquire_phy_base;
181 phy->ops.check_reset_block = e1000_check_reset_block_generic;
182 phy->ops.commit = e1000_phy_sw_reset_generic;
183 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
184 phy->ops.release = e1000_release_phy_base;
189 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
192 phy->ops.reset = e1000_phy_hw_reset_generic;
200 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
203 switch (hw->mac.type) {
207 phy->ops.read_reg = e1000_read_phy_reg_82580;
208 phy->ops.write_reg = e1000_write_phy_reg_82580;
212 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
213 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
216 phy->ops.read_reg = e1000_read_phy_reg_igp;
217 phy->ops.write_reg = e1000_write_phy_reg_igp;
221 /* Set phy->phy_addr and phy->id. */
225 switch (phy->id) {
231 phy->type = e1000_phy_m88;
232 phy->ops.check_polarity = e1000_check_polarity_m88;
233 phy->ops.get_info = e1000_get_phy_info_m88;
234 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
235 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
238 phy->type = e1000_phy_m88;
239 phy->ops.check_polarity = e1000_check_polarity_m88;
240 phy->ops.get_info = e1000_get_phy_info_m88;
241 phy->ops.get_cable_length = e1000_get_cable_length_m88;
242 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
246 phy->type = e1000_phy_igp_3;
247 phy->ops.check_polarity = e1000_check_polarity_igp;
248 phy->ops.get_info = e1000_get_phy_info_igp;
249 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
252 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
256 phy->type = e1000_phy_82580;
257 phy->ops.check_polarity = e1000_check_polarity_82577;
258 phy->ops.get_info = e1000_get_phy_info_82577;
259 phy->ops.get_cable_length = e1000_get_cable_length_82577;
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
262 phy->ops.force_speed_duplex =
266 phy->type = e1000_phy_i210;
267 phy->ops.check_polarity = e1000_check_polarity_m88;
268 phy->ops.get_info = e1000_get_phy_info_m88;
269 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
270 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
271 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
272 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
275 ret_val = -E1000_ERR_PHY;
280 switch (phy->id) {
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
297 hw->mac.ops.check_for_link =
320 * e1000_init_mac_params_82575 - Init MAC func ptrs.
325 struct e1000_mac_info *mac = &hw->mac;
326 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
336 mac->mta_reg_count = 128;
338 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
340 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
341 if (mac->type == e1000_82576)
342 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
343 if (mac->type == e1000_82580)
344 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
345 if (mac->type == e1000_i350 || mac->type == e1000_i354)
346 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
349 if (mac->type >= e1000_i350)
350 dev_spec->eee_disable = false;
353 if (mac->type >= e1000_i210)
354 dev_spec->clear_semaphore_once = true;
357 mac->asf_firmware_present = true;
359 mac->has_fwsm = true;
361 mac->arc_subsystem_valid =
367 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
369 if (mac->type >= e1000_82580)
370 mac->ops.reset_hw = e1000_reset_hw_82580;
372 mac->ops.reset_hw = e1000_reset_hw_82575;
374 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
375 mac->ops.init_hw = e1000_init_hw_i210;
377 mac->ops.init_hw = e1000_init_hw_82575;
379 mac->ops.setup_link = e1000_setup_link_generic;
381 mac->ops.setup_physical_interface =
382 (hw->phy.media_type == e1000_media_type_copper)
385 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
387 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
389 mac->ops.check_for_link = e1000_check_for_link_82575;
391 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
393 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
395 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
396 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
398 mac->ops.write_vfta = e1000_write_vfta_i350;
400 mac->ops.clear_vfta = e1000_clear_vfta_i350;
403 mac->ops.write_vfta = e1000_write_vfta_generic;
405 mac->ops.clear_vfta = e1000_clear_vfta_generic;
407 if (hw->mac.type >= e1000_82580)
408 mac->ops.validate_mdi_setting =
411 mac->ops.id_led_init = e1000_id_led_init_generic;
413 mac->ops.blink_led = e1000_blink_led_generic;
415 mac->ops.setup_led = e1000_setup_led_generic;
417 mac->ops.cleanup_led = e1000_cleanup_led_generic;
419 mac->ops.led_on = e1000_led_on_generic;
420 mac->ops.led_off = e1000_led_off_generic;
422 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
424 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
426 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync;
428 mac->ops.release_swfw_sync = e1000_release_swfw_sync;
431 hw->mac.ops.set_lan_id(hw);
437 * e1000_init_nvm_params_82575 - Initialize NVM function ptrs
442 struct e1000_nvm_info *nvm = &hw->nvm;
450 /* Added to a constant, "size" becomes the left-shift value
461 nvm->word_size = 1 << size;
462 if (hw->mac.type < e1000_i210) {
463 nvm->opcode_bits = 8;
464 nvm->delay_usec = 1;
466 switch (nvm->override) {
468 nvm->page_size = 32;
469 nvm->address_bits = 16;
472 nvm->page_size = 8;
473 nvm->address_bits = 8;
476 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
477 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
481 if (nvm->word_size == (1 << 15))
482 nvm->page_size = 128;
484 nvm->type = e1000_nvm_eeprom_spi;
486 nvm->type = e1000_nvm_flash_hw;
490 nvm->ops.acquire = e1000_acquire_nvm_82575;
491 nvm->ops.release = e1000_release_nvm_82575;
492 if (nvm->word_size < (1 << 15))
493 nvm->ops.read = e1000_read_nvm_eerd;
495 nvm->ops.read = e1000_read_nvm_spi;
497 nvm->ops.write = e1000_write_nvm_spi;
498 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
499 nvm->ops.update = e1000_update_nvm_checksum_generic;
500 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
503 switch (hw->mac.type) {
505 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
506 nvm->ops.update = e1000_update_nvm_checksum_82580;
509 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
510 nvm->ops.update = e1000_update_nvm_checksum_i350;
520 * e1000_init_function_pointers_82575 - Init func ptrs.
529 hw->mac.ops.init_params = e1000_init_mac_params_82575;
530 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
531 hw->phy.ops.init_params = e1000_init_phy_params_82575;
532 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
536 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
547 s32 ret_val = -E1000_ERR_PARAM;
556 ret_val = hw->phy.ops.acquire(hw);
562 hw->phy.ops.release(hw);
569 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
580 s32 ret_val = -E1000_ERR_PARAM;
589 ret_val = hw->phy.ops.acquire(hw);
595 hw->phy.ops.release(hw);
602 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
610 struct e1000_phy_info *phy = &hw->phy;
619 if (hw->mac.type == e1000_i354)
624 * we find one that works. For non-SGMII PHYs
626 * work. The result of this function should mean phy->phy_addr
627 * and phy->id are set correctly.
630 phy->addr = 1;
636 switch (hw->mac.type) {
641 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
650 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
653 ret_val = -E1000_ERR_PHY;
670 * Therefore, we need to test 1-7
672 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
676 phy_id, phy->addr);
685 phy->addr);
690 if (phy->addr == 8) {
691 phy->addr = 0;
692 ret_val = -E1000_ERR_PHY;
705 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
713 struct e1000_phy_info *phy = &hw->phy;
719 * available to us at this time.
724 if (!(hw->phy.ops.write_reg))
731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
735 ret_val = hw->phy.ops.commit(hw);
739 if (phy->id == M88E1512_E_PHY_ID)
746 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
760 struct e1000_phy_info *phy = &hw->phy;
766 if (!(hw->phy.ops.read_reg))
769 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
781 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
798 if (phy->smart_speed == e1000_smart_speed_on) {
799 ret_val = phy->ops.read_reg(hw,
806 ret_val = phy->ops.write_reg(hw,
811 } else if (phy->smart_speed == e1000_smart_speed_off) {
812 ret_val = phy->ops.read_reg(hw,
819 ret_val = phy->ops.write_reg(hw,
832 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
846 struct e1000_phy_info *phy = &hw->phy;
867 if (phy->smart_speed == e1000_smart_speed_on)
869 else if (phy->smart_speed == e1000_smart_speed_off)
878 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
893 struct e1000_phy_info *phy = &hw->phy;
908 if (phy->smart_speed == e1000_smart_speed_on)
910 else if (phy->smart_speed == e1000_smart_speed_off)
912 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
913 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
914 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
925 * e1000_acquire_nvm_82575 - Request for access to EEPROM
931 * EEPROM access and return -E1000_ERR_NVM (-1).
947 if (hw->mac.type == e1000_i350) {
958 if (hw->mac.type == e1000_82580) {
977 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
993 * e1000_get_cfg_done_82575 - Read config done bit
996 * Read the management control register for the config done bit for
997 * completion status. NOTE: silicon which is EEPROM-less will fail trying
998 * to read the config done bit, so an error is *ONLY* logged and returns
999 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1004 s32 timeout = PHY_CFG_TIMEOUT;
1009 if (hw->bus.func == E1000_FUNC_1)
1011 else if (hw->bus.func == E1000_FUNC_2)
1013 else if (hw->bus.func == E1000_FUNC_3)
1015 while (timeout) {
1019 timeout--;
1021 if (!timeout)
1026 (hw->phy.type == e1000_phy_igp_3))
1033 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1049 if (hw->phy.media_type != e1000_media_type_copper)
1060 * e1000_check_for_link_82575 - Check for link
1073 if (hw->phy.media_type != e1000_media_type_copper) {
1081 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1084 * Configure Flow Control now that Auto-Neg has completed.
1086 * settings because we may have had to re-autoneg with a
1100 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1107 struct e1000_phy_info *phy = &hw->phy;
1115 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1119 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1139 if (port && (hw->dev_spec._82575.media_port != port)) {
1140 hw->dev_spec._82575.media_port = port;
1141 hw->dev_spec._82575.media_changed = true;
1146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1153 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1162 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1171 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1191 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1196 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1202 struct e1000_mac_info *mac = &hw->mac;
1209 * Read the PCS Status register for link state. For non-copper mode,
1219 mac->serdes_has_link = true;
1236 if (mac->type == e1000_i354) {
1248 mac->serdes_has_link = false;
1257 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1269 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1293 * e1000_reset_hw_82575 - Reset hardware
1306 * Prevent the PCI-E bus from sticking if there is no TLP connection
1311 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1313 /* set the completion timeout for interface */
1316 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1335 * When auto config read does not complete, do not
1339 DEBUGOUT("Auto Read Done did not complete\n");
1357 * e1000_init_hw_82575 - Initialize hardware
1364 struct e1000_mac_info *mac = &hw->mac;
1370 ret_val = mac->ops.id_led_init(hw);
1378 mac->ops.clear_vfta(hw);
1383 hw->dev_spec._82575.mtu = 1500;
1395 * e1000_setup_copper_link_82575 - Configure copper link settings
1398 * Configures the link for auto-neg or forced speed and duplex. Then we check
1416 switch (hw->mac.type) {
1437 ret_val = hw->phy.ops.reset(hw);
1443 switch (hw->phy.type) {
1447 switch (hw->phy.id) {
1473 ret_val = -E1000_ERR_PHY;
1486 * e1000_setup_serdes_link_82575 - Setup link for serdes
1489 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1492 * for auto-negotiation or forces speed/duplex.
1503 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1524 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1530 pcs_autoneg = hw->mac.autoneg;
1544 if (hw->mac.type == e1000_82575 ||
1545 hw->mac.type == e1000_82576) {
1546 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1557 * non-SGMII modes only supports a speed of 1000/Full for the
1592 switch (hw->fc.requested_mode) {
1627 * e1000_get_media_type_82575 - derives current media type.
1632 * - link mode set in the current port Init Control Word #3
1633 * - current link mode settings in CSR register
1634 * - MDIO vs. I2C PHY control interface chosen
1635 * - SFP module media type
1639 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1645 dev_spec->sgmii_active = false;
1646 dev_spec->module_plugged = false;
1656 hw->phy.media_type = e1000_media_type_internal_serdes;
1659 hw->phy.media_type = e1000_media_type_copper;
1664 hw->phy.media_type = e1000_media_type_copper;
1665 dev_spec->sgmii_active = true;
1674 (hw->phy.media_type == e1000_media_type_unknown)) {
1679 hw->phy.media_type = e1000_media_type_internal_serdes;
1682 hw->phy.media_type = e1000_media_type_copper;
1683 dev_spec->sgmii_active = true;
1692 if (dev_spec->sgmii_active)
1709 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1719 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1720 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1722 s32 timeout = 3;
1732 while (timeout) {
1739 timeout--;
1753 dev_spec->module_plugged = true;
1757 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1758 hw->phy.media_type = e1000_media_type_internal_serdes;
1760 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
1761 dev_spec->sgmii_active = true;
1762 hw->phy.media_type = e1000_media_type_internal_serdes;
1764 } else if (eth_flags->e1000_base_t) {
1765 dev_spec->sgmii_active = true;
1766 hw->phy.media_type = e1000_media_type_copper;
1769 hw->phy.media_type = e1000_media_type_unknown;
1781 * e1000_valid_led_default_82575 - Verify a valid default LED config
1794 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1801 switch (hw->phy.media_type) {
1816 * e1000_sgmii_active_82575 - Return sgmii state
1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1826 return dev_spec->sgmii_active;
1830 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1840 if (hw->mac.type == e1000_82575) {
1868 * e1000_read_mac_addr_82575 - Read device MAC address
1893 * e1000_config_collision_dist_82575 - Configure collision distance
1915 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1974 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1980 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1983 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1984 * however the hardware default for these parts is 500us to 1ms which is less
1985 * than the 10ms recommended by the pci-e spec. To address this we need to
1986 * increase the value to either 10ms to 200ms for capability version 1 config,
1995 /* only take action if timeout value is defaulted to 0 */
2001 * timeout of 10ms to 200ms through the GCR register
2009 * for version 2 capabilities we need to write the config space
2010 * directly in order to set the completion timeout value for
2023 /* disable completion timeout resend */
2031 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2034 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2036 * enables/disables L2 switch anti-spoofing functionality.
2042 switch (hw->mac.type) {
2058 /* The PF can spoof - it has to in order to
2070 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2080 switch (hw->mac.type) {
2107 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2126 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2140 ret_val = hw->phy.ops.acquire(hw);
2146 hw->phy.ops.release(hw);
2153 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2166 ret_val = hw->phy.ops.acquire(hw);
2172 hw->phy.ops.release(hw);
2179 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2194 if (hw->mac.type != e1000_82580)
2199 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2200 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2218 * e1000_reset_hw_82580 - Reset hardware
2230 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2234 hw->dev_spec._82575.global_device_reset = false;
2237 if (hw->mac.type == e1000_82580)
2244 * Prevent the PCI-E bus from sticking if there is no TLP connection
2249 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2260 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2272 switch (hw->device_id) {
2280 /* Add delay to insure DEV_RST or RST has time to complete */
2286 * When auto config read does not complete, do not
2290 DEBUGOUT("Auto Read Done did not complete\n");
2309 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2315 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2335 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2352 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2362 ret_val = -E1000_ERR_NVM;
2371 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2389 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2396 checksum = (u16) NVM_SUM - checksum;
2397 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2407 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2423 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2448 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2463 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2472 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2492 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2520 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2547 * __e1000_access_emi_reg - Read/write EMI register
2560 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2565 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2567 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2573 * e1000_read_emi_reg - Read Extended Management Interface register
2586 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2593 struct e1000_phy_info *phy = &hw->phy;
2599 if (phy->id != M88E1512_E_PHY_ID)
2603 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2607 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2611 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2615 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2619 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2623 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2627 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2631 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2635 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2640 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2644 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2649 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2653 /* Change mode to SGMII-to-Copper */
2654 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2659 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2663 ret_val = phy->ops.commit(hw);
2675 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2682 struct e1000_phy_info *phy = &hw->phy;
2688 if (phy->id != M88E1543_E_PHY_ID)
2692 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2696 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2700 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2704 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2708 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2716 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2720 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2724 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2729 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2733 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2738 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2742 /* Change mode to SGMII-to-Copper */
2743 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2748 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2752 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2753 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2758 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2762 ret_val = phy->ops.commit(hw);
2774 * e1000_set_eee_i350 - Enable/disable EEE support
2788 if ((hw->mac.type < e1000_i350) ||
2789 (hw->phy.media_type != e1000_media_type_copper))
2795 if (!(hw->dev_spec._82575.eee_disable)) {
2829 * e1000_set_eee_i354 - Enable/disable EEE support
2839 struct e1000_phy_info *phy = &hw->phy;
2845 if ((hw->phy.media_type != e1000_media_type_copper) ||
2846 ((phy->id != M88E1543_E_PHY_ID) &&
2847 (phy->id != M88E1512_E_PHY_ID)))
2850 if (!hw->dev_spec._82575.eee_disable) {
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2856 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2862 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2912 * e1000_get_eee_status_i354 - Get EEE status
2921 struct e1000_phy_info *phy = &hw->phy;
2928 if ((hw->phy.media_type != e1000_media_type_copper) ||
2929 ((phy->id != M88E1543_E_PHY_ID) &&
2930 (phy->id != M88E1512_E_PHY_ID)))
2952 * e1000_clear_vfta_i350 - Clear VLAN filter table
2974 * e1000_write_vfta_i350 - Write value to VLAN filter table
2996 * e1000_set_i2c_bb - Enable I2C bit-bang
2999 * Enable I2C bit-bang interface
3025 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3049 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3095 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3100 DEBUGOUT("I2C byte read error - Retrying.\n");
3106 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3114 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3135 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3174 DEBUGOUT("I2C byte write error - Retrying.\n");
3179 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3187 * e1000_i2c_start - Sets I2C start condition
3190 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3202 /* Setup time for start condition (4.7us) */
3207 /* Hold time for start condition (4us) */
3212 /* Minimum low period of clock is 4.7 us */
3218 * e1000_i2c_stop - Sets I2C stop condition
3221 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3233 /* Setup time for stop condition (4us) */
3238 /* bus free time between stop and start (4.7us)*/
3243 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3257 for (i = 7; i >= 0; i--) {
3264 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3279 for (i = 7; i >= 0; i--) {
3298 * e1000_get_i2c_ack - Polls for I2C ACK
3308 u32 timeout = 10;
3315 /* Minimum high period of clock is 4us */
3319 for (i = 0; i < timeout; i++) {
3336 /* Minimum low period of clock is 4.7 us */
3343 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3357 /* Minimum high period of clock is 4us */
3365 /* Minimum low period of clock is 4.7 us */
3370 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3387 /* Minimum high period of clock is 4us */
3392 /* Minimum low period of clock is 4.7 us.
3404 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3408 * Raises the I2C clock line '0'->'1'
3424 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3428 * Lowers the I2C clock line '1'->'0'
3445 * e1000_set_i2c_data - Sets the I2C data bit
3468 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3474 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3481 * e1000_get_i2c_data - Reads the I2C SDA data bit
3501 * e1000_i2c_bus_clear - Clears the I2C bus
3521 /* Min high period of clock is 4us */
3526 /* Min low period of clock is 4.7us*/