Lines Matching +full:x +full:- +full:rc
1 /*-
57 * XXX: Add a TUNABLE and possible per-device sysctl for this?
61 uint16_t intr_type; /* MSI, or MSI-X */
71 {0x4800, "Chelsio T440-dbg VF"},
72 {0x4801, "Chelsio T420-CR VF"},
73 {0x4802, "Chelsio T422-CR VF"},
74 {0x4803, "Chelsio T440-CR VF"},
75 {0x4804, "Chelsio T420-BCH VF"},
76 {0x4805, "Chelsio T440-BCH VF"},
77 {0x4806, "Chelsio T440-CH VF"},
78 {0x4807, "Chelsio T420-SO VF"},
79 {0x4808, "Chelsio T420-CX VF"},
80 {0x4809, "Chelsio T420-BT VF"},
81 {0x480a, "Chelsio T404-BT VF"},
82 {0x480e, "Chelsio T440-LP-CR VF"},
84 {0x5800, "Chelsio T580-dbg VF"},
85 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */
86 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */
87 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */
88 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */
89 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */
90 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */
91 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */
92 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */
93 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */
94 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */
95 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */
96 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */
97 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */
98 {0x5818, "Chelsio T540-BT VF"}, /* 4 x 10GBaseT */
99 {0x5819, "Chelsio T540-LP-BT VF"}, /* 4 x 10GBaseT */
100 {0x581a, "Chelsio T540-SO-BT VF"}, /* 4 x 10GBaseT, nomem */
101 {0x581b, "Chelsio T540-SO-CR VF"}, /* 4 x 10G, nomem */
103 {0x6800, "Chelsio T6-DBG-25 VF"}, /* 2 x 10/25G, debug */
104 {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */
105 {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */
106 {0x6803, "Chelsio T6425-CR VF"}, /* 4 x 10/25G */
107 {0x6804, "Chelsio T6425-SO-CR VF"}, /* 4 x 10/25G, nomem */
108 {0x6805, "Chelsio T6225-SO-OCP3 VF"}, /* 2 x 10/25G, nomem */
109 {0x6806, "Chelsio T6225-OCP3 VF"}, /* 2 x 10/25G */
110 {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */
111 {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */
112 {0x6809, "Chelsio T6210-BT VF"}, /* 2 x 10GBASE-T */
113 {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */
114 {0x6810, "Chelsio T6-DBG-100 VF"}, /* 2 x 40/50/100G, debug */
115 {0x6811, "Chelsio T6225-LL-CR VF"}, /* 2 x 10/25G */
116 {0x6814, "Chelsio T62100-SO-OCP3 VF"}, /* 2 x 40/50/100G, nomem */
117 {0x6815, "Chelsio T6201-BT VF"}, /* 2 x 1000BASE-T */
122 {0x6882, "Chelsio T6225-CR 82 VF"},
123 {0x6883, "Chelsio T62100-CR 83 VF"},
124 {0x6884, "Chelsio T64100-CR 84 VF"},
125 {0x6885, "Chelsio T6240-SO 85 VF"},
126 {0x6886, "Chelsio T6225-SO-CR 86 VF"},
127 {0x6887, "Chelsio T6225-CR 87 VF"},
196 int rc;
202 rc = -t4vf_query_params(sc, nitems(param), param, val);
203 if (rc != 0) {
204 device_printf(sc->dev,
205 "failed to query parameters (pre_init): %d.\n", rc);
206 return (rc);
209 sc->params.fw_vers = val[0];
210 sc->params.tp_vers = val[1];
211 sc->params.vpd.cclk = val[2];
213 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
214 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
215 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
216 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
217 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
219 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
220 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
221 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
222 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
223 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
231 int rc;
234 rc = -t4vf_get_sge_params(sc);
235 if (rc != 0) {
236 device_printf(sc->dev,
237 "unable to retrieve adapter SGE parameters: %d\n", rc);
238 return (rc);
241 rc = -t4vf_get_rss_glb_config(sc);
242 if (rc != 0) {
243 device_printf(sc->dev,
244 "unable to retrieve adapter RSS parameters: %d\n", rc);
245 return (rc);
247 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
248 device_printf(sc->dev,
250 sc->params.rss.mode);
259 rc = -t4vf_get_vfres(sc);
260 if (rc != 0) {
261 device_printf(sc->dev,
262 "unable to get virtual interface resources: %d\n", rc);
263 return (rc);
269 if (sc->params.vfres.pmask == 0) {
270 device_printf(sc->dev, "no port access configured/usable!\n");
273 if (sc->params.vfres.nvi == 0) {
274 device_printf(sc->dev,
278 sc->params.portvec = sc->params.vfres.pmask;
281 rc = -t4vf_query_params(sc, 1, ¶m, &val);
282 if (rc == 0)
283 sc->params.max_pkts_per_eth_tx_pkts_wr = val;
285 sc->params.max_pkts_per_eth_tx_pkts_wr = 14;
287 rc = t4_verify_chip_settings(sc);
288 if (rc != 0)
289 return (rc);
309 sc->params.port_caps32 = 1;
322 int itype, iq_avail, navail, rc;
328 vfres = &sc->params.vfres;
329 nports = sc->params.nports;
337 navail = pci_msix_count(sc->dev);
339 navail = pci_msi_count(sc->dev);
344 iaq->intr_type = itype;
348 * forwarded interrupts when using MSI (but not MSI-X).
359 iaq->nirq = T4VF_EXTRA_INTR;
366 iq_avail = vfres->niqflint - iaq->nirq;
368 device_printf(sc->dev,
370 vfres->niqflint, nports);
380 if (iaq->nirq + nports <= navail) {
381 if (iq_avail > navail - iaq->nirq)
382 iq_avail = navail - iaq->nirq;
398 if (vfres->nethctrl < nports) {
399 device_printf(sc->dev,
401 vfres->nethctrl, nports);
406 if (ntxq > vfres->nethctrl) {
410 ntxq = (vfres->nethctrl / nports) * nports;
412 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
417 if (vfres->neq < nports * 2) {
418 device_printf(sc->dev,
420 vfres->neq, nports);
423 if (nrxq + ntxq > vfres->neq) {
428 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
429 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues"));
435 iaq->nirq += nrxq;
436 iaq->ntxq = ntxq;
437 iaq->nrxq = nrxq;
438 if (iaq->nirq <= navail &&
439 (itype != INTR_MSI || powerof2(iaq->nirq))) {
440 navail = iaq->nirq;
442 rc = pci_alloc_msix(sc->dev, &navail);
444 rc = pci_alloc_msi(sc->dev, &navail);
445 if (rc != 0) {
446 device_printf(sc->dev,
448 itype, rc, iaq->nirq, navail);
449 return (rc);
451 if (navail == iaq->nirq) {
454 pci_release_msi(sc->dev);
458 iaq->nirq = 1;
459 navail = iaq->nirq;
461 rc = pci_alloc_msix(sc->dev, &navail);
463 rc = pci_alloc_msi(sc->dev, &navail);
464 if (rc != 0)
465 device_printf(sc->dev,
467 itype, rc, iaq->nirq, navail);
468 return (rc);
471 device_printf(sc->dev,
473 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
474 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
483 int rc = 0, i, j, rqidx, tqidx, n, p, pmask;
489 sc->dev = dev;
490 sysctl_ctx_init(&sc->ctx);
493 sc->params.pci.mps = pci_get_max_payload(dev);
495 sc->flags |= IS_VF;
496 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
498 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS);
499 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL);
500 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
502 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
505 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
506 TAILQ_INIT(&sc->sfl);
507 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
509 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
511 rc = t4_map_bars_0_and_4(sc);
512 if (rc != 0)
515 rc = -t4vf_prep_adapter(sc);
516 if (rc != 0)
520 if (sc->names == NULL) {
521 rc = ENOTSUP;
531 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
539 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
540 if (rc != 0)
542 rc);
547 rc = ENOTSUP;
553 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux
555 * issue an FLR because of a self- deadlock on the device semaphore.
557 * cases where they're needed -- for instance, some versions of KVM
562 rc = -t4vf_fw_reset(sc);
563 if (rc != 0) {
564 device_printf(dev, "FW reset failed: %d\n", rc);
567 sc->flags |= FW_OK;
577 rc = get_params__pre_init(sc);
578 if (rc != 0)
580 rc = get_params__post_init(sc);
581 if (rc != 0)
584 rc = set_params__post_init(sc);
585 if (rc != 0)
588 rc = t4_map_bar_2(sc);
589 if (rc != 0)
592 rc = t4_adj_doorbells(sc);
593 if (rc != 0)
596 rc = t4_create_dma_tag(sc);
597 if (rc != 0)
604 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS);
611 sc->params.nports = imin(sc->params.nports,
612 bitcount32(sc->params.vfres.pmask));
622 * First pass over all the ports - allocate VIs and initialize some
625 pmask = sc->params.vfres.pmask;
631 sc->port[i] = pi;
634 pi->adapter = sc;
635 pi->port_id = i;
636 pi->nvi = 1;
637 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE,
644 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
645 if (rc != 0) {
647 i, rc);
648 free(pi->vi, M_CXGBE);
650 sc->port[i] = NULL;
656 p = ffs(pmask) - 1;
658 rc = t4vf_get_vf_mac(sc, p, &n, mac);
659 if (rc == 0 && n == 1)
663 sc->vlan_id = t4vf_get_vf_vlan(sc);
667 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
669 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
670 sc->chan_map[pi->tx_chan] = i;
673 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
676 pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, DEVICE_UNIT_ANY);
677 if (pi->dev == NULL) {
680 rc = ENXIO;
683 pi->vi[0].dev = pi->dev;
684 device_set_softc(pi->dev, pi);
690 rc = cfg_itype_and_nqueues(sc, &iaq);
691 if (rc != 0)
694 sc->intr_type = iaq.intr_type;
695 sc->intr_count = iaq.nirq;
697 s = &sc->sge;
698 s->nrxq = sc->params.nports * iaq.nrxq;
699 s->ntxq = sc->params.nports * iaq.ntxq;
700 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
701 s->neq += sc->params.nports; /* ctrl queues: 1 per port */
702 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
704 s->iqmap_sz = s->niq;
705 s->eqmap_sz = s->neq;
707 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
709 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
711 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
713 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
716 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
725 struct port_info *pi = sc->port[i];
732 vi->pi = pi;
733 vi->adapter = sc;
734 vi->qsize_rxq = t4_qsize_rxq;
735 vi->qsize_txq = t4_qsize_txq;
737 vi->first_rxq = rqidx;
738 vi->first_txq = tqidx;
739 vi->tmr_idx = t4_tmr_idx;
740 vi->pktc_idx = t4_pktc_idx;
741 vi->nrxq = j == 0 ? iaq.nrxq: 1;
742 vi->ntxq = j == 0 ? iaq.ntxq: 1;
744 rqidx += vi->nrxq;
745 tqidx += vi->ntxq;
747 vi->rsrv_noflowq = 0;
751 rc = t4_setup_intr_handlers(sc);
752 if (rc != 0) {
754 "failed to setup interrupt handlers: %d\n", rc);
762 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ?
763 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq,
764 sc->sge.niq);
767 if (rc != 0)
772 return (rc);
780 regs->version = chip_id(sc) | (0x3f << 10);
781 t4_get_regs(sc, buf, regs->len);
798 int rc;
799 struct adapter *sc = dev->si_drv1;
801 rc = priv_check(td, PRIV_DRIVER);
802 if (rc != 0)
803 return (rc);
809 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
812 if (edata->size == 4)
813 edata->val = t4_read_reg(sc, edata->addr);
814 else if (edata->size == 8)
815 edata->val = t4_read_reg64(sc, edata->addr);
824 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
827 if (edata->size == 4) {
828 if (edata->val & 0xffffffff00000000)
830 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
831 } else if (edata->size == 8)
832 t4_write_reg64(sc, edata->addr, edata->val);
842 if (regs->len < reglen) {
843 regs->len = reglen; /* hint to the caller */
847 regs->len = reglen;
850 rc = copyout(buf, regs->data, reglen);
860 if (port_id >= sc->params.nports)
862 pi = sc->port[port_id];
865 pi->tx_parse_error = 0;
873 if (vi->flags & VI_INIT_DONE) {
879 rxq->lro.lro_queued = 0;
880 rxq->lro.lro_flushed = 0;
882 rxq->rxcsum = 0;
883 rxq->vlan_extraction = 0;
887 txq->txcsum = 0;
888 txq->tso_wrs = 0;
889 txq->vlan_insertion = 0;
890 txq->imm_wrs = 0;
891 txq->sgl_wrs = 0;
892 txq->txpkt_wrs = 0;
893 txq->txpkts0_wrs = 0;
894 txq->txpkts1_wrs = 0;
895 txq->txpkts0_pkts = 0;
896 txq->txpkts1_pkts = 0;
897 txq->txpkts_flush = 0;
898 mp_ring_reset_stats(txq->r);
905 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
908 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
911 rc = ENOTTY;
914 return (rc);