Lines Matching +full:pn +full:- +full:retry +full:- +full:params
2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
38 * t3_wait_op_done_val - wait until an operation is completed
41 * @mask: a single-bit field within @reg that indicates completion
50 * operation completes and -EAGAIN otherwise.
63 if (--attempts == 0) in t3_wait_op_done_val()
64 return -EAGAIN; in t3_wait_op_done_val()
71 * t3_write_regs - write a bunch of registers
84 while (n--) { in t3_write_regs()
85 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
91 * t3_set_reg_field - set a register field to a value
109 * t3_read_indirect - read indirectly addressed registers
124 while (nregs--) { in t3_read_indirect()
132 * t3_mc7_bd_read - read from MC7 through backdoor accesses
134 * @start: index of first 64-bit word to read
135 * @n: number of 64-bit words to read
138 * Read n 64-bit words from MC7 starting at word start, using backdoor
147 unsigned int size64 = mc7->size / 8; /* # of 64-bit words */ in t3_mc7_bd_read()
148 adapter_t *adap = mc7->adapter; in t3_mc7_bd_read()
151 return -EINVAL; in t3_mc7_bd_read()
153 start *= (8 << mc7->width); in t3_mc7_bd_read()
154 while (n--) { in t3_mc7_bd_read()
158 for (i = (1 << mc7->width) - 1; i >= 0; --i) { in t3_mc7_bd_read()
162 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, in t3_mc7_bd_read()
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); in t3_mc7_bd_read()
165 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
166 while ((val & F_BUSY) && attempts--) in t3_mc7_bd_read()
168 mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
170 return -EIO; in t3_mc7_bd_read()
172 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); in t3_mc7_bd_read()
173 if (mc7->width == 0) { in t3_mc7_bd_read()
175 mc7->offset + A_MC7_BD_DATA0); in t3_mc7_bd_read()
178 if (mc7->width > 1) in t3_mc7_bd_read()
179 val >>= shift[mc7->width]; in t3_mc7_bd_read()
180 val64 |= (u64)val << (step[mc7->width] * i); in t3_mc7_bd_read()
190 * Low-level I2C read and write routines. These simply read and write a
192 * is to be chained. Generally most code will use higher-level routines to
198 * Read an 8-bit value from the I2C bus. If the "chained" parameter is
199 * non-zero then a STOP bit will not be written after the read command. On
201 * -EAGAIN, etc.). On success, the 8-bit value read from the I2C bus is
223 * Write an 8-bit value to the I2C bus. If the "chained" parameter is
224 * non-zero, then a STOP bit will not be written after the write command. On
226 * -EAGAIN, etc.). On success, the value of the I2C ACK bit is returned as a
250 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; in mi1_init()
268 return -EINVAL; in t3_mi1_read()
288 return -EINVAL; in t3_mi1_write()
359 * t3_mdio_change_bits - modify the value of a PHY register
384 * t3_phy_reset - reset a PHY block
409 } while (ctl && --wait); in t3_phy_reset()
411 return ctl ? -1 : 0; in t3_phy_reset()
415 * t3_phy_advertise - set the PHY advertisement registers for autoneg
458 * t3_phy_advertise_fiber - set fiber PHY advertisement register
481 * t3_set_phy_speed_duplex - force PHY speed and duplex
487 * auto-negotiation except for GigE, where auto-negotiation is mandatory.
510 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */ in t3_set_phy_speed_duplex()
577 &mi1_mdio_ext_ops, "Chelsio N320E-G2" },
581 * Return the adapter_info structure with a given index. Out-of-range indices
613 * VPD-R sections.
621 VPD_ENTRY(pn, 16); /* part number */
637 u32 pad; /* for multiple-of-4 sizing and alignment */
645 * t3_seeprom_read - read a VPD EEPROM location
650 * Read a 32-bit word from a location in VPD EEPROM using the card's PCI
659 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_read()
662 return -EINVAL; in t3_seeprom_read()
668 } while (!(val & PCI_VPD_ADDR_F) && --attempts); in t3_seeprom_read()
672 return -EIO; in t3_seeprom_read()
680 * t3_seeprom_write - write a VPD EEPROM location
685 * Write a 32-bit word to a location in VPD EEPROM using the card's PCI
692 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_write()
695 return -EINVAL; in t3_seeprom_write()
704 } while ((val & PCI_VPD_ADDR_F) && --attempts); in t3_seeprom_write()
708 return -EIO; in t3_seeprom_write()
714 * t3_seeprom_wp - enable/disable EEPROM write protection
730 return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10; in hex2int()
734 * get_desc_len - get the length of a vpd descriptor.
772 * is_end_tag - Check if a vpd tag is the end tag.
798 * t3_get_vpd_len - computes the length of a vpd structure
802 * Computes the lentgh of the vpd structure starting at vpd->offset.
810 offset = vpd->offset; in t3_get_vpd_len()
812 while (offset < (vpd->offset + MAX_VPD_BYTES)) { in t3_get_vpd_len()
829 * t3_read_vpd - reads the stream of bytes containing a vpd structure
833 * Reads the vpd structure starting at vpd->offset into vpd->data,
834 * the length of the byte stream to read is vpd->len.
841 for (i = 0; i < vpd->len; i += 4) { in t3_read_vpd()
842 ret = t3_seeprom_read(adapter, vpd->offset + i, in t3_read_vpd()
843 (u32 *) &(vpd->data[i])); in t3_read_vpd()
853 * get_vpd_params - read VPD parameters from VPD EEPROM
880 p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10); in get_vpd_params()
881 p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10); in get_vpd_params()
882 p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10); in get_vpd_params()
883 p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10); in get_vpd_params()
884 p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10); in get_vpd_params()
885 memcpy(p->sn, vpd.sn_data, SERNUM_LEN); in get_vpd_params()
886 memcpy(p->ec, vpd.ec_data, ECNUM_LEN); in get_vpd_params()
889 if (adapter->params.rev == 0 && !vpd.port0_data[0]) { in get_vpd_params()
890 p->port_type[0] = uses_xaui(adapter) ? 1 : 2; in get_vpd_params()
891 p->port_type[1] = uses_xaui(adapter) ? 6 : 2; in get_vpd_params()
893 p->port_type[0] = (u8)hex2int(vpd.port0_data[0]); in get_vpd_params()
894 p->port_type[1] = (u8)hex2int(vpd.port1_data[0]); in get_vpd_params()
895 p->port_type[2] = (u8)hex2int(vpd.port2_data[0]); in get_vpd_params()
896 p->port_type[3] = (u8)hex2int(vpd.port3_data[0]); in get_vpd_params()
897 p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16); in get_vpd_params()
898 p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16); in get_vpd_params()
902 p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 + in get_vpd_params()
934 FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR,
935 FW_MAX_SIZE_PRE8 = FW_VERS_ADDR_PRE8 - FW_FLASH_BOOT_ADDR,
945 * sf1_read - read data from the serial flash
961 return -EINVAL; in sf1_read()
963 return -EBUSY; in sf1_read()
964 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
972 * sf1_write - write data to the serial flash
986 return -EINVAL; in sf1_write()
988 return -EBUSY; in sf1_write()
991 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); in sf1_write()
996 * flash_wait_op - wait for a flash operation to complete
1014 if (--attempts == 0) in flash_wait_op()
1015 return -EAGAIN; in flash_wait_op()
1022 * t3_read_flash - read words from serial flash
1025 * @nwords: how many 32-bit words to read
1029 * Read the specified number of 32-bit words from the serial flash.
1031 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1040 return -EINVAL; in t3_read_flash()
1048 for ( ; nwords; nwords--, data++) { in t3_read_flash()
1059 * t3_write_flash - write up to a page of data to the serial flash
1068 * If @byte_oriented is set the write data is stored as a 32-bit
1069 * big-endian array, otherwise in the processor's native endianness.
1081 return -EINVAL; in t3_write_flash()
1089 for (left = n; left; left -= c) { in t3_write_flash()
1109 if (memcmp(data - n, (u8 *)buf + offset, n)) in t3_write_flash()
1110 return -EIO; in t3_write_flash()
1115 * t3_get_tp_version - read the tp sram version
1138 * t3_check_tpsram_version - read the tp sram version
1148 if (adapter->params.rev == T3_REV_A) in t3_check_tpsram_version()
1168 return -EINVAL; in t3_check_tpsram_version()
1172 * t3_check_tpsram - check if provided protocol SRAM
1193 return -EINVAL; in t3_check_tpsram()
1205 * t3_get_fw_version - read the firmware version
1223 * t3_check_fw_version - check if the FW is compatible with this driver
1257 return -EINVAL; in t3_check_fw_version()
1261 * t3_flash_erase_sectors - erase a range of flash sectors
1284 * t3_load_fw - download firmware
1290 * The FW image has the following sections: @size - 8 bytes of code and
1291 * data, followed by 4 bytes of FW version, followed by the 32-bit
1302 return -EINVAL; in t3_load_fw()
1303 if (size - 8 > FW_MAX_SIZE) in t3_load_fw()
1304 return -EFBIG; in t3_load_fw()
1306 version = ntohl(*(const u32 *)(fw_data + size - 8)); in t3_load_fw()
1311 if (size - 8 > FW_MAX_SIZE_PRE8) in t3_load_fw()
1312 return -EFBIG; in t3_load_fw()
1321 return -EINVAL; in t3_load_fw()
1328 size -= 8; /* trim off version and checksum */ in t3_load_fw()
1338 size -= chunk_size; in t3_load_fw()
1349 * t3_load_boot - download boot flash
1355 * The boot image has the following sections: a 28-byte header and the
1364 unsigned int boot_end = (BOOT_FLASH_BOOT_ADDR + size - 1) >> 16; in t3_load_boot()
1373 return -EFBIG; in t3_load_boot()
1375 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE) { in t3_load_boot()
1377 return -EINVAL; in t3_load_boot()
1379 if (header->length * BOOT_SIZE_INC != size) { in t3_load_boot()
1381 return -EINVAL; in t3_load_boot()
1397 size -= chunk_size; in t3_load_boot()
1409 * t3_cim_ctl_blk_read - read a block from CIM control region
1415 * Reads a block of 4-byte words from the CIM control region.
1423 return -EBUSY; in t3_cim_ctl_blk_read()
1425 for ( ; !ret && n--; addr += 4) { in t3_cim_ctl_blk_read()
1442 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG + mac->offset); in t3_gate_rx_traffic()
1443 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, in t3_gate_rx_traffic()
1447 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH + in t3_gate_rx_traffic()
1448 mac->offset); in t3_gate_rx_traffic()
1449 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, 0); in t3_gate_rx_traffic()
1451 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW + in t3_gate_rx_traffic()
1452 mac->offset); in t3_gate_rx_traffic()
1453 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, 0); in t3_gate_rx_traffic()
1463 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, in t3_open_rx_traffic()
1466 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, in t3_open_rx_traffic()
1468 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, in t3_open_rx_traffic()
1475 struct cmac *mac = &pi->mac; in t3_detect_link_fault()
1481 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_detect_link_fault()
1484 (void) t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_detect_link_fault()
1488 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, F_RXEN); in t3_detect_link_fault()
1491 link_fault = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_detect_link_fault()
1498 struct cmac *mac = &pi->mac; in t3_clear_faults()
1500 if (adapter->params.nports <= 2) { in t3_clear_faults()
1501 t3_xgm_intr_disable(adapter, pi->port_id); in t3_clear_faults()
1502 t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_clear_faults()
1503 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, F_XGM_INT); in t3_clear_faults()
1504 t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset, in t3_clear_faults()
1506 t3_xgm_intr_enable(adapter, pi->port_id); in t3_clear_faults()
1511 * t3_link_changed - handle interface link changes
1517 * invokes an OS-specific handler.
1523 struct cphy *phy = &pi->phy; in t3_link_changed()
1524 struct cmac *mac = &pi->mac; in t3_link_changed()
1525 struct link_config *lc = &pi->link_config; in t3_link_changed()
1527 link_ok = lc->link_ok; in t3_link_changed()
1528 speed = lc->speed; in t3_link_changed()
1529 duplex = lc->duplex; in t3_link_changed()
1530 fc = lc->fc; in t3_link_changed()
1533 phy->ops->get_link_status(phy, &link_state, &speed, &duplex, &fc); in t3_link_changed()
1536 phy->rst = 0; in t3_link_changed()
1537 else if (++phy->rst == 3) { in t3_link_changed()
1538 phy->ops->reset(phy, 0); in t3_link_changed()
1539 phy->rst = 0; in t3_link_changed()
1543 pi->link_fault = LF_NO; in t3_link_changed()
1545 if (lc->requested_fc & PAUSE_AUTONEG) in t3_link_changed()
1546 fc &= lc->requested_fc; in t3_link_changed()
1548 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); in t3_link_changed()
1551 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE && in t3_link_changed()
1552 (speed != lc->speed || duplex != lc->duplex || fc != lc->fc)) in t3_link_changed()
1558 * b) PHY link transitioned from down -> up in t3_link_changed()
1560 if (adapter->params.nports <= 2 && in t3_link_changed()
1561 ((pi->link_fault && link_ok) || (!lc->link_ok && link_ok))) { in t3_link_changed()
1565 if (pi->link_fault != LF_YES) { in t3_link_changed()
1566 mac->stats.link_faults++; in t3_link_changed()
1567 pi->link_fault = LF_YES; in t3_link_changed()
1571 if (adapter->params.rev >= T3_REV_C) in t3_link_changed()
1581 if (pi->link_fault == LF_MAYBE && in t3_link_changed()
1582 link_ok && lc->link_ok) in t3_link_changed()
1585 pi->link_fault = LF_NO; in t3_link_changed()
1589 if (link_ok == lc->link_ok && speed == lc->speed && in t3_link_changed()
1590 duplex == lc->duplex && fc == lc->fc) in t3_link_changed()
1593 lc->link_ok = (unsigned char)link_ok; in t3_link_changed()
1594 lc->speed = speed < 0 ? SPEED_INVALID : speed; in t3_link_changed()
1595 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; in t3_link_changed()
1596 lc->fc = fc; in t3_link_changed()
1600 /* down -> up, or up -> up with changed settings */ in t3_link_changed()
1602 if (adapter->params.rev > 0 && uses_xaui(adapter)) { in t3_link_changed()
1604 if (adapter->params.rev >= T3_REV_C) in t3_link_changed()
1609 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_changed()
1614 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset, in t3_link_changed()
1618 t3_set_reg_field(adapter, A_XGM_STAT_CTRL + mac->offset, in t3_link_changed()
1624 /* up -> down */ in t3_link_changed()
1626 if (adapter->params.rev > 0 && uses_xaui(adapter)) { in t3_link_changed()
1628 A_XGM_XAUI_ACT_CTRL + mac->offset, 0); in t3_link_changed()
1631 t3_xgm_intr_disable(adapter, pi->port_id); in t3_link_changed()
1632 if (adapter->params.nports <= 2) { in t3_link_changed()
1634 A_XGM_INT_ENABLE + mac->offset, in t3_link_changed()
1644 A_XGM_TXFIFO_CFG + mac->offset, 0, F_ENDROPPKT); in t3_link_changed()
1645 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_changed()
1647 A_XGM_TX_CTRL + mac->offset, F_TXEN); in t3_link_changed()
1649 A_XGM_RX_CTRL + mac->offset, F_RXEN); in t3_link_changed()
1654 mac->was_reset); in t3_link_changed()
1655 mac->was_reset = 0; in t3_link_changed()
1659 * t3_link_start - apply link configuration to MAC/PHY
1665 * - If the PHY can auto-negotiate first decide what to advertise, then
1666 * enable/disable auto-negotiation as desired, and reset.
1667 * - If the PHY does not auto-negotiate just reset it.
1668 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1669 * otherwise do it later based on the outcome of auto-negotiation.
1673 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); in t3_link_start()
1675 lc->link_ok = 0; in t3_link_start()
1676 if (lc->supported & SUPPORTED_Autoneg) { in t3_link_start()
1677 lc->advertising &= ~(ADVERTISED_Asym_Pause | ADVERTISED_Pause); in t3_link_start()
1679 lc->advertising |= ADVERTISED_Asym_Pause; in t3_link_start()
1681 lc->advertising |= ADVERTISED_Pause; in t3_link_start()
1684 phy->ops->advertise(phy, lc->advertising); in t3_link_start()
1686 if (lc->autoneg == AUTONEG_DISABLE) { in t3_link_start()
1687 lc->speed = lc->requested_speed; in t3_link_start()
1688 lc->duplex = lc->requested_duplex; in t3_link_start()
1689 lc->fc = (unsigned char)fc; in t3_link_start()
1690 t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex, in t3_link_start()
1693 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); in t3_link_start()
1695 if (!is_10G(phy->adapter)) in t3_link_start()
1696 phy->ops->power_down(phy, 0); in t3_link_start()
1698 phy->ops->autoneg_enable(phy); in t3_link_start()
1700 t3_mac_set_speed_duplex_fc(mac, -1, -1, fc); in t3_link_start()
1701 lc->fc = (unsigned char)fc; in t3_link_start()
1702 phy->ops->reset(phy, 0); in t3_link_start()
1708 * t3_set_vlan_accel - control HW VLAN extraction
1725 short stat_idx; /* stat counter to increment or -1 */
1730 * t3_handle_intr_status - table driven interrupt handler
1752 for ( ; acts->mask; ++acts) { in t3_handle_intr_status()
1753 if (!(status & acts->mask)) continue; in t3_handle_intr_status()
1754 if (acts->fatal) { in t3_handle_intr_status()
1757 acts->msg, status & acts->mask); in t3_handle_intr_status()
1758 status &= ~acts->mask; in t3_handle_intr_status()
1759 } else if (acts->msg) in t3_handle_intr_status()
1761 acts->msg, status & acts->mask); in t3_handle_intr_status()
1762 if (acts->stat_idx >= 0) in t3_handle_intr_status()
1763 stats[acts->stat_idx]++; in t3_handle_intr_status()
1831 { F_MSTDETPARERR, "PCI master detected parity error", -1, 1 }, in pci_intr_handler()
1832 { F_SIGTARABT, "PCI signaled target abort", -1, 1 }, in pci_intr_handler()
1833 { F_RCVTARABT, "PCI received target abort", -1, 1 }, in pci_intr_handler()
1834 { F_RCVMSTABT, "PCI received master abort", -1, 1 }, in pci_intr_handler()
1835 { F_SIGSYSERR, "PCI signaled system error", -1, 1 }, in pci_intr_handler()
1836 { F_DETPARERR, "PCI detected parity error", -1, 1 }, in pci_intr_handler()
1837 { F_SPLCMPDIS, "PCI split completion discarded", -1, 1 }, in pci_intr_handler()
1838 { F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1 }, in pci_intr_handler()
1839 { F_RCVSPLCMPERR, "PCI received split completion error", -1, in pci_intr_handler()
1843 { F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1 }, in pci_intr_handler()
1844 { F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, in pci_intr_handler()
1845 { V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1, in pci_intr_handler()
1847 { V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1, in pci_intr_handler()
1849 { V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1, in pci_intr_handler()
1851 { V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity " in pci_intr_handler()
1852 "error", -1, 1 }, in pci_intr_handler()
1857 pcix1_intr_info, adapter->irq_stats)) in pci_intr_handler()
1867 { F_PEXERR, "PCI PEX error", -1, 1 }, in pcie_intr_handler()
1869 "PCI unexpected split completion DMA read error", -1, 1 }, in pcie_intr_handler()
1871 "PCI unexpected split completion DMA command error", -1, 1 }, in pcie_intr_handler()
1872 { F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, in pcie_intr_handler()
1873 { F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1 }, in pcie_intr_handler()
1874 { F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1 }, in pcie_intr_handler()
1875 { F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1 }, in pcie_intr_handler()
1877 "PCI MSI-X table/PBA parity error", -1, 1 }, in pcie_intr_handler()
1878 { F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1 }, in pcie_intr_handler()
1879 { F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1 }, in pcie_intr_handler()
1880 { F_RXPARERR, "PCI Rx parity error", -1, 1 }, in pcie_intr_handler()
1881 { F_TXPARERR, "PCI Tx parity error", -1, 1 }, in pcie_intr_handler()
1882 { V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1 }, in pcie_intr_handler()
1891 pcie_intr_info, adapter->irq_stats)) in pcie_intr_handler()
1901 { 0xffffff, "TP parity error", -1, 1 }, in tp_intr_handler()
1902 { 0x1000000, "TP out of Rx pages", -1, 1 }, in tp_intr_handler()
1903 { 0x2000000, "TP out of Tx pages", -1, 1 }, in tp_intr_handler()
1907 { 0x1fffffff, "TP parity error", -1, 1 }, in tp_intr_handler()
1908 { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 }, in tp_intr_handler()
1909 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, in tp_intr_handler()
1914 adapter->params.rev < T3_REV_C ? in tp_intr_handler()
1925 { F_RSVDSPACEINT, "CIM reserved space write", -1, 1 }, in cim_intr_handler()
1926 { F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1 }, in cim_intr_handler()
1927 { F_FLASHRANGEINT, "CIM flash address out of range", -1, 1 }, in cim_intr_handler()
1928 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, in cim_intr_handler()
1929 { F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1 }, in cim_intr_handler()
1930 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, in cim_intr_handler()
1931 { F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1 }, in cim_intr_handler()
1932 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, in cim_intr_handler()
1933 { F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1 }, in cim_intr_handler()
1934 { F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1 }, in cim_intr_handler()
1935 { F_BLKRDPLINT, "CIM block read from PL space", -1, 1 }, in cim_intr_handler()
1936 { F_BLKWRPLINT, "CIM block write to PL space", -1, 1 }, in cim_intr_handler()
1937 { F_DRAMPARERR, "CIM DRAM parity error", -1, 1 }, in cim_intr_handler()
1938 { F_ICACHEPARERR, "CIM icache parity error", -1, 1 }, in cim_intr_handler()
1939 { F_DCACHEPARERR, "CIM dcache parity error", -1, 1 }, in cim_intr_handler()
1940 { F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1 }, in cim_intr_handler()
1941 { F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1 }, in cim_intr_handler()
1942 { F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1 }, in cim_intr_handler()
1943 { F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1 }, in cim_intr_handler()
1944 { F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1 }, in cim_intr_handler()
1945 { F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1 }, in cim_intr_handler()
1946 { F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1 }, in cim_intr_handler()
1947 { F_ITAGPARERR, "CIM itag parity error", -1, 1 }, in cim_intr_handler()
1948 { F_DTAGPARERR, "CIM dtag parity error", -1, 1 }, in cim_intr_handler()
1963 { F_PARERRDATA, "ULP RX data parity error", -1, 1 }, in ulprx_intr_handler()
1964 { F_PARERRPCMD, "ULP RX command parity error", -1, 1 }, in ulprx_intr_handler()
1965 { F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1 }, in ulprx_intr_handler()
1966 { F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1 }, in ulprx_intr_handler()
1967 { F_ARBFPERR, "ULP RX ArbF parity error", -1, 1 }, in ulprx_intr_handler()
1968 { F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1 }, in ulprx_intr_handler()
1969 { F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1 }, in ulprx_intr_handler()
1970 { F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1 }, in ulprx_intr_handler()
1989 { 0xfc, "ULP TX parity error", -1, 1 }, in ulptx_intr_handler()
1994 ulptx_intr_info, adapter->irq_stats)) in ulptx_intr_handler()
2013 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, in pmtx_intr_handler()
2014 { ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1 }, in pmtx_intr_handler()
2015 { OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1 }, in pmtx_intr_handler()
2017 "PMTX ispi parity error", -1, 1 }, in pmtx_intr_handler()
2019 "PMTX ospi parity error", -1, 1 }, in pmtx_intr_handler()
2043 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, in pmrx_intr_handler()
2044 { IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1 }, in pmrx_intr_handler()
2045 { OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1 }, in pmrx_intr_handler()
2047 "PMRX ispi parity error", -1, 1 }, in pmrx_intr_handler()
2049 "PMRX ospi parity error", -1, 1 }, in pmrx_intr_handler()
2064 { F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1 }, in cplsw_intr_handler()
2065 { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, in cplsw_intr_handler()
2066 { F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1 }, in cplsw_intr_handler()
2067 { F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1 }, in cplsw_intr_handler()
2068 { F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1 }, in cplsw_intr_handler()
2069 { F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1 }, in cplsw_intr_handler()
2084 { 0x1ff, "MPS parity error", -1, 1 }, in mps_intr_handler()
2100 adapter_t *adapter = mc7->adapter; in mc7_intr_handler()
2101 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); in mc7_intr_handler()
2104 mc7->stats.corr_err++; in mc7_intr_handler()
2106 "data 0x%x 0x%x 0x%x\n", mc7->name, in mc7_intr_handler()
2107 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), in mc7_intr_handler()
2108 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), in mc7_intr_handler()
2109 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), in mc7_intr_handler()
2110 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); in mc7_intr_handler()
2114 mc7->stats.uncorr_err++; in mc7_intr_handler()
2116 "data 0x%x 0x%x 0x%x\n", mc7->name, in mc7_intr_handler()
2117 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), in mc7_intr_handler()
2118 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), in mc7_intr_handler()
2119 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), in mc7_intr_handler()
2120 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); in mc7_intr_handler()
2124 mc7->stats.parity_err++; in mc7_intr_handler()
2126 mc7->name, G_PE(cause)); in mc7_intr_handler()
2132 if (adapter->params.rev > 0) in mc7_intr_handler()
2134 mc7->offset + A_MC7_ERR_ADDR); in mc7_intr_handler()
2135 mc7->stats.addr_err++; in mc7_intr_handler()
2137 mc7->name, addr); in mc7_intr_handler()
2143 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
2157 idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */ in mac_intr_handler()
2159 mac = &pi->mac; in mac_intr_handler()
2167 cause = (t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) in mac_intr_handler()
2171 mac->stats.tx_fifo_parity_err++; in mac_intr_handler()
2175 mac->stats.rx_fifo_parity_err++; in mac_intr_handler()
2179 mac->stats.tx_fifo_urun++; in mac_intr_handler()
2181 mac->stats.rx_fifo_ovfl++; in mac_intr_handler()
2183 mac->stats.serdes_signal_loss++; in mac_intr_handler()
2185 mac->stats.xaui_pcs_ctc_err++; in mac_intr_handler()
2187 mac->stats.xaui_pcs_align_change++; in mac_intr_handler()
2189 t3_read_reg(adap, A_XGM_INT_ENABLE + mac->offset)) { in mac_intr_handler()
2190 t3_set_reg_field(adap, A_XGM_INT_ENABLE + mac->offset, in mac_intr_handler()
2194 pi->link_fault = LF_MAYBE; in mac_intr_handler()
2201 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause); in mac_intr_handler()
2215 if (!(p->phy.caps & SUPPORTED_IRQ)) in phy_intr_handler()
2218 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { in phy_intr_handler()
2219 int phy_cause = p->phy.ops->intr_handler(&p->phy); in phy_intr_handler()
2224 p->phy.fifo_errors++; in phy_intr_handler()
2239 * t3_slow_intr_handler - control path interrupt handler
2242 * T3 interrupt handler for non-data interrupt events, e.g., errors.
2250 cause &= adapter->slow_intr_mask; in t3_slow_intr_handler()
2262 mc7_intr_handler(&adapter->pmrx); in t3_slow_intr_handler()
2264 mc7_intr_handler(&adapter->pmtx); in t3_slow_intr_handler()
2266 mc7_intr_handler(&adapter->cm); in t3_slow_intr_handler()
2284 t3_mc5_intr_handler(&adapter->mc5); in t3_slow_intr_handler()
2303 if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) && in calc_gpio_intr()
2304 adapter_info(adap)->gpio_intr[i]) in calc_gpio_intr()
2305 gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i]; in calc_gpio_intr()
2310 * t3_intr_enable - enable interrupts
2314 * various HW modules and then enabling the top-level interrupt
2321 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, in t3_intr_enable()
2323 { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, in t3_intr_enable()
2333 adapter->slow_intr_mask = PL_INTR_MASK; in t3_intr_enable()
2337 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); in t3_intr_enable()
2340 if (adapter->params.rev > 0) { in t3_intr_enable()
2357 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); in t3_intr_enable()
2362 * t3_intr_disable - disable a card's interrupts
2365 * Disable interrupts. We only disable the top-level interrupt
2372 adapter->slow_intr_mask = 0; in t3_intr_disable()
2376 * t3_intr_clear - clear all interrupts
2388 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, in t3_intr_clear()
2389 A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, in t3_intr_clear()
2420 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, in t3_xgm_intr_enable()
2428 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, in t3_xgm_intr_disable()
2433 * t3_port_intr_enable - enable port-specific interrupts
2437 * Enable port-specific (i.e., MAC and PHY) interrupts for the given
2444 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK); in t3_port_intr_enable()
2445 pi->phy.ops->intr_enable(&pi->phy); in t3_port_intr_enable()
2449 * t3_port_intr_disable - disable port-specific interrupts
2453 * Disable port-specific (i.e., MAC and PHY) interrupts for the given
2460 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0); in t3_port_intr_disable()
2461 pi->phy.ops->intr_disable(&pi->phy); in t3_port_intr_disable()
2465 * t3_port_intr_clear - clear port-specific interrupts
2469 * Clear port-specific (i.e., MAC and PHY) interrupts for the given
2476 t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff); in t3_port_intr_clear()
2477 pi->phy.ops->intr_clear(&pi->phy); in t3_port_intr_clear()
2483 * t3_sge_write_context - write an SGE context
2518 * clear_sge_ctxt - completely clear an SGE context
2523 * Completely clear an SGE context. Used predominantly at post-reset
2545 * t3_sge_init_ecntxt - initialize an SGE egress context
2569 return -EINVAL; in t3_sge_init_ecntxt()
2571 return -EBUSY; in t3_sge_init_ecntxt()
2589 * t3_sge_init_flcntxt - initialize an SGE free-buffer list context
2609 return -EINVAL; in t3_sge_init_flcntxt()
2611 return -EBUSY; in t3_sge_init_flcntxt()
2623 V_FL_ENTRY_SIZE_HI(bsize >> (32 - S_FL_ENTRY_SIZE_LO)) | in t3_sge_init_flcntxt()
2629 * t3_sge_init_rspcntxt - initialize an SGE response queue context
2632 * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ
2650 return -EINVAL; in t3_sge_init_rspcntxt()
2652 return -EBUSY; in t3_sge_init_rspcntxt()
2672 * t3_sge_init_cqcntxt - initialize an SGE completion queue context
2691 return -EINVAL; in t3_sge_init_cqcntxt()
2693 return -EBUSY; in t3_sge_init_cqcntxt()
2709 * t3_sge_enable_ecntxt - enable/disable an SGE egress context
2720 return -EBUSY; in t3_sge_enable_ecntxt()
2734 * t3_sge_disable_fl - disable an SGE free-buffer list
2738 * Disable an SGE free-buffer list. The caller is responsible for
2744 return -EBUSY; in t3_sge_disable_fl()
2758 * t3_sge_disable_rspcntxt - disable an SGE response queue
2768 return -EBUSY; in t3_sge_disable_rspcntxt()
2782 * t3_sge_disable_cqcntxt - disable an SGE completion queue
2792 return -EBUSY; in t3_sge_disable_cqcntxt()
2806 * t3_sge_cqcntxt_op - perform an operation on a completion queue context
2825 return -EBUSY; in t3_sge_cqcntxt_op()
2832 return -EIO; in t3_sge_cqcntxt_op()
2835 if (adapter->params.rev > 0) in t3_sge_cqcntxt_op()
2843 return -EIO; in t3_sge_cqcntxt_op()
2850 * t3_sge_read_context - read an SGE context
2863 return -EBUSY; in t3_sge_read_context()
2869 return -EIO; in t3_sge_read_context()
2878 * t3_sge_read_ecntxt - read an SGE egress context
2889 return -EINVAL; in t3_sge_read_ecntxt()
2894 * t3_sge_read_cq - read an SGE CQ context
2905 return -EINVAL; in t3_sge_read_cq()
2910 * t3_sge_read_fl - read an SGE free-list context
2915 * Read an SGE free-list context. The caller is responsible for ensuring
2921 return -EINVAL; in t3_sge_read_fl()
2926 * t3_sge_read_rspq - read an SGE response queue context
2937 return -EINVAL; in t3_sge_read_rspq()
2942 * t3_config_rss - configure Rx packet steering
2982 * t3_read_rss - read the contents of the RSS tables
3000 return -EAGAIN; in t3_read_rss()
3011 return -EAGAIN; in t3_read_rss()
3018 * t3_tp_set_offload_mode - put TP in NIC/offload mode
3032 * tp_wr_bits_indirect - set/clear bits in an indirect TP register
3049 * t3_enable_filters - enable the HW filters
3063 * t3_disable_filters - disable the HW filters
3070 /* note that we don't want to revert to NIC-only mode */ in t3_disable_filters()
3078 * pm_num_pages - calculate the number of pages of the payload memory
3091 return n - n % 24; in pm_num_pages()
3099 * partition_mem - partition memory and configure TP memory settings
3108 unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5); in partition_mem()
3111 if (adap->params.rev > 0) { in partition_mem()
3125 p->chan_rx_size | (p->chan_tx_size >> 16)); in partition_mem()
3128 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size); in partition_mem()
3129 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs); in partition_mem()
3131 V_TXDATAACKIDX(fls(p->tx_pg_size) - 12)); in partition_mem()
3134 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size); in partition_mem()
3135 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs); in partition_mem()
3137 pstructs = p->rx_num_pgs + p->tx_num_pgs; in partition_mem()
3140 pstructs -= pstructs % 24; in partition_mem()
3147 m += ((p->ntimer_qs - 1) << timers_shift) + (1 << 22); in partition_mem()
3150 mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE); in partition_mem()
3151 mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE); in partition_mem()
3155 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m); in partition_mem()
3157 tids = (p->cm_size - m - (3 << 20)) / 3072 - 32; in partition_mem()
3158 m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - in partition_mem()
3159 adap->params.mc5.nfilters - adap->params.mc5.nroutes; in partition_mem()
3161 adap->params.mc5.nservers += m - tids; in partition_mem()
3193 adap->params.rev > 0 ? F_ENABLEESND : in tp_config()
3205 if (adap->params.rev > 0) { in tp_config()
3216 if (adap->params.rev == T3_REV_C) in tp_config()
3226 if (adap->params.nports > 2) { in tp_config()
3247 * tp_set_timers - set TP timing parameters
3256 unsigned int tre = adap->params.tp.tre; in tp_set_timers()
3257 unsigned int dack_re = adap->params.tp.dack_re; in tp_set_timers()
3278 adap->params.rev > 0 ? 0 : 2 SECONDS); in tp_set_timers()
3292 * t3_tp_set_coalescing_size - set receive coalescing size
3304 return -EINVAL; in t3_tp_set_coalescing_size()
3322 * t3_tp_set_max_rxsize - set the max receive size
3338 * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so in init_mtus()
3361 * init_cong_ctrl - initialize congestion control parameters
3408 * t3_load_mtus - write the MTU and congestion control HW tables
3416 * Update the high-speed congestion control table with the supplied alpha,
3435 log2--; in t3_load_mtus()
3442 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], in t3_load_mtus()
3452 * t3_read_hw_mtus - returns the values in the HW MTU table
3472 * t3_get_cong_cntl_tab - reads the congestion control table
3494 * t3_tp_get_mib_stats - read TP's MIB counters
3507 * t3_read_pace_tbl - read the pace table
3524 * t3_set_pace_tbl - set the pace table
3537 for ( ; n; n--, start++, pace_vals++) in t3_set_pace_tbl()
3545 (start) + (len) - 1); \
3551 (start) + (len) - 1)
3555 unsigned int m = p->chan_rx_size; in ulp_config()
3557 ulp_region(adap, ISCSI, m, p->chan_rx_size / 8); in ulp_config()
3558 ulp_region(adap, TDDP, m, p->chan_rx_size / 8); in ulp_config()
3559 ulptx_region(adap, TPT, m, p->chan_rx_size / 4); in ulp_config()
3560 ulp_region(adap, STAG, m, p->chan_rx_size / 4); in ulp_config()
3561 ulp_region(adap, RQ, m, p->chan_rx_size / 4); in ulp_config()
3562 ulptx_region(adap, PBL, m, p->chan_rx_size / 4); in ulp_config()
3563 ulp_region(adap, PBL, m, p->chan_rx_size / 4); in ulp_config()
3569 * t3_set_proto_sram - set the contents of the protocol sram
3589 return -EIO; in t3_set_proto_sram()
3595 * t3_config_trace_filter - configure one of the tracing filters
3599 * @invert: if set non-matching packets are traced instead of matching ones
3609 key[0] = tp->sport | (tp->sip << 16); in t3_config_trace_filter()
3610 key[1] = (tp->sip >> 16) | (tp->dport << 16); in t3_config_trace_filter()
3611 key[2] = tp->dip; in t3_config_trace_filter()
3612 key[3] = tp->proto | (tp->vlan << 8) | (tp->intf << 20); in t3_config_trace_filter()
3614 mask[0] = tp->sport_mask | (tp->sip_mask << 16); in t3_config_trace_filter()
3615 mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16); in t3_config_trace_filter()
3616 mask[2] = tp->dip_mask; in t3_config_trace_filter()
3617 mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20); in t3_config_trace_filter()
3637 * t3_query_trace_filter - query a tracing filter
3641 * @inverted: non-zero if the filter is inverted
3642 * @enabled: non-zero if the filter is enabled
3661 tp->sport = key[0] & 0xffff; in t3_query_trace_filter()
3662 tp->sip = (key[0] >> 16) | ((key[1] & 0xffff) << 16); in t3_query_trace_filter()
3663 tp->dport = key[1] >> 16; in t3_query_trace_filter()
3664 tp->dip = key[2]; in t3_query_trace_filter()
3665 tp->proto = key[3] & 0xff; in t3_query_trace_filter()
3666 tp->vlan = key[3] >> 8; in t3_query_trace_filter()
3667 tp->intf = key[3] >> 20; in t3_query_trace_filter()
3669 tp->sport_mask = mask[0] & 0xffff; in t3_query_trace_filter()
3670 tp->sip_mask = (mask[0] >> 16) | ((mask[1] & 0xffff) << 16); in t3_query_trace_filter()
3671 tp->dport_mask = mask[1] >> 16; in t3_query_trace_filter()
3672 tp->dip_mask = mask[2]; in t3_query_trace_filter()
3673 tp->proto_mask = mask[3] & 0xff; in t3_query_trace_filter()
3674 tp->vlan_mask = mask[3] >> 8; in t3_query_trace_filter()
3675 tp->intf_mask = mask[3] >> 20; in t3_query_trace_filter()
3682 * t3_config_sched - configure a HW traffic scheduler
3692 unsigned int clk = adap->params.vpd.cclk * 1000; in t3_config_sched()
3696 kbps *= 125; /* -> bytes */ in t3_config_sched()
3702 delta = v >= kbps ? v - kbps : kbps - v; in t3_config_sched()
3712 return -EINVAL; in t3_config_sched()
3715 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); in t3_config_sched()
3726 * t3_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
3735 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t3_set_sched_ipg()
3741 return -EINVAL; in t3_set_sched_ipg()
3755 * t3_get_tx_sched - get the configuration of a Tx HW traffic scheduler
3769 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; in t3_get_tx_sched()
3779 v = (adap->params.vpd.cclk * 1000) / cpt; in t3_get_tx_sched()
3784 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t3_get_tx_sched()
3795 * tp_init - configure TP
3809 tp_set_timers(adap, adap->params.vpd.cclk * 1000); in tp_init()
3823 * t3_mps_set_active_ports - configure port failover
3831 if (port_mask & ~((1 << adap->params.nports) - 1)) in t3_mps_set_active_ports()
3832 return -EINVAL; in t3_mps_set_active_ports()
3839 * chan_init_hw - channel-dependent HW initialization
3900 return -1; in calibrate_xgm()
3947 return -EIO; in wrreg_wait()
3965 adapter_t *adapter = mc7->adapter; in mc7_init()
3968 if (!mc7->size) in mc7_init()
3971 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_init()
3976 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3977 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3981 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3982 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL); in mc7_init()
3984 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & in mc7_init()
3987 mc7->name); in mc7_init()
3992 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3993 V_ACTTOPREDLY(p->ActToPreDly) | in mc7_init()
3994 V_ACTTORDWRDLY(p->ActToRdWrDly) | V_PRECYC(p->PreCyc) | in mc7_init()
3995 V_REFCYC(p->RefCyc[density]) | V_BKCYC(p->BkCyc) | in mc7_init()
3996 V_WRTORDDLY(p->WrToRdDly) | V_RDTOWRDLY(p->RdToWrDly)); in mc7_init()
3998 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
4000 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
4003 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, in mc7_init()
4008 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4009 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || in mc7_init()
4010 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || in mc7_init()
4011 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4015 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
4016 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, in mc7_init()
4021 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4022 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4023 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4024 wrreg_wait(adapter, mc7->offset + A_MC7_MODE, in mc7_init()
4026 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || in mc7_init()
4027 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4032 mc7_clock /= 1000000; /* KHz->MHz, ns->us */ in mc7_init()
4034 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
4036 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ in mc7_init()
4038 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, in mc7_init()
4040 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
4041 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
4042 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
4043 (mc7->size << width) - 1); in mc7_init()
4044 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
4045 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ in mc7_init()
4050 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); in mc7_init()
4051 } while ((val & F_BUSY) && --attempts); in mc7_init()
4053 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); in mc7_init()
4058 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); in mc7_init()
4062 return -1; in mc7_init()
4085 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, in config_pcie()
4096 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, in config_pcie()
4102 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, in config_pcie()
4106 fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : in config_pcie()
4108 log2_width = fls(adap->params.pci.width) - 1; in config_pcie()
4114 if (adap->params.rev == 0) in config_pcie()
4132 * t3_init_hw - initialize and configure T3 HW modules
4146 int err = -EIO, attempts, i; in t3_init_hw()
4147 const struct vpd_params *vpd = &adapter->params.vpd; in t3_init_hw()
4149 if (adapter->params.rev > 0) in t3_init_hw()
4154 if (adapter->params.nports > 2) in t3_init_hw()
4155 t3_mac_init(&adap2pinfo(adapter, 0)->mac); in t3_init_hw()
4157 if (vpd->mclk) { in t3_init_hw()
4158 partition_mem(adapter, &adapter->params.tp); in t3_init_hw()
4160 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4161 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4162 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4163 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, in t3_init_hw()
4164 adapter->params.mc5.nfilters, in t3_init_hw()
4165 adapter->params.mc5.nroutes)) in t3_init_hw()
4173 if (tp_init(adapter, &adapter->params.tp)) in t3_init_hw()
4177 min(adapter->params.sge.max_pkt_size, in t3_init_hw()
4180 min(adapter->params.sge.max_pkt_size, 16384U)); in t3_init_hw()
4181 ulp_config(adapter, &adapter->params.tp); in t3_init_hw()
4188 if (adapter->params.rev == T3_REV_C) in t3_init_hw()
4195 chan_init_hw(adapter, adapter->params.chan_map); in t3_init_hw()
4196 t3_sge_init(adapter, &adapter->params.sge); in t3_init_hw()
4201 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
4209 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); in t3_init_hw()
4221 * get_pci_mode - determine a card's PCI mode
4237 p->variant = PCI_VARIANT_PCIE; in get_pci_mode()
4238 p->pcie_cap_addr = pcie_cap; in get_pci_mode()
4241 p->width = (val >> 4) & 0x3f; in get_pci_mode()
4246 p->speed = speed_map[G_PCLKRANGE(pci_mode)]; in get_pci_mode()
4247 p->width = (pci_mode & F_64BIT) ? 64 : 32; in get_pci_mode()
4250 p->variant = PCI_VARIANT_PCI; in get_pci_mode()
4252 p->variant = PCI_VARIANT_PCIX_MODE1_PARITY; in get_pci_mode()
4254 p->variant = PCI_VARIANT_PCIX_MODE1_ECC; in get_pci_mode()
4256 p->variant = PCI_VARIANT_PCIX_266_MODE2; in get_pci_mode()
4260 * init_link_config - initialize a link's SW state
4265 * capabilities and default speed/duplex/flow-control/autonegotiation
4271 lc->supported = caps; in init_link_config()
4272 lc->requested_speed = lc->speed = SPEED_INVALID; in init_link_config()
4273 lc->requested_duplex = lc->duplex = DUPLEX_INVALID; in init_link_config()
4274 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; in init_link_config()
4275 if (lc->supported & SUPPORTED_Autoneg) { in init_link_config()
4276 lc->advertising = lc->supported; in init_link_config()
4277 lc->autoneg = AUTONEG_ENABLE; in init_link_config()
4278 lc->requested_fc |= PAUSE_AUTONEG; in init_link_config()
4280 lc->advertising = 0; in init_link_config()
4281 lc->autoneg = AUTONEG_DISABLE; in init_link_config()
4286 * mc7_calc_size - calculate MC7 memory size
4308 mc7->adapter = adapter; in mc7_prep()
4309 mc7->name = name; in mc7_prep()
4310 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; in mc7_prep()
4311 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_prep()
4312 mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); in mc7_prep()
4313 mc7->width = G_WIDTH(cfg); in mc7_prep()
4320 mac->adapter = adapter; in mac_prep()
4321 mac->multiport = adapter->params.nports > 2; in mac_prep()
4322 if (mac->multiport) { in mac_prep()
4323 mac->ext_port = (unsigned char)index; in mac_prep()
4324 mac->nucast = 8; in mac_prep()
4326 mac->nucast = 1; in mac_prep()
4333 if (mac->multiport || in mac_prep()
4334 (!adapter->params.vpd.xauicfg[1] && (devid==0x37))) in mac_prep()
4337 mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index; in mac_prep()
4339 if (adapter->params.rev == 0 && uses_xaui(adapter)) { in mac_prep()
4340 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, in mac_prep()
4342 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset, in mac_prep()
4348 * early_hw_init - HW initialization done at card detection time
4358 u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ? in early_hw_init()
4360 u32 gpio_out = ai->gpio_out; in early_hw_init()
4364 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); in early_hw_init()
4370 if (adapter->params.rev == 0 || !uses_xaui(adapter)) in early_hw_init()
4385 * t3_reset_adapter - reset the adapter
4393 adapter->params.rev < T3_REV_B2 && is_pcie(adapter); in t3_reset_adapter()
4412 return -1; in t3_reset_adapter()
4424 return -EBUSY; in init_parity()
4450 * t3_prep_adapter - prepare SW and HW for operation
4464 get_pci_mode(adapter, &adapter->params.pci); in t3_prep_adapter()
4466 adapter->params.info = ai; in t3_prep_adapter()
4467 adapter->params.nports = ai->nports0 + ai->nports1; in t3_prep_adapter()
4468 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1); in t3_prep_adapter()
4469 adapter->params.rev = t3_read_reg(adapter, A_PL_REV); in t3_prep_adapter()
4479 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
4481 if (adapter->params.nports > 2) in t3_prep_adapter()
4482 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS; in t3_prep_adapter()
4484 adapter->params.stats_update_period = is_10G(adapter) ? in t3_prep_adapter()
4486 adapter->params.pci.vpd_cap_addr = in t3_prep_adapter()
4489 ret = get_vpd_params(adapter, &adapter->params.vpd); in t3_prep_adapter()
4494 return -1; in t3_prep_adapter()
4496 if (adapter->params.vpd.mclk) { in t3_prep_adapter()
4497 struct tp_params *p = &adapter->params.tp; in t3_prep_adapter()
4499 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX"); in t3_prep_adapter()
4500 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); in t3_prep_adapter()
4501 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); in t3_prep_adapter()
4503 p->nchan = adapter->params.chan_map == 3 ? 2 : 1; in t3_prep_adapter()
4504 p->pmrx_size = t3_mc7_size(&adapter->pmrx); in t3_prep_adapter()
4505 p->pmtx_size = t3_mc7_size(&adapter->pmtx); in t3_prep_adapter()
4506 p->cm_size = t3_mc7_size(&adapter->cm); in t3_prep_adapter()
4507 p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */ in t3_prep_adapter()
4508 p->chan_tx_size = p->pmtx_size / p->nchan; in t3_prep_adapter()
4509 p->rx_pg_size = 64 * 1024; in t3_prep_adapter()
4510 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; in t3_prep_adapter()
4511 p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size); in t3_prep_adapter()
4512 p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size); in t3_prep_adapter()
4513 p->ntimer_qs = p->cm_size >= (128 << 20) || in t3_prep_adapter()
4514 adapter->params.rev > 0 ? 12 : 6; in t3_prep_adapter()
4515 p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) - in t3_prep_adapter()
4517 p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */ in t3_prep_adapter()
4520 adapter->params.offload = t3_mc7_size(&adapter->pmrx) && in t3_prep_adapter()
4521 t3_mc7_size(&adapter->pmtx) && in t3_prep_adapter()
4522 t3_mc7_size(&adapter->cm); in t3_prep_adapter()
4524 t3_sge_prep(adapter, &adapter->params.sge); in t3_prep_adapter()
4527 adapter->params.mc5.nservers = DEFAULT_NSERVERS; in t3_prep_adapter()
4529 adapter->params.mc5.nfilters = 0; in t3_prep_adapter()
4530 adapter->params.mc5.nroutes = 0; in t3_prep_adapter()
4531 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); in t3_prep_adapter()
4533 init_mtus(adapter->params.mtus); in t3_prep_adapter()
4534 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t3_prep_adapter()
4542 if (adapter->params.nports > 2 && in t3_prep_adapter()
4543 (ret = t3_vsc7323_init(adapter, adapter->params.nports))) in t3_prep_adapter()
4552 unsigned port_type = adapter->params.vpd.port_type[j]; in t3_prep_adapter()
4558 return -EINVAL; in t3_prep_adapter()
4561 if (j >= ARRAY_SIZE(adapter->params.vpd.port_type)) in t3_prep_adapter()
4562 return -EINVAL; in t3_prep_adapter()
4564 ret = pti->phy_prep(p, ai->phy_base_addr + j, in t3_prep_adapter()
4565 ai->mdio_ops); in t3_prep_adapter()
4568 mac_prep(&p->mac, adapter, j); in t3_prep_adapter()
4576 memcpy(hw_addr, adapter->params.vpd.eth_base, 5); in t3_prep_adapter()
4577 hw_addr[5] = adapter->params.vpd.eth_base[5] + i; in t3_prep_adapter()
4580 init_link_config(&p->link_config, p->phy.caps); in t3_prep_adapter()
4581 p->phy.ops->power_down(&p->phy, 1); in t3_prep_adapter()
4588 if (!(p->phy.caps & SUPPORTED_IRQ) && in t3_prep_adapter()
4589 adapter->params.linkpoll_period > 10) in t3_prep_adapter()
4590 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
4597 * t3_reinit_adapter - prepare HW for operation again
4610 early_hw_init(adap, adap->params.info); in t3_reinit_adapter()
4615 if (adap->params.nports > 2 && in t3_reinit_adapter()
4616 (ret = t3_vsc7323_init(adap, adap->params.nports))) in t3_reinit_adapter()
4624 unsigned port_type = adap->params.vpd.port_type[j]; in t3_reinit_adapter()
4630 return -EINVAL; in t3_reinit_adapter()
4633 if (j >= ARRAY_SIZE(adap->params.vpd.port_type)) in t3_reinit_adapter()
4634 return -EINVAL; in t3_reinit_adapter()
4636 ret = pti->phy_prep(p, p->phy.addr, NULL); in t3_reinit_adapter()
4639 p->phy.ops->power_down(&p->phy, 1); in t3_reinit_adapter()
4678 return -EIO; in t3_cim_hac_read()
4696 return -EIO; in t3_cim_hac_write()
4707 return -EINVAL; in t3_get_up_la()
4735 --cnt; in t3_get_up_la()
4742 return -EIO; in t3_get_up_la()
4769 return -EINVAL; in t3_get_up_ioqs()