Lines Matching +full:clock +full:- +full:div
1 /*-
61 uint32_t div;
80 if (sc->freq == 0)
92 if ((sc->mult != 0) && (sc->div != 0))
93 *freq = (*freq / sc->div) * sc->mult;
95 *freq = sc->freq;
106 if (sc->mult == 0 || sc->div == 0) {
107 /* Fixed frequency clock. */
109 if (*fout != sc->freq)
113 /* Fixed factor clock. */
115 *fout = (*fout / sc->mult) * sc->div;
125 clk = clknode_create(clkdom, &clknode_fixed_class, &clkdef->clkdef);
130 sc->fixed_flags = clkdef->fixed_flags;
131 sc->freq = clkdef->freq;
132 sc->mult = clkdef->mult;
133 sc->div = clkdef->div;
142 {"fixed-clock", CLK_TYPE_FIXED},
143 {"fixed-factor-clock", CLK_TYPE_FIXED_FACTOR},
157 clk_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
160 if (OF_hasprop(ofw_bus_get_node(dev), "clock-frequency") == 0) {
162 "clock-fixed has no clock-frequency\n");
165 device_set_desc(dev, "Fixed clock");
168 device_set_desc(dev, "Fixed factor clock");
187 def->clkdef.id = 1;
188 rv = OF_getencprop(node, "clock-frequency", &freq, sizeof(freq));
191 def->freq = freq;
202 def->clkdef.id = 1;
203 rv = OF_getencprop(node, "clock-mult", &def->mult, sizeof(def->mult));
206 rv = OF_getencprop(node, "clock-div", &def->div, sizeof(def->div));
209 /* Get name of parent clock */
210 rv = clk_get_by_ofw_index(sc->dev, 0, 0, &parent);
213 def->clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP, M_WAITOK);
214 def->clkdef.parent_names[0] = clk_get_name(parent);
215 def->clkdef.parent_cnt = 1;
230 sc->dev = dev;
232 clk_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
242 device_printf(sc->dev, "Cannot FDT parameters.\n");
247 device_printf(sc->dev, "Cannot parse clock name.\n");
250 sc->clkdom = clkdom_create(dev);
251 KASSERT(sc->clkdom != NULL, ("Clock domain is NULL"));
253 rv = clknode_fixed_register(sc->clkdom, &def);
255 device_printf(sc->dev, "Cannot register fixed clock.\n");
260 rv = clkdom_finit(sc->clkdom);
262 device_printf(sc->dev, "Clk domain finit fails.\n");
268 clkdom_dump(sc->clkdom);