Lines Matching +full:div +full:- +full:clk

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
48 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
50 /* Non-exported clocks */
65 	CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
66 	CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0)
67 	CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0)
68 	CCU_GATE(CLK_R_APB2_UART, "r_apb1-uart", "r_apb2", 0x18c, 0)
69 	CCU_GATE(CLK_R_APB2_I2C, "r_apb1-i2c", "r_apb2", 0x19c, 0)
70 	CCU_GATE(CLK_R_APB1_IR, "r_apb1-ir", "r_apb1", 0x1cc, 0)
71 	CCU_GATE(CLK_R_APB1_W1, "r_apb1-w1", "r_apb1", 0x1ec, 0)
79     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,			/* div */
90     1,				/* div */
99     0, NULL);			/* flags, div table */
106     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,			/* div */
111 	{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk},
112 	{ .type = AW_CLK_FIXED, .clk.fixed = &r_ahb_clk},
113 	{ .type = AW_CLK_DIV, .clk.div = &r_apb1_clk},
114 	{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &r_apb2_clk},
118 	{ "allwinner,sun50i-h6-r-ccu", 1 },
129 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in ccu_sun50i_h6_r_probe()
143 	sc->resets = ccu_sun50i_h6_r_resets;  in ccu_sun50i_h6_r_attach()
144 	sc->nresets = nitems(ccu_sun50i_h6_r_resets);  in ccu_sun50i_h6_r_attach()
145 	sc->gates = ccu_sun50i_h6_r_gates;  in ccu_sun50i_h6_r_attach()
146 	sc->ngates = nitems(ccu_sun50i_h6_r_gates);  in ccu_sun50i_h6_r_attach()
147 	sc->clks = clks;  in ccu_sun50i_h6_r_attach()
148 	sc->nclks = nitems(clks);  in ccu_sun50i_h6_r_attach()