Lines Matching +full:0 +full:x0000003f
46 #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0)
50 #define CHIPC_ID 0x00
51 #define CHIPC_CAPABILITIES 0x04
52 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */
53 #define CHIPC_BIST 0x0C
55 #define CHIPC_OTPST 0x10 /**< otp status */
56 #define CHIPC_OTPCTRL 0x14 /**< otp control */
57 #define CHIPC_OTPPROG 0x18
58 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */
60 #define CHIPC_INTST 0x20 /**< interrupt status */
61 #define CHIPC_INTM 0x24 /**< interrupt mask */
63 #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */
64 #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */
66 #define CHIPC_JTAGCMD 0x30
67 #define CHIPC_JTAGIR 0x34
68 #define CHIPC_JTAGDR 0x38
69 #define CHIPC_JTAGCTRL 0x3c
71 #define CHIPC_SFLASH_BASE 0x40
73 #define CHIPC_SFLASHCTRL 0x40
74 #define CHIPC_SFLASHADDR 0x44
75 #define CHIPC_SFLASHDATA 0x48
78 #define CHIPC_SBBCAST_ADDR 0x50
79 #define CHIPC_SBBCAST_DATA 0x54
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
82 #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */
83 #define CHIPC_GPIOIN 0x60
84 #define CHIPC_GPIOOUT 0x64
85 #define CHIPC_GPIOOUTEN 0x68
86 #define CHIPC_GPIOCTRL 0x6C
87 #define CHIPC_GPIOPOL 0x70
88 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */
90 #define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */
91 #define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */
93 #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */
95 #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
98 #define CHIPC_GPIOTIMEROUTMASK 0x8C
101 #define CHIPC_CLKC_N 0x90
102 #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */
103 #define CHIPC_CLKC_PCI 0x98 /* m1 */
104 #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */
105 #define CHIPC_CLKC_M3 0xA0 /* cpu */
106 #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */
108 #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */
109 #define CHIPC_CAPABILITIES_EXT 0xAC
112 #define CHIPC_PLL_ON_DELAY 0xB0 /* rev >= 4 */
113 #define CHIPC_PLL_FREFSEL_DELAY 0xB4 /* rev >= 4 */
114 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */
117 #define CHIPC_SYS_CLK_CTL 0xC0 /* "instaclock" (rev >= 10) */
118 #define CHIPC_SYS_CLK_ST_STRETCH 0xC4 /* state strech (?) rev >= 10 */
121 #define CHIPC_BP_ADDRLOW 0xD0
122 #define CHIPC_BP_ADDRHIGH 0xD4
123 #define CHIPC_BP_DATA 0xD8
124 #define CHIPC_BP_INDACCESS 0xE0
127 #define CHIPC_GSIO_CTRL 0xE4
128 #define CHIPC_GSIO_ADDR 0xE8
129 #define CHIPC_GSIO_DATA 0xEC
132 #define CHIPC_CLKDIV2 0xF0
134 #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address
138 #define CHIPC_PCMCIA_CFG 0x100
139 #define CHIPC_PCMCIA_MEMWAIT 0x104
140 #define CHIPC_PCMCIA_ATTRWAIT 0x108
141 #define CHIPC_PCMCIA_IOWAIT 0x10C
142 #define CHIPC_IDE_CFG 0x110
143 #define CHIPC_IDE_MEMWAIT 0x114
144 #define CHIPC_IDE_ATTRWAIT 0x118
145 #define CHIPC_IDE_IOWAIT 0x11C
146 #define CHIPC_PROG_CFG 0x120
147 #define CHIPC_PROG_WAITCOUNT 0x124
148 #define CHIPC_FLASH_CFG 0x128
149 #define CHIPC_FLASH_WAITCOUNT 0x12C
150 #define CHIPC_SECI_CFG 0x130
151 #define CHIPC_SECI_ST 0x134
152 #define CHIPC_SECI_STM 0x138
153 #define CHIPC_SECI_RXNBC 0x13C
156 #define CHIPC_ECI_OUTPUT 0x140
157 #define CHIPC_ECI_CTRL 0x144
158 #define CHIPC_ECI_INPUTLO 0x148
159 #define CHIPC_ECI_INPUTMI 0x14C
160 #define CHIPC_ECI_INPUTHI 0x150
161 #define CHIPC_ECI_INPUTINTPOLARITYLO 0x154
162 #define CHIPC_ECI_INPUTINTPOLARITYMI 0x158
163 #define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C
164 #define CHIPC_ECI_INTMASKLO 0x160
165 #define CHIPC_ECI_INTMASKMI 0x164
166 #define CHIPC_ECI_INTMASKHI 0x168
167 #define CHIPC_ECI_EVENTLO 0x16C
168 #define CHIPC_ECI_EVENTMI 0x170
169 #define CHIPC_ECI_EVENTHI 0x174
170 #define CHIPC_ECI_EVENTMASKLO 0x178
171 #define CHIPC_ECI_EVENTMASKMI 0x17C
172 #define CHIPC_ECI_EVENTMASKHI 0x180
174 #define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */
176 #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */
177 #define CHIPC_SPROM_ADDR 0x194
178 #define CHIPC_SPROM_DATA 0x198
181 #define CHIPC_CLK_CTL_ST 0x1E0
182 #define CHIPC_SPROM_HWWAR 0x19
184 #define CHIPC_UART_BASE 0x300
185 #define CHIPC_UART_SIZE 0x100
190 #define CHIPC_PMU_BASE 0x600
191 #define CHIPC_PMU_SIZE 0x70
193 #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */
194 #define CHIPC_SPROM_OTP_SIZE 0x400
197 #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */
198 #define CHIPC_ID_CHIP_SHIFT 0
199 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */
201 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */
203 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */
205 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */
209 #define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */
210 #define CHIPC_CAP_NUM_UART_SHIFT 0
211 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
212 #define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */
214 #define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */
215 #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
216 #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
218 #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */
219 #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */
220 #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */
221 #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
223 #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */
224 #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */
225 #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */
226 #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */
227 #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */
228 #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
230 #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power/clock control */
231 #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */
234 #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
235 #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */
236 #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
237 #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
238 #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */
239 #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */
240 #define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? …
242 #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
243 #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */
244 #define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */
245 #define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49)
260 CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */
266 #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */
267 #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0
268 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31)
277 #define CHIPC_PLL_NONE 0x0
278 #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */
279 #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */
280 #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */
281 #define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */
282 #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */
283 #define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */
284 #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */
294 #define CHIPC_ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
304 #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
305 #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
306 #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
309 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
310 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
311 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */
314 #define CHIPC_OTPS_OL_MASK 0x000000ff
315 #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */
316 #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
317 #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
318 #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */
319 #define CHIPC_OTPS_GUP_MASK 0x00000f00
321 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
322 #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
323 #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
324 #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
325 #define CHIPC_OTPS_READY 0x00001000
327 #define CHIPC_OTPS_RV_MASK 0x0fff0000
330 #define CHIPC_OTPC_PROGSEL 0x00000001
331 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e
333 #define CHIPC_OTPC_VSEL_MASK 0x000000f0
335 #define CHIPC_OTPC_TMM_MASK 0x00000700
337 #define CHIPC_OTPC_ODM 0x00000800
338 #define CHIPC_OTPC_PROGEN 0x80000000
341 #define CHIPC_OTPP_COL_MASK 0x000000ff
342 #define CHIPC_OTPP_COL_SHIFT 0
343 #define CHIPC_OTPP_ROW_MASK 0x0000ff00
345 #define CHIPC_OTPP_OC_MASK 0x0f000000
347 #define CHIPC_OTPP_READERR 0x10000000
348 #define CHIPC_OTPP_VALUE_MASK 0x20000000
350 #define CHIPC_OTPP_START_BUSY 0x80000000
351 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */
354 #define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */
356 #define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */
357 #define CHIPC_OTPL_GUP_SHIFT 0
358 #define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */
361 #define CHIPC_OTPPOC_READ 0
377 #define CHIPC_JCMD_START 0x80000000
378 #define CHIPC_JCMD_BUSY 0x80000000
379 #define CHIPC_JCMD_STATE_MASK 0x60000000
380 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */
381 #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */
382 #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */
383 #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */
384 #define CHIPC_JCMD0_ACC_MASK 0x0000f000
385 #define CHIPC_JCMD0_ACC_IRDR 0x00000000
386 #define CHIPC_JCMD0_ACC_DR 0x00001000
387 #define CHIPC_JCMD0_ACC_IR 0x00002000
388 #define CHIPC_JCMD0_ACC_RESET 0x00003000
389 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000
390 #define CHIPC_JCMD0_ACC_PDR 0x00005000
391 #define CHIPC_JCMD0_IRW_MASK 0x00000f00
392 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
393 #define CHIPC_JCMD_ACC_IRDR 0x00000000
394 #define CHIPC_JCMD_ACC_DR 0x00010000
395 #define CHIPC_JCMD_ACC_IR 0x00020000
396 #define CHIPC_JCMD_ACC_RESET 0x00030000
397 #define CHIPC_JCMD_ACC_IRPDR 0x00040000
398 #define CHIPC_JCMD_ACC_PDR 0x00050000
399 #define CHIPC_JCMD_ACC_PIR 0x00060000
400 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */
401 #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */
402 #define CHIPC_JCMD_IRW_MASK 0x00001f00
404 #define CHIPC_JCMD_DRW_MASK 0x0000003f
412 #define CHIPC_CLKD_SFLASH 0x0f000000
414 #define CHIPC_CLKD_OTP 0x000f0000
416 #define CHIPC_CLKD_JTAG 0x00000f00
418 #define CHIPC_CLKD_UART 0x000000ff
420 #define CHIPC_CLKD2_SPROM 0x00000003
423 #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */
424 #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */
425 #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
426 #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
427 #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
428 #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */
429 #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */
432 #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */
433 #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
434 #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
435 #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
436 #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
437 #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
438 * 0: LPO is enabled
440 #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
441 * 0: power logic control
443 #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
446 #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
449 #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
450 #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
454 #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
455 #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
456 #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */
457 #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
458 #define CHIPC_SYCC_HR 0x00000010 /* Force HT */
459 #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
463 #define CHIPC_BPIA_BYTEEN 0x0000000f
464 #define CHIPC_BPIA_SZ1 0x00000001
465 #define CHIPC_BPIA_SZ2 0x00000003
466 #define CHIPC_BPIA_SZ4 0x00000007
467 #define CHIPC_BPIA_SZ8 0x0000000f
468 #define CHIPC_BPIA_WRITE 0x00000100
469 #define CHIPC_BPIA_START 0x00000200
470 #define CHIPC_BPIA_BUSY 0x00000200
471 #define CHIPC_BPIA_ERROR 0x00000400
474 #define CHIPC_CF_EN 0x00000001 /* enable */
475 #define CHIPC_CF_EM_MASK 0x0000000e /* mode */
477 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */
480 #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */
481 #define CHIPC_CF_BS 0x00000020 /* byteswap */
482 #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */
484 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */
485 #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */
486 #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */
487 #define CHIPC_CF_CE 0x00000100 /* clock enable */
488 #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */
491 #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */
492 #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */
494 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */
496 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */
500 #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */
501 #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */
503 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */
505 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */
509 #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */
510 #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */
512 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */
514 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */
518 #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */
519 #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */
521 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */
523 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */
526 #define CHIPC_PW_W0 0x0000000c
527 #define CHIPC_PW_W1 0x00000a00
528 #define CHIPC_PW_W2 0x00020000
529 #define CHIPC_PW_W3 0x01000000
532 #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */
533 #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */
535 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */
537 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */
541 #define CHIPC_SRC_START 0x80000000
542 #define CHIPC_SRC_BUSY 0x80000000
543 #define CHIPC_SRC_OPCODE 0x60000000
544 #define CHIPC_SRC_OP_READ 0x00000000
545 #define CHIPC_SRC_OP_WRITE 0x20000000
546 #define CHIPC_SRC_OP_WRDIS 0x40000000
547 #define CHIPC_SRC_OP_WREN 0x60000000
548 #define CHIPC_SRC_OTPSEL 0x00000010
549 #define CHIPC_SRC_LOCK 0x00000008
550 #define CHIPC_SRC_SIZE_MASK 0x00000006
551 #define CHIPC_SRC_SIZE_1K 0x00000000
552 #define CHIPC_SRC_SIZE_4K 0x00000002
553 #define CHIPC_SRC_SIZE_16K 0x00000004
555 #define CHIPC_SRC_PRESENT 0x00000001
566 #define CHIPC_CN_N1_MASK 0x3f /* n1 control */
567 #define CHIPC_CN_N1_SHIFT 0
568 #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */
570 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */
574 #define CHIPC_M1_MASK 0x3f /* m1 control */
575 #define CHIPC_M1_SHIFT 0
576 #define CHIPC_M2_MASK 0x3f00 /* m2 control */
578 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */
580 #define CHIPC_MC_MASK 0x1f000000 /* mux control */
584 #define CHIPC_F6_2 0x02 /* A factor of 2 in */
585 #define CHIPC_F6_3 0x03 /* 6-bit fields like */
586 #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */
587 #define CHIPC_F6_5 0x09
588 #define CHIPC_F6_6 0x11
589 #define CHIPC_F6_7 0x21
593 #define CHIPC_MC_BYPASS 0x08
594 #define CHIPC_MC_M1 0x04
595 #define CHIPC_MC_M1M2 0x02
596 #define CHIPC_MC_M1M2M3 0x01
597 #define CHIPC_MC_M1M3 0x11
609 #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */
618 #define CHIPC_CLKC_5350_N 0x0311
619 #define CHIPC_CLKC_5350_M 0x04020009
622 #define CHIPC_CFG_EN 0x0001 /* Enable */
623 #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */
624 #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
625 #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */
626 #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
627 #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */
628 #define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
629 #define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
630 #define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
631 #define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
632 #define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
635 #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
636 #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
637 #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
638 #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
639 #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */
640 #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
641 #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
642 #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
643 #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
646 #define CHIPC_SFLASH_OPCODE 0x000000ff
647 #define CHIPC_SFLASH_ACTION 0x00000700
648 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
649 #define CHIPC_SFLASH_START 0x80000000
653 #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
654 #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
655 #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */
656 #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */
657 #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */
658 #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */
659 #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */
662 #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */
663 #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */
664 #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */
665 #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */
666 #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */
667 #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */
668 #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */
669 #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */
670 #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */
671 #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
672 #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
673 #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */
676 #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */
677 #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */
678 #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */
680 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
683 #define CHIPC_SFLASH_AT_READ 0x07e8
684 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2
687 #define CHIPC_SFLASH_AT_STATUS 0x01d7
688 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384
689 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387
690 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
691 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
692 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288
693 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289
694 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281
695 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250
696 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
697 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
698 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253
699 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255
700 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260
701 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261
702 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258
703 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259
706 #define CHIPC_SFLASH_AT_READY 0x80
707 #define CHIPC_SFLASH_AT_MISMATCH 0x40
708 #define CHIPC_SFLASH_AT_ID_MASK 0x38
717 #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */
718 #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
719 #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
720 #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
729 #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */
730 #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */
731 #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
732 #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */
733 #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */
734 #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */
735 #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
736 #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */
737 #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */
738 #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */
739 #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */
740 #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */
744 #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
745 #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
746 #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */
747 #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */
748 #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */
749 #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */
750 #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
751 #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */
762 #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004
764 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008
766 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0
768 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
774 #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004
782 #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020
785 #define CHIPC_CST4322_PCI_OR_USB 0x00000100
786 #define CHIPC_CST4322_BOOT_MASK 0x00000600
788 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
792 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800
793 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000
795 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */
797 #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000
798 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000
800 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */
804 #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000
805 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000
806 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000
809 #define CHIPC_CST43236_SFLASH_MASK 0x00000040
810 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080
812 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
813 #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
814 #define CHIPC_CST43236_BOOT_MASK 0x00001800
816 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
822 #define CHIPC_CST43237_BP_CLK 0x00000200 /* 96/80Mbps */
825 #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */
826 #define CHIPC_CST4331_SPROM_PRESENT 0x00000002
827 #define CHIPC_CST4331_OTP_PRESENT 0x00000004
828 #define CHIPC_CST4331_LDO_RF 0x00000008
829 #define CHIPC_CST4331_LDO_PAR 0x00000010
832 #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */
833 #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */
834 #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */
836 #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */
844 #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */
851 #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */
852 #define CHIPC_CST4315_RCAL_VALID 0x00000008
853 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0
855 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */
856 #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00
857 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400
858 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00
861 #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001
862 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002
863 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008
866 #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */
867 #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600
868 #define CHIPC_CST4319_ILPDIV_EN 0x00000800
869 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000
870 #define CHIPC_CST4319_LPO_SEL 0x00002000
871 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000
872 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */
873 #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000
874 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000
875 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000
876 #define CHIPC_CST4319_RCAL_VALID 0x01000000
877 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000
881 #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001
882 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002
883 #define CHIPC_CST4336_OTP_PRESENT 0x00000004
884 #define CHIPC_CST4336_ARMREMAP_0 0x00000008
885 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010
887 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020
889 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040
891 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180
893 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600
897 #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */
898 #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */
899 #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */
900 #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */
901 #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */
902 #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */
903 #define CHIPC_CST4330_OTP_PRESENT 0x00000010
904 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020
905 #define CHIPC_CST4330_ARMREMAP_0 0x00000040
906 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */
907 #define CHIPC_CST4330_ILPDIV_EN 0x00000100
908 #define CHIPC_CST4330_LPO_SEL 0x00000200
910 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00
912 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000
913 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000
914 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000
915 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000
916 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000
921 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002
922 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0
925 #define CHIPC_CST43228_ILP_DIV_EN 0x1
926 #define CHIPC_CST43228_OTP_PRESENT 0x2
927 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4
928 #define CHIPC_CST43228_SDIO_MODE 0x8
930 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10
931 #define CHIPC_CST43228_SDIO_RESET 0x20
934 #define CHIPC_CST4706_LOWCOST_PKG (1<<0) /* 0: full-featured package 1: low-cost package */
935 #define CHIPC_CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */
936 #define CHIPC_CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
937 #define CHIPC_CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */
941 #define CHIPC_FLSTRCF4706_MASK 0x000000ff
942 #define CHIPC_FLSTRCF4706_SF1 0x00000001 /* 2nd serial flash present */
943 #define CHIPC_FLSTRCF4706_PF1 0x00000002 /* 2nd parallel flash present */
944 #define CHIPC_FLSTRCF4706_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
945 #define CHIPC_FLSTRCF4706_NF1 0x00000008 /* 2nd NAND flash present */
946 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /* Valid value mask */
948 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_4MB 0x1 /* 4MB */
949 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_8MB 0x2 /* 8MB */
950 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_16MB 0x3 /* 16MB */
951 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_32MB 0x4 /* 32MB */
952 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_64MB 0x5 /* 64MB */
953 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_128MB 0x6 /* 128MB */
954 #define CHIPC_FLSTRCF4706_1ST_MADDR_SEG_256MB 0x7 /* 256MB */
958 * - BT packet type information bits [7:0]
960 /* [3:0] - Task (link) type */
961 #define CHIPC_BT_ACL 0x00
962 #define CHIPC_BT_SCO 0x01
963 #define CHIPC_BT_eSCO 0x02
964 #define CHIPC_BT_A2DP 0x03
965 #define CHIPC_BT_SNIFF 0x04
966 #define CHIPC_BT_PAGE_SCAN 0x05
967 #define CHIPC_BT_INQUIRY_SCAN 0x06
968 #define CHIPC_BT_PAGE 0x07
969 #define CHIPC_BT_INQUIRY 0x08
970 #define CHIPC_BT_MSS 0x09
971 #define CHIPC_BT_PARK 0x0a
972 #define CHIPC_BT_RSSISCAN 0x0b
973 #define CHIPC_BT_MD_ACL 0x0c
974 #define CHIPC_BT_MD_eSCO 0x0d
975 #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e
976 #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f
979 #define CHIPC_BT_MASTER 0
982 #define CHIPC_BT_LOWEST_PRIO 0x0
983 #define CHIPC_BT_HIGHEST_PRIO 0x3