Lines Matching +full:local +full:- +full:bd +full:- +full:address
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
19 * 4. Neither the name of the author nor the names of any co-contributors
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
58 * set, the device I/O mapping consumes 32MB of host address space,
61 * Flat mode consumes so much host address space that it is not
428 * PCI state register -- note, this register is read only
434 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
447 * PCI Clock Control register -- note, this register is read only
473 * Each mailbox is 64-bits wide, though we only use the
474 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
873 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
879 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
991 * Send BD Ring Selector Control registers
1013 /* Send BD Ring Selector Mode register */
1018 /* Send BD Ring Selector Status register */
1021 /* Send BD Ring Selector HW Diagnostics register */
1028 * Send BD Initiator Selector Control registers
1049 /* Send BD Initiator Mode register */
1054 /* Send BD Initiator Status register */
1058 * Send BD Completion Control registers
1063 /* Send BD Completion Control Mode register */
1068 /* Send BD Completion Control Status register */
1167 * Receive Data and Receive BD Initiator Control Registers
1204 /* Receive Data and Receive BD Initiator Mode register */
1211 /* Receive Data and Receive BD Initiator Status register */
1227 * Receive BD Initiator Control registers
1241 /* Receive BD Initiator Mode register */
1246 /* Receive BD Initiator Status register */
1250 * Receive BD Completion Control registers
1258 /* Receive BD completion mode register */
1263 /* Receive BD completion status register */
1365 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1366 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1594 /* BD Read DMA Mode register */
1596 /* BD Read DMA Mode status register */
1602 /* Non-LSO Read DMA Mode register */
1604 /* Non-LSO Read DMA Mode status register */
2031 /* Misc. Local Control */
2060 /* EEPROM address register */
2205 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2212 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2250 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
2560 * Offset of MAC address inside EEPROM.
2790 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2804 bus_write_4(sc->bge_res, reg, val)
2807 bus_read_4(sc->bge_res, reg)
2816 bus_write_4(sc->bge_res2, reg, val)
2819 bus_read_4(sc->bge_res2, reg)
2839 /* Maximum DMA address for controllers that have 40bit DMA address bug. */
2882 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
3048 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
3049 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
3050 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
3051 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
3052 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)