Lines Matching defs:sc
363 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
364 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
365 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
366 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
367 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
368 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
369 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
370 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
393 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
546 bge_has_eaddr(struct bge_softc *sc)
552 bge_readmem_ind(struct bge_softc *sc, int off)
557 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
561 dev = sc->bge_dev;
570 bge_writemem_ind(struct bge_softc *sc, int off, int val)
574 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
578 dev = sc->bge_dev;
587 bge_readreg_ind(struct bge_softc *sc, int off)
591 dev = sc->bge_dev;
599 bge_writereg_ind(struct bge_softc *sc, int off, int val)
603 dev = sc->bge_dev;
610 bge_writemem_direct(struct bge_softc *sc, int off, int val)
612 CSR_WRITE_4(sc, off, val);
616 bge_writembx(struct bge_softc *sc, int off, int val)
618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
621 CSR_WRITE_4(sc, off, val);
622 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
623 CSR_READ_4(sc, off);
630 bge_ape_lock_init(struct bge_softc *sc)
635 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
650 if (sc->bge_func_addr == 0)
653 bit = (1 << sc->bge_func_addr);
655 APE_WRITE_4(sc, regbase + 4 * i, bit);
659 switch (sc->bge_func_addr) {
661 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
664 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
667 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
670 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
673 device_printf(sc->bge_dev,
682 bge_ape_read_fw_ver(struct bge_softc *sc)
688 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
690 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
695 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
697 device_printf(sc->bge_dev, "APE signature found "
702 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
705 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
706 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
708 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
711 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
717 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
726 bge_ape_lock(struct bge_softc *sc, int locknum)
731 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
735 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
748 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
750 if (sc->bge_func_addr == 0)
753 bit = (1 << sc->bge_func_addr);
757 if (sc->bge_func_addr == 0)
760 bit = (1 << sc->bge_func_addr);
764 if (sc->bge_func_addr == 0)
767 bit = (1 << sc->bge_func_addr);
781 APE_WRITE_4(sc, req + off, bit);
785 status = APE_READ_4(sc, gnt + off);
793 device_printf(sc->bge_dev, "APE lock %d request failed! "
798 APE_WRITE_4(sc, gnt + off, bit);
806 bge_ape_unlock(struct bge_softc *sc, int locknum)
811 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
814 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
823 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
825 if (sc->bge_func_addr == 0)
828 bit = (1 << sc->bge_func_addr);
831 if (sc->bge_func_addr == 0)
834 bit = (1 << sc->bge_func_addr);
837 if (sc->bge_func_addr == 0)
840 bit = (1 << sc->bge_func_addr);
852 APE_WRITE_4(sc, gnt + off, bit);
859 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
865 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
870 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
872 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
874 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
876 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
877 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
880 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
884 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
889 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
893 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
899 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
901 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
903 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
904 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
906 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
908 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
912 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
914 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
916 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
918 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
923 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
934 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
957 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
963 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
965 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
973 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
974 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
976 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
977 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
980 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
987 if_printf(sc->bge_ifp, "nvram read timed out\n");
992 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
997 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1000 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1001 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1010 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1015 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1019 err = bge_nvram_getbyte(sc, off + i, &byte);
1035 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1044 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1047 CSR_WRITE_4(sc, BGE_EE_ADDR,
1052 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1057 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1062 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1067 byte = CSR_READ_4(sc, BGE_EE_DATA);
1078 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1084 error = bge_eeprom_getbyte(sc, off + i, &byte);
1096 struct bge_softc *sc;
1100 sc = device_get_softc(dev);
1102 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1106 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1107 CSR_WRITE_4(sc, BGE_MI_MODE,
1108 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1112 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1118 val = CSR_READ_4(sc, BGE_MI_COMM);
1121 val = CSR_READ_4(sc, BGE_MI_COMM);
1127 device_printf(sc->bge_dev,
1134 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1135 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1139 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1150 struct bge_softc *sc;
1153 sc = device_get_softc(dev);
1155 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1159 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1163 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1164 CSR_WRITE_4(sc, BGE_MI_MODE,
1165 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1169 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1174 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1176 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1182 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1183 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1187 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1190 device_printf(sc->bge_dev,
1200 struct bge_softc *sc;
1204 sc = device_get_softc(dev);
1205 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1207 mii = device_get_softc(sc->bge_miibus);
1214 sc->bge_link = 1;
1219 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1220 sc->bge_link = 1;
1222 sc->bge_link = 0;
1225 sc->bge_link = 0;
1229 sc->bge_link = 0;
1230 if (sc->bge_link == 0)
1240 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1242 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1243 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1262 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1264 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1265 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1272 bge_newbuf_std(struct bge_softc *sc, int i)
1280 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1281 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1293 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1296 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1297 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1302 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1303 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1304 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1305 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1306 sc->bge_cdata.bge_rx_std_dmamap[i]);
1308 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1309 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1310 sc->bge_cdata.bge_rx_std_sparemap = map;
1311 sc->bge_cdata.bge_rx_std_chain[i] = m;
1312 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1313 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1320 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1321 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1331 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1348 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1351 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1352 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1358 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1359 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1360 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1361 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1362 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1364 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1365 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1366 sc->bge_cdata.bge_rx_jumbo_sparemap;
1367 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1368 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1369 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1370 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1371 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1372 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1377 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1386 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1391 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1396 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1401 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1407 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1408 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1414 bge_init_rx_ring_std(struct bge_softc *sc)
1418 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1419 sc->bge_std = 0;
1421 if ((error = bge_newbuf_std(sc, i)) != 0)
1423 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1426 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1427 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1429 sc->bge_std = 0;
1430 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1436 bge_free_rx_ring_std(struct bge_softc *sc)
1441 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1442 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1443 sc->bge_cdata.bge_rx_std_dmamap[i],
1445 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1446 sc->bge_cdata.bge_rx_std_dmamap[i]);
1447 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1448 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1450 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1456 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1461 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1462 sc->bge_jumbo = 0;
1464 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1466 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1469 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1470 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1472 sc->bge_jumbo = 0;
1475 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1478 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1480 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1486 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1491 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1492 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1493 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1495 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1496 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1497 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1498 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1500 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1506 bge_free_tx_ring(struct bge_softc *sc)
1510 if (sc->bge_ldata.bge_tx_ring == NULL)
1514 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1515 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1516 sc->bge_cdata.bge_tx_dmamap[i],
1518 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1519 sc->bge_cdata.bge_tx_dmamap[i]);
1520 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1521 sc->bge_cdata.bge_tx_chain[i] = NULL;
1523 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1529 bge_init_tx_ring(struct bge_softc *sc)
1531 sc->bge_txcnt = 0;
1532 sc->bge_tx_saved_considx = 0;
1534 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1535 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1536 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1539 sc->bge_tx_prodidx = 0;
1540 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1543 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1544 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1547 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1549 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1550 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1556 bge_setpromisc(struct bge_softc *sc)
1560 BGE_LOCK_ASSERT(sc);
1562 ifp = sc->bge_ifp;
1566 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1568 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1584 bge_setmulti(struct bge_softc *sc)
1590 BGE_LOCK_ASSERT(sc);
1592 ifp = sc->bge_ifp;
1596 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1602 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1607 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1611 bge_setvlan(struct bge_softc *sc)
1615 BGE_LOCK_ASSERT(sc);
1617 ifp = sc->bge_ifp;
1621 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1623 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1627 bge_sig_pre_reset(struct bge_softc *sc, int type)
1633 if (sc->bge_asf_mode)
1634 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1636 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1639 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1643 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1647 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1654 bge_ape_driver_state_change(sc, type);
1658 bge_sig_post_reset(struct bge_softc *sc, int type)
1661 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1664 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1669 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1675 bge_ape_driver_state_change(sc, type);
1679 bge_sig_legacy(struct bge_softc *sc, int type)
1682 if (sc->bge_asf_mode) {
1685 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1689 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1697 bge_stop_fw(struct bge_softc *sc)
1701 if (sc->bge_asf_mode) {
1702 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1703 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1704 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1707 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1716 bge_dma_swap_options(struct bge_softc *sc)
1732 bge_chipinit(struct bge_softc *sc)
1740 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1742 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1750 BGE_MEMWIN_WRITE(sc, i, 0);
1754 BGE_MEMWIN_WRITE(sc, i, 0);
1756 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1762 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1764 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1767 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1768 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1774 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1775 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1776 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1786 if (sc->bge_flags & BGE_FLAG_PCIE) {
1787 if (sc->bge_mps >= 256)
1791 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1792 if (BGE_IS_5714_FAMILY(sc)) {
1796 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1799 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1808 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1818 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1819 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1823 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1836 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1837 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1840 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1841 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1844 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1845 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1847 if (BGE_IS_5717_PLUS(sc)) {
1849 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1856 if (!BGE_IS_57765_PLUS(sc) &&
1857 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1858 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1861 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1866 mode_ctl = bge_dma_swap_options(sc);
1867 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1868 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1870 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1885 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1891 if (sc->bge_asf_mode & ASF_STACKUP)
1894 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1900 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1903 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1906 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1910 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1911 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1919 bge_blockinit(struct bge_softc *sc)
1934 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1938 if (!(BGE_IS_5705_PLUS(sc))) {
1940 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1941 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1942 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1944 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1947 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1949 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1953 if (BGE_IS_5717_PLUS(sc)) {
1954 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1955 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1956 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1960 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1962 } else if (!BGE_IS_5705_PLUS(sc)) {
1963 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1964 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1965 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1966 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1967 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1968 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1969 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1972 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1977 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1978 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1988 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1990 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1995 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2000 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2005 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2006 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2011 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2016 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2052 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2054 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2056 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2057 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2058 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2059 if (BGE_IS_5717_PLUS(sc)) {
2068 } else if (BGE_IS_5705_PLUS(sc)) {
2087 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2088 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2089 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2094 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2095 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2096 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2097 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2100 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2109 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2110 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2113 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2115 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2116 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2117 sc->bge_cdata.bge_rx_jumbo_ring_map,
2121 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2122 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2123 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2127 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2129 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2132 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2134 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2136 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2140 if (BGE_IS_5700_FAMILY(sc)) {
2141 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2144 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2147 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2151 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2152 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2153 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2154 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2155 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2156 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2175 if (BGE_IS_5705_PLUS(sc))
2179 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2180 if (BGE_IS_JUMBO_CAPABLE(sc))
2181 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2183 if (BGE_IS_5717_PLUS(sc)) {
2184 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2185 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2193 if (!BGE_IS_5705_PLUS(sc))
2196 else if (BGE_IS_57765_PLUS(sc) ||
2197 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2199 else if (BGE_IS_5717_PLUS(sc))
2205 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2207 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2213 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2214 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2215 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2216 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2217 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2218 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2219 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2221 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2223 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2231 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2232 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2233 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2236 } else if (!BGE_IS_5705_PLUS(sc))
2238 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2239 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2240 BGE_IS_57765_PLUS(sc))
2247 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2248 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2249 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2251 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2252 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2263 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2264 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2265 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2266 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2267 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2268 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2270 lladdr = if_getlladdr(sc->bge_ifp);
2272 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2280 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2281 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2282 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2284 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2290 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2296 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2299 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2300 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2303 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2308 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2313 device_printf(sc->bge_dev,
2319 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2320 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2321 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2322 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2323 if (!(BGE_IS_5705_PLUS(sc))) {
2324 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2325 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2327 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2328 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2331 if (!(BGE_IS_5705_PLUS(sc))) {
2332 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2333 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2334 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2335 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2336 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2337 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2338 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2342 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2343 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2344 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2345 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2348 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2349 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2351 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2354 bzero(sc->bge_ldata.bge_status_block, 32);
2356 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2357 sc->bge_cdata.bge_status_map,
2361 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2364 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2368 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2371 if (!(BGE_IS_5705_PLUS(sc)))
2372 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2380 if (sc->bge_flags & BGE_FLAG_TBI)
2382 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2388 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2391 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2395 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2399 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2401 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2406 if (!(BGE_IS_5705_PLUS(sc)))
2407 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2412 if (BGE_IS_5755_PLUS(sc))
2416 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2420 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2426 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2429 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2430 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2431 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2435 if (sc->bge_flags & BGE_FLAG_PCIE)
2437 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2439 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2441 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2445 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2446 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2447 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2456 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2457 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2458 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2459 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2460 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2461 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2465 dmactl = CSR_READ_4(sc, rdmareg);
2470 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2471 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2484 CSR_WRITE_4(sc, rdmareg, dmactl |
2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2489 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2490 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2493 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2498 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2499 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2502 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2503 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2504 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2509 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2512 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2514 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2521 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2522 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2526 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2531 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2534 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2537 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2540 if (!(BGE_IS_5705_PLUS(sc)))
2541 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2544 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2548 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2550 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2553 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2554 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2557 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2560 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2563 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2565 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2566 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2570 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2573 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2579 if (sc->bge_flags & BGE_FLAG_TBI) {
2580 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2582 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2583 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2586 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2587 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2588 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2599 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2604 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2705 struct bge_softc *sc;
2711 sc = device_get_softc(dev);
2712 sc->bge_dev = dev;
2719 if (bge_has_eaddr(sc) &&
2740 bge_dma_free(struct bge_softc *sc)
2746 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2747 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2748 sc->bge_cdata.bge_rx_std_dmamap[i]);
2750 if (sc->bge_cdata.bge_rx_std_sparemap)
2751 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2752 sc->bge_cdata.bge_rx_std_sparemap);
2756 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2757 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2758 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2760 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2761 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2762 sc->bge_cdata.bge_rx_jumbo_sparemap);
2766 if (sc->bge_cdata.bge_tx_dmamap[i])
2767 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2768 sc->bge_cdata.bge_tx_dmamap[i]);
2771 if (sc->bge_cdata.bge_rx_mtag)
2772 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2773 if (sc->bge_cdata.bge_mtag_jumbo)
2774 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2775 if (sc->bge_cdata.bge_tx_mtag)
2776 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2779 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2780 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2781 sc->bge_cdata.bge_rx_std_ring_map);
2782 if (sc->bge_ldata.bge_rx_std_ring)
2783 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2784 sc->bge_ldata.bge_rx_std_ring,
2785 sc->bge_cdata.bge_rx_std_ring_map);
2787 if (sc->bge_cdata.bge_rx_std_ring_tag)
2788 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2791 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2792 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2793 sc->bge_cdata.bge_rx_jumbo_ring_map);
2795 if (sc->bge_ldata.bge_rx_jumbo_ring)
2796 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2797 sc->bge_ldata.bge_rx_jumbo_ring,
2798 sc->bge_cdata.bge_rx_jumbo_ring_map);
2800 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2801 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2804 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2805 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2806 sc->bge_cdata.bge_rx_return_ring_map);
2808 if (sc->bge_ldata.bge_rx_return_ring)
2809 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2810 sc->bge_ldata.bge_rx_return_ring,
2811 sc->bge_cdata.bge_rx_return_ring_map);
2813 if (sc->bge_cdata.bge_rx_return_ring_tag)
2814 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2817 if (sc->bge_ldata.bge_tx_ring_paddr)
2818 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2819 sc->bge_cdata.bge_tx_ring_map);
2821 if (sc->bge_ldata.bge_tx_ring)
2822 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2823 sc->bge_ldata.bge_tx_ring,
2824 sc->bge_cdata.bge_tx_ring_map);
2826 if (sc->bge_cdata.bge_tx_ring_tag)
2827 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2830 if (sc->bge_ldata.bge_status_block_paddr)
2831 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2832 sc->bge_cdata.bge_status_map);
2834 if (sc->bge_ldata.bge_status_block)
2835 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2836 sc->bge_ldata.bge_status_block,
2837 sc->bge_cdata.bge_status_map);
2839 if (sc->bge_cdata.bge_status_tag)
2840 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2843 if (sc->bge_ldata.bge_stats_paddr)
2844 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2845 sc->bge_cdata.bge_stats_map);
2847 if (sc->bge_ldata.bge_stats)
2848 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2849 sc->bge_ldata.bge_stats,
2850 sc->bge_cdata.bge_stats_map);
2852 if (sc->bge_cdata.bge_stats_tag)
2853 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2855 if (sc->bge_cdata.bge_buffer_tag)
2856 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2859 if (sc->bge_cdata.bge_parent_tag)
2860 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2864 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2875 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2879 device_printf(sc->bge_dev,
2887 device_printf(sc->bge_dev,
2896 device_printf(sc->bge_dev,
2902 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2912 device_printf(sc->bge_dev, "4GB boundary crossed, "
2924 bge_dma_alloc(struct bge_softc *sc)
2931 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2936 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2939 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2941 device_printf(sc->bge_dev,
2947 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2948 &sc->bge_cdata.bge_rx_std_ring_tag,
2949 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2950 &sc->bge_cdata.bge_rx_std_ring_map,
2951 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2956 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2957 &sc->bge_cdata.bge_rx_return_ring_tag,
2958 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2959 &sc->bge_cdata.bge_rx_return_ring_map,
2960 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2965 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2966 &sc->bge_cdata.bge_tx_ring_tag,
2967 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2968 &sc->bge_cdata.bge_tx_ring_map,
2969 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2980 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2981 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2985 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2986 &sc->bge_cdata.bge_status_tag,
2987 (uint8_t **)&sc->bge_ldata.bge_status_block,
2988 &sc->bge_cdata.bge_status_map,
2989 &sc->bge_ldata.bge_status_block_paddr, "status block");
2994 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2995 &sc->bge_cdata.bge_stats_tag,
2996 (uint8_t **)&sc->bge_ldata.bge_stats,
2997 &sc->bge_cdata.bge_stats_map,
2998 &sc->bge_ldata.bge_stats_paddr, "statistics block");
3003 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3004 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3005 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3006 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3007 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3008 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3015 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3024 if (sc->bge_pcixcap != 0)
3027 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3030 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3032 device_printf(sc->bge_dev,
3037 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3044 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3047 &sc->bge_cdata.bge_tx_mtag);
3050 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3055 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3059 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3061 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3064 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3069 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3070 &sc->bge_cdata.bge_rx_std_sparemap);
3072 device_printf(sc->bge_dev,
3077 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3078 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3080 device_printf(sc->bge_dev,
3088 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3089 &sc->bge_cdata.bge_tx_dmamap[i]);
3091 device_printf(sc->bge_dev,
3098 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3099 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3102 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3104 device_printf(sc->bge_dev,
3109 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3110 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3112 device_printf(sc->bge_dev,
3117 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3118 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3120 device_printf(sc->bge_dev,
3134 bge_has_multiple_ports(struct bge_softc *sc)
3136 device_t dev = sc->bge_dev;
3153 bge_can_use_msi(struct bge_softc *sc)
3157 if (sc->bge_msi == 0)
3164 switch (sc->bge_asicrev) {
3171 if (bge_has_multiple_ports(sc))
3175 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3176 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3184 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3188 if (BGE_IS_575X_PLUS(sc))
3195 bge_mbox_reorder(struct bge_softc *sc)
3211 dev = sc->bge_dev;
3225 device_printf(sc->bge_dev,
3236 bge_devinfo(struct bge_softc *sc)
3240 device_printf(sc->bge_dev,
3242 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3243 if (sc->bge_flags & BGE_FLAG_PCIE)
3245 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3247 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3251 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3272 if (sc->bge_pcixcap != 0)
3276 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3292 struct bge_softc *sc;
3297 sc = device_get_softc(dev);
3298 sc->bge_dev = dev;
3300 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3301 NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3302 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3310 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3313 if (sc->bge_res == NULL) {
3314 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3320 sc->bge_func_addr = pci_get_function(dev);
3321 sc->bge_chipid = bge_chipid(dev);
3322 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3323 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3326 sc->bge_phy_addr = 1;
3349 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3350 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3351 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3352 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3353 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3355 sc->bge_phy_addr = sc->bge_func_addr + 8;
3357 sc->bge_phy_addr = sc->bge_func_addr + 1;
3359 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3361 sc->bge_phy_addr = sc->bge_func_addr + 8;
3363 sc->bge_phy_addr = sc->bge_func_addr + 1;
3367 if (bge_has_eaddr(sc))
3368 sc->bge_flags |= BGE_FLAG_EADDR;
3371 switch (sc->bge_asicrev) {
3375 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3380 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3383 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3384 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3389 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3390 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3391 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3393 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3403 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3410 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3415 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3420 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3423 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3428 switch (sc->bge_asicrev) {
3434 sc->bge_flags |= BGE_FLAG_APE;
3439 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3441 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3443 if (sc->bge_res2 == NULL) {
3444 device_printf (sc->bge_dev,
3457 bge_ape_lock_init(sc);
3458 bge_ape_read_fw_ver(sc);
3462 bge_add_sysctls(sc);
3465 if (BGE_IS_5717_PLUS(sc) ||
3466 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3467 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3468 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3469 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3470 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3471 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3472 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3474 sc->bge_mi_mode = BGE_MIMODE_BASE;
3476 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3477 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3486 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3489 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3490 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3498 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3499 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3501 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3502 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3505 sc->bge_flags |= BGE_FLAG_5788;
3509 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3511 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3523 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3526 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3541 if (BGE_IS_5717_PLUS(sc)) {
3543 sc->bge_flags |= BGE_FLAG_TSO3;
3544 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3545 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3547 sc->bge_flags &= ~BGE_FLAG_TSO3;
3549 } else if (BGE_IS_5755_PLUS(sc)) {
3558 sc->bge_flags |= BGE_FLAG_TSO;
3569 sc->bge_flags |= BGE_FLAG_PCIE;
3570 sc->bge_expcap = reg;
3572 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3574 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3575 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3576 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3577 sc->bge_expmrq = 2048;
3579 sc->bge_expmrq = 4096;
3580 pci_set_max_read_req(dev, sc->bge_expmrq);
3587 sc->bge_pcixcap = reg;
3590 sc->bge_flags |= BGE_FLAG_PCIX;
3598 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3599 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3608 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3609 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3616 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3617 sc->bge_msicap = reg;
3619 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3621 sc->bge_flags |= BGE_FLAG_MSI;
3631 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3632 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3635 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3638 if (sc->bge_irq == NULL) {
3639 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3644 bge_devinfo(sc);
3646 sc->bge_asf_mode = 0;
3648 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3649 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3651 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3653 sc->bge_asf_mode |= ASF_ENABLE;
3654 sc->bge_asf_mode |= ASF_STACKUP;
3655 if (BGE_IS_575X_PLUS(sc))
3656 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3661 bge_stop_fw(sc);
3662 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3663 if (bge_reset(sc)) {
3664 device_printf(sc->bge_dev, "chip reset failed\n");
3669 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3670 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3672 if (bge_chipinit(sc)) {
3673 device_printf(sc->bge_dev, "chip initialization failed\n");
3678 error = bge_get_eaddr(sc, eaddr);
3680 device_printf(sc->bge_dev,
3687 if (BGE_IS_5717_PLUS(sc))
3688 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3689 else if (BGE_IS_5705_PLUS(sc))
3690 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3692 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3694 if (bge_dma_alloc(sc)) {
3695 device_printf(sc->bge_dev,
3702 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3703 sc->bge_rx_coal_ticks = 150;
3704 sc->bge_tx_coal_ticks = 150;
3705 sc->bge_rx_max_coal_bds = 10;
3706 sc->bge_tx_max_coal_bds = 10;
3709 sc->bge_csum_features = BGE_CSUM_FEATURES;
3710 if (sc->bge_forced_udpcsum != 0)
3711 sc->bge_csum_features |= CSUM_UDP;
3714 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3715 if_setsoftc(ifp, sc);
3724 if_sethwassist(ifp, sc->bge_csum_features);
3727 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3743 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3758 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3759 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3760 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3761 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3762 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3764 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3774 if (BGE_IS_5705_PLUS(sc)) {
3775 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3776 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3778 sc->bge_flags |= BGE_FLAG_TBI;
3782 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3783 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3784 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3785 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3786 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3787 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3788 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3789 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3791 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3792 if ((BGE_IS_5705_PLUS(sc)) &&
3793 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3794 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3795 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3796 !BGE_IS_5717_PLUS(sc)) {
3797 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3798 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3799 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3800 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3803 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3805 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3807 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3814 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3815 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3816 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3817 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3818 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3820 if (sc->bge_flags & BGE_FLAG_TBI) {
3821 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3823 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3824 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3826 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3827 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3828 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3838 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3840 bge_asf_driver_up(sc);
3842 error = mii_attach(dev, &sc->bge_miibus, ifp,
3844 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3848 device_printf(sc->bge_dev, "Try again\n");
3849 bge_miibus_writereg(sc->bge_dev,
3850 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3853 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3860 if (sc->bge_asf_mode & ASF_STACKUP)
3861 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3872 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3873 sc->bge_flags & BGE_FLAG_PCIX)
3874 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3887 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3889 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3891 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3892 taskqueue_thread_enqueue, &sc->bge_tq);
3893 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3894 "%s taskq", device_get_nameunit(sc->bge_dev));
3900 error = bus_setup_intr(dev, sc->bge_irq,
3901 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3902 &sc->bge_intrhand);
3904 error = bus_setup_intr(dev, sc->bge_irq,
3905 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3906 &sc->bge_intrhand);
3910 device_printf(sc->bge_dev, "couldn't set up irq\n");
3926 struct bge_softc *sc;
3929 sc = device_get_softc(dev);
3930 ifp = sc->bge_ifp;
3939 BGE_LOCK(sc);
3940 bge_stop(sc);
3941 BGE_UNLOCK(sc);
3942 callout_drain(&sc->bge_stat_ch);
3945 if (sc->bge_tq)
3946 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3948 if (sc->bge_flags & BGE_FLAG_TBI)
3949 ifmedia_removeall(&sc->bge_ifmedia);
3950 else if (sc->bge_miibus != NULL) {
3954 bge_release_resources(sc);
3960 bge_release_resources(struct bge_softc *sc)
3964 dev = sc->bge_dev;
3966 if (sc->bge_tq != NULL)
3967 taskqueue_free(sc->bge_tq);
3969 if (sc->bge_intrhand != NULL)
3970 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3972 if (sc->bge_irq != NULL) {
3974 rman_get_rid(sc->bge_irq), sc->bge_irq);
3978 if (sc->bge_res != NULL)
3980 rman_get_rid(sc->bge_res), sc->bge_res);
3982 if (sc->bge_res2 != NULL)
3984 rman_get_rid(sc->bge_res2), sc->bge_res2);
3986 if (sc->bge_ifp != NULL)
3987 if_free(sc->bge_ifp);
3989 bge_dma_free(sc);
3991 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3992 BGE_LOCK_DESTROY(sc);
3996 bge_reset(struct bge_softc *sc)
4004 dev = sc->bge_dev;
4007 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4009 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4011 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4012 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4013 if (sc->bge_flags & BGE_FLAG_PCIE)
4020 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4021 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4022 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4024 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4035 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4046 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4047 BGE_IS_5755_PLUS(sc)) {
4050 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4058 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4063 if (sc->bge_flags & BGE_FLAG_PCIE) {
4064 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4065 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4066 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4067 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4069 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4071 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4076 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4077 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4078 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4080 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4081 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4089 if (BGE_IS_5705_PLUS(sc) &&
4090 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4094 write_op(sc, BGE_MISC_CFG, reset);
4096 if (sc->bge_flags & BGE_FLAG_PCIE)
4102 if (sc->bge_flags & BGE_FLAG_PCIE) {
4103 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4109 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4113 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4115 pci_set_max_read_req(dev, sc->bge_expmrq);
4117 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4128 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4129 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4131 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4143 if (sc->bge_flags & BGE_FLAG_PCIX) {
4145 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4147 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4150 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4155 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4159 if (BGE_IS_5714_FAMILY(sc)) {
4161 if (sc->bge_flags & BGE_FLAG_MSI) {
4163 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4165 sc->bge_msicap + PCIR_MSI_CTRL,
4167 val = CSR_READ_4(sc, BGE_MSI_MODE);
4168 CSR_WRITE_4(sc, BGE_MSI_MODE,
4171 val = CSR_READ_4(sc, BGE_MARB_MODE);
4172 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4174 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4177 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4179 val = CSR_READ_4(sc, BGE_MAC_MODE);
4181 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4184 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4186 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4188 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4206 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4211 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4216 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4225 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4226 sc->bge_flags & BGE_FLAG_TBI) {
4227 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4229 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4233 if (sc->bge_flags & BGE_FLAG_PCIE &&
4234 !BGE_IS_5717_PLUS(sc) &&
4235 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4236 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4238 val = CSR_READ_4(sc, 0x7C00);
4239 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4242 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4243 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4250 bge_rxreuse_std(struct bge_softc *sc, int i)
4254 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4256 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4258 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4262 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4266 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4268 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4269 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4270 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4271 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4273 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4286 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4292 rx_cons = sc->bge_rx_saved_considx;
4298 ifp = sc->bge_ifp;
4300 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4301 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4302 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4303 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4304 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4307 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4308 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4319 if (sc->rxcycles <= 0)
4321 sc->rxcycles--;
4325 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4328 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4338 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4340 bge_rxreuse_jumbo(sc, rxidx);
4343 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4344 bge_rxreuse_jumbo(sc, rxidx);
4348 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4351 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4353 bge_rxreuse_std(sc, rxidx);
4356 if (bge_newbuf_std(sc, rxidx) != 0) {
4357 bge_rxreuse_std(sc, rxidx);
4361 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4370 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4380 bge_rxcsum(sc, cur_rx, m);
4392 BGE_UNLOCK(sc);
4394 BGE_LOCK(sc);
4403 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4404 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4406 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4407 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4410 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4411 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4413 sc->bge_rx_saved_considx = rx_cons;
4414 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4416 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4419 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4426 if (BGE_IS_5705_PLUS(sc))
4427 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4433 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4436 if (BGE_IS_5717_PLUS(sc)) {
4468 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4473 BGE_LOCK_ASSERT(sc);
4476 if (sc->bge_tx_saved_considx == tx_cons)
4479 ifp = sc->bge_ifp;
4481 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4482 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4487 while (sc->bge_tx_saved_considx != tx_cons) {
4490 idx = sc->bge_tx_saved_considx;
4491 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4494 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4495 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4496 sc->bge_cdata.bge_tx_dmamap[idx],
4498 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4499 sc->bge_cdata.bge_tx_dmamap[idx]);
4500 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4501 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4503 sc->bge_txcnt--;
4504 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4508 if (sc->bge_txcnt == 0)
4509 sc->bge_timer = 0;
4516 struct bge_softc *sc = if_getsoftc(ifp);
4521 BGE_LOCK(sc);
4523 BGE_UNLOCK(sc);
4527 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4528 sc->bge_cdata.bge_status_map,
4531 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4532 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4534 statusword = sc->bge_ldata.bge_status_block->bge_status;
4536 sc->bge_ldata.bge_status_block->bge_status = 0;
4538 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4539 sc->bge_cdata.bge_status_map,
4544 sc->bge_link_evt++;
4547 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4548 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4549 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4550 bge_link_upd(sc);
4552 sc->rxcycles = count;
4553 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4555 BGE_UNLOCK(sc);
4558 bge_txeof(sc, tx_cons);
4562 BGE_UNLOCK(sc);
4570 struct bge_softc *sc;
4572 sc = (struct bge_softc *)arg;
4577 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4584 struct bge_softc *sc;
4589 sc = (struct bge_softc *)arg;
4590 ifp = sc->bge_ifp;
4592 BGE_LOCK(sc);
4594 BGE_UNLOCK(sc);
4599 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4600 sc->bge_cdata.bge_status_map,
4604 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4605 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4606 status = sc->bge_ldata.bge_status_block->bge_status;
4607 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4609 sc->bge_ldata.bge_status_block->bge_status = 0;
4610 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4611 sc->bge_cdata.bge_status_map,
4613 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4617 bge_link_upd(sc);
4620 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4623 sc->bge_rx_saved_considx != rx_prod) {
4625 BGE_UNLOCK(sc);
4626 bge_rxeof(sc, rx_prod, 0);
4627 BGE_LOCK(sc);
4631 bge_txeof(sc, tx_cons);
4635 BGE_UNLOCK(sc);
4641 struct bge_softc *sc;
4646 sc = xsc;
4648 BGE_LOCK(sc);
4650 ifp = sc->bge_ifp;
4654 BGE_UNLOCK(sc);
4679 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4684 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4687 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4688 sc->bge_cdata.bge_status_map,
4690 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4691 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4692 sc->bge_ldata.bge_status_block->bge_status = 0;
4693 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4694 sc->bge_cdata.bge_status_map,
4697 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4698 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4699 statusword || sc->bge_link_evt)
4700 bge_link_upd(sc);
4704 bge_rxeof(sc, rx_prod, 1);
4709 bge_txeof(sc, tx_cons);
4716 BGE_UNLOCK(sc);
4720 bge_asf_driver_up(struct bge_softc *sc)
4722 if (sc->bge_asf_mode & ASF_STACKUP) {
4724 if (sc->bge_asf_count)
4725 sc->bge_asf_count --;
4727 sc->bge_asf_count = 2;
4728 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4730 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4731 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4733 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4734 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4743 struct bge_softc *sc = xsc;
4746 BGE_LOCK_ASSERT(sc);
4749 if (callout_pending(&sc->bge_stat_ch) ||
4750 !callout_active(&sc->bge_stat_ch))
4753 if (BGE_IS_5705_PLUS(sc))
4754 bge_stats_update_regs(sc);
4756 bge_stats_update(sc);
4760 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4761 mii = device_get_softc(sc->bge_miibus);
4767 if (!sc->bge_link)
4777 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4780 sc->bge_link_evt++;
4781 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4782 sc->bge_flags & BGE_FLAG_5788)
4783 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4785 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4789 bge_asf_driver_up(sc);
4790 bge_watchdog(sc);
4792 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4796 bge_stats_update_regs(struct bge_softc *sc)
4801 stats = &sc->bge_mac_stats;
4804 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4806 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4808 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4810 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4812 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4814 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4816 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4818 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4820 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4822 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4824 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4826 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4828 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4831 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4833 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4835 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4837 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4839 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4841 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4843 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4845 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4847 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4860 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4862 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4864 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4866 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4886 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4887 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4888 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4890 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4892 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4894 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4896 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4904 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4905 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4909 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4910 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4916 bge_stats_clear_regs(struct bge_softc *sc)
4919 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4920 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4921 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4922 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4923 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4924 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4925 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4926 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4927 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4928 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4929 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4930 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4931 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4933 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4934 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4935 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4936 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4937 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4938 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4939 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4940 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4941 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4942 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4943 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4944 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4945 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4946 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4948 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4949 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4950 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4951 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4952 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4953 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4954 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4958 bge_stats_update(struct bge_softc *sc)
4964 ifp = sc->bge_ifp;
4968 #define READ_STAT(sc, stats, stat) \
4969 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4971 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4972 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4973 sc->bge_tx_collisions = cnt;
4975 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4976 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4977 sc->bge_rx_nobds = cnt;
4978 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4979 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
4980 sc->bge_rx_inerrs = cnt;
4981 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4982 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
4983 sc->bge_rx_discards = cnt;
4985 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4986 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
4987 sc->bge_tx_discards = cnt;
5071 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5119 if (sc->bge_flags & BGE_FLAG_TSO3) {
5147 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5160 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5168 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5173 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5188 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5191 if (sc->bge_forced_collapse > 0 &&
5192 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5198 if (sc->bge_forced_collapse == 1)
5202 sc->bge_forced_collapse);
5209 map = sc->bge_cdata.bge_tx_dmamap[idx];
5210 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5220 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5231 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5232 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5236 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5243 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5252 d = &sc->bge_ldata.bge_tx_ring[idx];
5267 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5269 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5276 d = &sc->bge_ldata.bge_tx_ring[idx];
5297 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5298 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5299 sc->bge_cdata.bge_tx_chain[idx] = m;
5300 sc->bge_txcnt += nsegs;
5315 struct bge_softc *sc;
5320 sc = if_getsoftc(ifp);
5321 BGE_LOCK_ASSERT(sc);
5323 if (!sc->bge_link ||
5328 prodidx = sc->bge_tx_prodidx;
5331 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5344 if (bge_encap(sc, &m_head, &prodidx)) {
5361 bge_start_tx(sc, prodidx);
5365 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5368 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5369 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5371 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5373 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5374 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5376 sc->bge_tx_prodidx = prodidx;
5379 sc->bge_timer = BGE_TX_TIMEOUT;
5389 struct bge_softc *sc;
5391 sc = if_getsoftc(ifp);
5392 BGE_LOCK(sc);
5394 BGE_UNLOCK(sc);
5398 bge_init_locked(struct bge_softc *sc)
5404 BGE_LOCK_ASSERT(sc);
5406 ifp = sc->bge_ifp;
5412 bge_stop(sc);
5414 bge_stop_fw(sc);
5415 bge_sig_pre_reset(sc, BGE_RESET_START);
5416 bge_reset(sc);
5417 bge_sig_legacy(sc, BGE_RESET_START);
5418 bge_sig_post_reset(sc, BGE_RESET_START);
5420 bge_chipinit(sc);
5426 if (bge_blockinit(sc)) {
5427 device_printf(sc->bge_dev, "initialization failure\n");
5431 ifp = sc->bge_ifp;
5434 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5439 m = (uint16_t *)if_getlladdr(sc->bge_ifp);
5440 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5441 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5444 bge_setpromisc(sc);
5447 bge_setmulti(sc);
5450 bge_setvlan(sc);
5453 if (sc->bge_forced_udpcsum == 0)
5454 sc->bge_csum_features &= ~CSUM_UDP;
5456 sc->bge_csum_features |= CSUM_UDP;
5460 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5464 if (bge_init_rx_ring_std(sc) != 0) {
5465 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5466 bge_stop(sc);
5475 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5479 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5484 device_printf (sc->bge_dev,
5489 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5492 if (bge_init_rx_ring_jumbo(sc) != 0) {
5493 device_printf(sc->bge_dev,
5495 bge_stop(sc);
5501 sc->bge_rx_saved_considx = 0;
5504 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5507 bge_init_tx_ring(sc);
5510 mode = CSR_READ_4(sc, BGE_TX_MODE);
5511 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5513 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5514 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5516 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5520 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5524 mode = CSR_READ_4(sc, BGE_RX_MODE);
5525 if (BGE_IS_5755_PLUS(sc))
5527 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5529 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5538 if (BGE_IS_57765_PLUS(sc))
5539 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5541 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5544 if (BGE_IS_5705_PLUS(sc))
5545 bge_stats_clear_regs(sc);
5548 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5553 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5555 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5561 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5562 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5563 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5571 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5577 struct bge_softc *sc = xsc;
5579 BGE_LOCK(sc);
5580 bge_init_locked(sc);
5581 BGE_UNLOCK(sc);
5590 struct bge_softc *sc = if_getsoftc(ifp);
5593 BGE_LOCK(sc);
5595 BGE_UNLOCK(sc);
5603 struct bge_softc *sc = if_getsoftc(ifp);
5608 BGE_LOCK_ASSERT(sc);
5610 ifm = &sc->bge_ifmedia;
5613 if (sc->bge_flags & BGE_FLAG_TBI) {
5623 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5625 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5627 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5628 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5632 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5635 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5641 BGE_CLRBIT(sc, BGE_MAC_MODE,
5644 BGE_SETBIT(sc, BGE_MAC_MODE,
5655 sc->bge_link_evt++;
5656 mii = device_get_softc(sc->bge_miibus);
5673 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5674 sc->bge_flags & BGE_FLAG_5788)
5675 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5677 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5688 struct bge_softc *sc = if_getsoftc(ifp);
5691 BGE_LOCK(sc);
5694 BGE_UNLOCK(sc);
5697 if (sc->bge_flags & BGE_FLAG_TBI) {
5700 if (CSR_READ_4(sc, BGE_MAC_STS) &
5705 BGE_UNLOCK(sc);
5709 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5713 BGE_UNLOCK(sc);
5717 mii = device_get_softc(sc->bge_miibus);
5722 BGE_UNLOCK(sc);
5728 struct bge_softc *sc = if_getsoftc(ifp);
5735 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5736 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5746 BGE_LOCK(sc);
5751 bge_init_locked(sc);
5754 BGE_UNLOCK(sc);
5757 BGE_LOCK(sc);
5768 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5770 bge_setpromisc(sc);
5772 bge_setmulti(sc);
5774 bge_init_locked(sc);
5777 bge_stop(sc);
5780 sc->bge_if_flags = if_getflags(ifp);
5781 BGE_UNLOCK(sc);
5787 BGE_LOCK(sc);
5788 bge_setmulti(sc);
5789 BGE_UNLOCK(sc);
5795 if (sc->bge_flags & BGE_FLAG_TBI) {
5797 &sc->bge_ifmedia, command);
5799 mii = device_get_softc(sc->bge_miibus);
5812 BGE_LOCK(sc);
5813 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5815 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5817 BGE_UNLOCK(sc);
5821 BGE_LOCK(sc);
5822 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5824 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5826 BGE_UNLOCK(sc);
5835 sc->bge_csum_features, 0);
5838 sc->bge_csum_features);
5857 bge_init(sc);
5868 BGE_LOCK(sc);
5869 bge_setvlan(sc);
5870 BGE_UNLOCK(sc);
5885 bge_watchdog(struct bge_softc *sc)
5890 BGE_LOCK_ASSERT(sc);
5892 if (sc->bge_timer == 0 || --sc->bge_timer)
5896 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5897 status = CSR_READ_4(sc, BGE_RX_STS);
5903 CSR_WRITE_4(sc, BGE_RX_STS, status);
5904 sc->bge_timer = BGE_TX_TIMEOUT;
5912 CSR_WRITE_4(sc, BGE_RX_STS, status);
5913 sc->bge_timer = BGE_TX_TIMEOUT;
5922 ifp = sc->bge_ifp;
5927 bge_init_locked(sc);
5933 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5937 BGE_CLRBIT(sc, reg, bit);
5940 if ((CSR_READ_4(sc, reg) & bit) == 0)
5951 bge_stop(struct bge_softc *sc)
5955 BGE_LOCK_ASSERT(sc);
5957 ifp = sc->bge_ifp;
5959 callout_stop(&sc->bge_stat_ch);
5962 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5963 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5968 bge_stop_fw(sc);
5969 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5974 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5975 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5976 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5977 if (BGE_IS_5700_FAMILY(sc))
5978 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5979 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5980 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5981 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5986 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5987 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5988 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5989 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5990 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5991 if (BGE_IS_5700_FAMILY(sc))
5992 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5993 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5999 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6000 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6001 if (BGE_IS_5700_FAMILY(sc))
6002 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6004 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6005 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6006 if (!(BGE_IS_5705_PLUS(sc))) {
6007 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6008 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6011 if (BGE_IS_5705_PLUS(sc))
6012 bge_stats_update_regs(sc);
6014 bge_reset(sc);
6015 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6016 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6021 if (sc->bge_asf_mode & ASF_STACKUP)
6022 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6024 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6027 bge_free_rx_ring_std(sc);
6030 if (BGE_IS_JUMBO_CAPABLE(sc))
6031 bge_free_rx_ring_jumbo(sc);
6034 bge_free_tx_ring(sc);
6036 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6039 if (bootverbose && sc->bge_link)
6040 if_printf(sc->bge_ifp, "link DOWN\n");
6041 sc->bge_link = 0;
6053 struct bge_softc *sc;
6055 sc = device_get_softc(dev);
6056 BGE_LOCK(sc);
6057 bge_stop(sc);
6058 BGE_UNLOCK(sc);
6066 struct bge_softc *sc;
6068 sc = device_get_softc(dev);
6069 BGE_LOCK(sc);
6070 bge_stop(sc);
6071 BGE_UNLOCK(sc);
6079 struct bge_softc *sc;
6082 sc = device_get_softc(dev);
6083 BGE_LOCK(sc);
6084 ifp = sc->bge_ifp;
6086 bge_init_locked(sc);
6090 BGE_UNLOCK(sc);
6096 bge_link_upd(struct bge_softc *sc)
6101 BGE_LOCK_ASSERT(sc);
6104 sc->bge_link_evt = 0;
6121 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6122 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6123 status = CSR_READ_4(sc, BGE_MAC_STS);
6125 mii = device_get_softc(sc->bge_miibus);
6127 if (!sc->bge_link &&
6130 sc->bge_link++;
6132 if_printf(sc->bge_ifp, "link UP\n");
6133 } else if (sc->bge_link &&
6136 sc->bge_link = 0;
6138 if_printf(sc->bge_ifp, "link DOWN\n");
6142 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6144 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6146 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6152 if (sc->bge_flags & BGE_FLAG_TBI) {
6153 status = CSR_READ_4(sc, BGE_MAC_STS);
6155 if (!sc->bge_link) {
6156 sc->bge_link++;
6157 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6158 BGE_CLRBIT(sc, BGE_MAC_MODE,
6162 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6164 if_printf(sc->bge_ifp, "link UP\n");
6165 if_link_state_change(sc->bge_ifp,
6168 } else if (sc->bge_link) {
6169 sc->bge_link = 0;
6171 if_printf(sc->bge_ifp, "link DOWN\n");
6172 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6174 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6180 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6182 if (link != sc->bge_link ||
6183 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6184 mii = device_get_softc(sc->bge_miibus);
6186 if (!sc->bge_link &&
6189 sc->bge_link++;
6191 if_printf(sc->bge_ifp, "link UP\n");
6192 } else if (sc->bge_link &&
6195 sc->bge_link = 0;
6197 if_printf(sc->bge_ifp, "link DOWN\n");
6205 mii = device_get_softc(sc->bge_miibus);
6207 bge_miibus_statchg(sc->bge_dev);
6211 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6217 bge_add_sysctls(struct bge_softc *sc)
6222 ctx = device_get_sysctl_ctx(sc->bge_dev);
6223 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6227 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6231 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6235 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6239 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6256 sc->bge_forced_collapse = 0;
6258 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6262 sc->bge_msi = 1;
6264 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6276 sc->bge_forced_udpcsum = 0;
6278 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6282 if (BGE_IS_5705_PLUS(sc))
6283 bge_add_sysctl_stats_regs(sc, ctx, children);
6285 bge_add_sysctl_stats(sc, ctx, children);
6288 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6290 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \
6294 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6303 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6306 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6308 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6310 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6312 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6314 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6316 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6318 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6320 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6322 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6324 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6326 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6328 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6330 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6332 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6338 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6340 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6342 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6344 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6346 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6348 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6350 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6352 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6355 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6358 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6360 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6362 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6364 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6366 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6368 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6374 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6376 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6378 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6380 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6382 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6384 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6387 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6390 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6393 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6396 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6399 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6402 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6404 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6406 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6408 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6411 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6413 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6423 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6430 stats = &sc->bge_mac_stats;
6520 struct bge_softc *sc;
6524 sc = (struct bge_softc *)arg1;
6526 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6535 struct bge_softc *sc;
6546 sc = (struct bge_softc *)arg1;
6548 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6549 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6553 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6555 BGE_LOCK(sc);
6556 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6557 sc->bge_cdata.bge_status_map,
6570 printf(" %08x", CSR_READ_4(sc, i));
6575 BGE_UNLOCK(sc);
6578 if (BGE_IS_5717_PLUS(sc))
6580 if (BGE_IS_5755_PLUS(sc))
6582 if (BGE_IS_575X_PLUS(sc))
6584 if (BGE_IS_5705_PLUS(sc))
6586 if (BGE_IS_5714_FAMILY(sc))
6588 if (BGE_IS_5700_FAMILY(sc))
6590 if (sc->bge_flags & BGE_FLAG_JUMBO)
6592 if (sc->bge_flags & BGE_FLAG_PCIX)
6594 if (sc->bge_flags & BGE_FLAG_PCIE)
6596 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6598 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6608 struct bge_softc *sc;
6619 sc = (struct bge_softc *)arg1;
6620 val = CSR_READ_4(sc, result);
6630 struct bge_softc *sc;
6641 sc = (struct bge_softc *)arg1;
6642 val = APE_READ_4(sc, result);
6652 struct bge_softc *sc;
6663 sc = (struct bge_softc *)arg1;
6664 val = bge_readmem_ind(sc, result);
6673 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6679 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6683 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6687 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6698 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6702 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6705 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6710 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6713 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6716 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6721 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6734 if ((*func)(sc, eaddr) == 0)
6743 struct bge_softc *sc;
6746 sc = if_getsoftc(ifp);
6747 if (!BGE_IS_5705_PLUS(sc))
6749 stats = &sc->bge_mac_stats;
6766 struct bge_softc *sc;
6768 sc = if_getsoftc(ifp);
6769 BGE_LOCK(sc);
6779 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6780 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6785 BGE_UNLOCK(sc);
6796 struct bge_softc *sc;
6800 sc = if_getsoftc(ifp);
6805 prodidx = sc->bge_tx_prodidx;
6806 error = bge_encap(sc, &m, &prodidx);
6808 bge_start_tx(sc, prodidx);
6815 struct bge_softc *sc;
6818 sc = if_getsoftc(ifp);
6823 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6824 sc->bge_cdata.bge_status_map,
6827 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6828 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6830 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6831 sc->bge_cdata.bge_status_map,
6834 (void)bge_rxeof(sc, rx_prod, 0);
6835 bge_txeof(sc, tx_cons);