Lines Matching +full:region +full:- +full:freeze +full:- +full:timeout +full:- +full:us
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2014 QLogic Corporation
42 * BCM5706C A0, A1 (pre-production)
43 * BCM5706S A0, A1 (pre-production)
44 * BCM5708C A0, B0 (pre-production)
45 * BCM5708S A0, B0 (pre-production)
46 * BCM5709C A0 B0, B1, B2 (pre-production)
47 * BCM5709S A0, B0, B1, B2 (pre-production)
153 "QLogic NetXtreme II BCM5706 1000Base-T" },
159 "QLogic NetXtreme II BCM5706 1000Base-SX" },
169 "QLogic NetXtreme II BCM5708 1000Base-T" },
179 "QLogic NetXtreme II BCM5708 1000Base-SX" },
187 "QLogic NetXtreme II BCM5709 1000Base-T" },
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
195 "QLogic NetXtreme II BCM5709 1000Base-SX" },
199 "QLogic NetXtreme II BCM5716 1000Base-T" },
215 "EEPROM - slow"},
221 /* Saifun SA25F010 (non-buffered flash) */
226 "Non-buffered flash (128kB)"},
227 /* Saifun SA25F020 (non-buffered flash) */
232 "Non-buffered flash (256kB)"},
238 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
242 "Entry 0101: ST M45PE10 (128kB non-buffered)"},
243 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
247 "Entry 0110: ST M45PE20 (256kB non-buffered)"},
248 /* Saifun SA25F005 (non-buffered flash) */
253 "Non-buffered flash (64kB)"},
258 "EEPROM - fast"},
300 * logical-to-physical mapping is required in the
523 bce_devs, nitems(bce_devs) - 1);
541 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
542 /* ToDo: Add MSI-X support. */
545 "MSI-X|MSI|INTx selector");
594 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
597 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
605 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
608 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
640 /* Generate an int. if 0us have elapsed since the last received frame. */
643 /* Generate an int. if 18us have elapsed since the last received frame. */
651 /* Generate an int. if 0us have elapsed since the last received frame. */
654 /* Generate an int. if 18us have elapsed since the last received frame. */
679 sc->bce_unit = device_get_unit(dev);
680 sc->bce_dev = dev;
693 while(t->bce_name != NULL) {
694 if ((vid == t->bce_vid) && (did == t->bce_did) &&
695 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
696 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
698 t->bce_name, (((pci_read_config(dev,
726 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
731 if (sc->bce_flags & BCE_PCIE_FLAG) {
732 printf("Bus (PCIe x%d, ", sc->link_width);
733 switch (sc->link_speed) {
740 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
741 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
742 "32-bit" : "64-bit"), sc->bus_speed_mhz);
747 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages,
748 (bce_hdr_split == TRUE ? sc->pg_pages: 0));
755 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
760 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
762 printf("MSI-X"); i++;
765 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
770 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
773 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
777 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
779 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
785 sc->bce_rx_quick_cons_trip_int,
786 sc->bce_rx_quick_cons_trip,
787 sc->bce_rx_ticks_int,
788 sc->bce_rx_ticks,
789 sc->bce_tx_quick_cons_trip_int,
790 sc->bce_tx_quick_cons_trip,
791 sc->bce_tx_ticks_int,
792 sc->bce_tx_ticks);
814 /* Check if PCI-X capability is enabled. */
817 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
826 sc->link_speed = link_status & 0xf;
827 sc->link_width = (link_status >> 4) & 0x3f;
828 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
829 sc->bce_flags |= BCE_PCIE_FLAG;
836 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
839 /* Check if MSI-X capability is enabled. */
842 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
860 /* fall-through */
862 /* fall-through */
864 /* fall-through */
866 sc->rx_pages = bce_rx_pages;
869 sc->rx_pages = DEFAULT_RX_PAGES;
876 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
881 /* fall-through */
883 /* fall-through */
885 /* fall-through */
887 sc->tx_pages = bce_tx_pages;
890 sc->tx_pages = DEFAULT_TX_PAGES;
902 sc->bce_tx_quick_cons_trip_int =
909 sc->bce_tx_quick_cons_trip_int =
914 sc->bce_tx_quick_cons_trip =
921 sc->bce_tx_quick_cons_trip =
932 sc->bce_tx_ticks_int =
939 sc->bce_tx_ticks_int =
944 sc->bce_tx_ticks =
951 sc->bce_tx_ticks =
961 sc->bce_rx_quick_cons_trip_int =
968 sc->bce_rx_quick_cons_trip_int =
973 sc->bce_rx_quick_cons_trip =
980 sc->bce_rx_quick_cons_trip =
991 sc->bce_rx_ticks_int = bce_rx_ticks_int;
997 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
1001 sc->bce_rx_ticks = bce_rx_ticks;
1007 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1015 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1016 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1024 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1025 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1048 sc->bce_dev = dev;
1052 sc->bce_unit = device_get_unit(dev);
1055 sc->bce_flags = 0;
1056 sc->bce_phy_flags = 0;
1064 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1067 if (sc->bce_res_mem == NULL) {
1075 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
1076 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1077 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1084 /* Try allocating MSI-X interrupts. */
1085 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1087 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1093 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1099 sc->bce_res_irq);
1100 sc->bce_res_irq = NULL;
1102 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1104 sc->bce_flags |= BCE_USING_MSIX_FLAG;
1110 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1121 sc->bce_flags |= BCE_USING_MSI_FLAG;
1123 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1135 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1139 if (sc->bce_res_irq == NULL) {
1160 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
1162 /* Weed out any non-production controller revisions. */
1182 * The embedded PCIe to PCI-X bridge (EPB)
1187 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1189 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1198 /* Multi-port devices use different offsets in shared memory. */
1199 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1200 (pci_get_function(sc->bce_dev) << 2));
1202 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1205 __FUNCTION__, sc->bce_shmem_base);
1212 num = (u8) (val >> (24 - (i * 8)));
1215 sc->bce_bc_ver[j++] = (num / k) + '0';
1221 sc->bce_bc_ver[j++] = '.';
1227 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1249 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1256 strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1267 sc->bce_flags |= BCE_PCIX_FLAG;
1274 sc->bus_speed_mhz = 133;
1278 sc->bus_speed_mhz = 100;
1283 sc->bus_speed_mhz = 66;
1288 sc->bus_speed_mhz = 50;
1294 sc->bus_speed_mhz = 33;
1299 sc->bus_speed_mhz = 66;
1301 sc->bus_speed_mhz = 33;
1305 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1338 sc->bce_stats_ticks = 1000000 & 0xffff00;
1341 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1342 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1353 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1374 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1385 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1391 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1399 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1400 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1408 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1409 ifmedia_add(&sc->bce_ifmedia,
1411 ifmedia_add(&sc->bce_ifmedia,
1414 ifmedia_add(&sc->bce_ifmedia,
1416 ifmedia_add(&sc->bce_ifmedia,
1419 ifmedia_add(&sc->bce_ifmedia,
1421 ifmedia_add(&sc->bce_ifmedia,
1423 ifmedia_add(&sc->bce_ifmedia,
1425 ifmedia_add(&sc->bce_ifmedia,
1427 ifmedia_add(&sc->bce_ifmedia,
1429 ifmedia_add(&sc->bce_ifmedia,
1432 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1433 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1434 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1437 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1438 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1448 ether_ifattach(ifp, sc->eaddr);
1450 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1451 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1454 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1455 NULL, bce_intr, sc, &sc->bce_intrhand);
1523 ifp = sc->bce_ifp;
1529 callout_stop(&sc->bce_pulse_callout);
1532 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1543 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1544 ifmedia_removeall(&sc->bce_ifmedia);
1575 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1637 /* reads but is much slower than memory-mapped I/O. */
1646 dev = sc->bce_dev;
1667 /* writes but is muchh slower than memory-mapped I/O. */
1676 dev = sc->bce_dev;
1688 /* Writes NetXtreme II shared memory region. */
1699 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1705 /* Reads NetXtreme II shared memory region. */
1713 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1836 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1841 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1871 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1878 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1916 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1921 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1947 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1950 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1984 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1990 mii = device_get_softc(sc->bce_miibus);
1991 media_active = mii->mii_media_active;
1992 media_status = mii->mii_media_status;
2014 /* fall-through */
2022 /* fall-through */
2037 "Setting Half-Duplex interface.\n");
2041 "Setting Full-Duplex interface.\n");
2049 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2054 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2061 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2066 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2104 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2144 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2172 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2187 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2272 /* Non-buffered flash parts require that a page be erased before it is */
2287 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2314 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2346 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2347 offset = ((offset / sc->bce_flash_info->page_size) <<
2348 sc->bce_flash_info->page_bits) +
2349 (offset % sc->bce_flash_info->page_size);
2378 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2411 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2412 offset = ((offset / sc->bce_flash_info->page_size) <<
2413 sc->bce_flash_info->page_bits) +
2414 (offset % sc->bce_flash_info->page_size);
2418 * Clear the DONE bit separately, convert NVRAM data to big-endian,
2436 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2465 sc->bce_flash_info = &flash_5709;
2490 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2491 sc->bce_flash_info = flash;
2510 if ((val & mask) == (flash->strapping & mask)) {
2512 sc->bce_flash_info = flash;
2520 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2521 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2522 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2523 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2534 sc->bce_flash_info = NULL;
2546 sc->bce_flash_size = val;
2548 sc->bce_flash_size = sc->bce_flash_info->total_size;
2551 __FUNCTION__, sc->bce_flash_info->name,
2552 sc->bce_flash_info->total_size);
2597 pre_len = 4 - (offset & 3);
2616 len32 -= pre_len;
2620 extra = 4 - (len32 & 3);
2635 memcpy(ret_buf, buf, 4 - extra);
2651 len32 -= 4;
2659 len32 -= 4;
2668 memcpy(ret_buf, buf, 4 - extra);
2717 align_end = 4 - (len32 & 3);
2719 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2738 memcpy(buf + len32 - 4, end, 4);
2752 page_start -= (page_start % sc->bce_flash_info->page_size);
2754 page_end = page_start + sc->bce_flash_info->page_size;
2769 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2773 * (non-buffer flash only) */
2774 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2775 if (j == (sc->bce_flash_info->page_size - 4)) {
2790 /* Enable writes to flash interface (unlock write-protect) */
2798 /* Re-enable the write again for the actual write */
2804 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2819 if ((addr == page_end - 4) ||
2820 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2821 (addr == data_end - 4))) {
2836 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2839 if (addr == page_end-4) {
2852 /* Disable writes to flash interface (lock write-protect) */
2860 written += data_end - data_start;
2967 sc->rx_bd_mbuf_alloc_size = MHLEN;
2969 sc->rx_bd_mbuf_align_pad =
2970 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN);
2971 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
2972 sc->rx_bd_mbuf_align_pad;
2977 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
2978 sc->rx_bd_mbuf_align_pad =
2979 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
2980 sc->rx_bd_mbuf_data_len =
2981 sc->rx_bd_mbuf_alloc_size -
2982 sc->rx_bd_mbuf_align_pad;
2985 sc->rx_bd_mbuf_alloc_size = MCLBYTES;
2986 sc->rx_bd_mbuf_align_pad =
2987 roundup2(MCLBYTES, 16) - MCLBYTES;
2988 sc->rx_bd_mbuf_data_len =
2989 sc->rx_bd_mbuf_alloc_size -
2990 sc->rx_bd_mbuf_align_pad;
2998 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
2999 sc->rx_bd_mbuf_align_pad);
3019 sc->bce_phy_addr = 1;
3037 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3048 if (pci_get_function(sc->bce_dev) == 0) {
3055 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3069 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3079 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3081 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3082 sc->bce_flags |= BCE_NO_WOL_FLAG;
3085 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3089 sc->bce_phy_addr = 2;
3093 sc->bce_phy_flags |=
3101 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3105 "Using PHY address %d.\n", sc->bce_phy_addr);
3120 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3129 /* Select auto-negotiation MMD of the PHY. */
3130 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3132 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3136 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3158 if (sc->status_block_paddr != 0) {
3160 sc->status_tag,
3161 sc->status_map);
3162 sc->status_block_paddr = 0;
3165 if (sc->status_block != NULL) {
3167 sc->status_tag,
3168 sc->status_block,
3169 sc->status_map);
3170 sc->status_block = NULL;
3173 if (sc->status_tag != NULL) {
3174 bus_dma_tag_destroy(sc->status_tag);
3175 sc->status_tag = NULL;
3179 if (sc->stats_block_paddr != 0) {
3181 sc->stats_tag,
3182 sc->stats_map);
3183 sc->stats_block_paddr = 0;
3186 if (sc->stats_block != NULL) {
3188 sc->stats_tag,
3189 sc->stats_block,
3190 sc->stats_map);
3191 sc->stats_block = NULL;
3194 if (sc->stats_tag != NULL) {
3195 bus_dma_tag_destroy(sc->stats_tag);
3196 sc->stats_tag = NULL;
3201 for (i = 0; i < sc->ctx_pages; i++ ) {
3202 if (sc->ctx_paddr[i] != 0) {
3204 sc->ctx_tag,
3205 sc->ctx_map[i]);
3206 sc->ctx_paddr[i] = 0;
3209 if (sc->ctx_block[i] != NULL) {
3211 sc->ctx_tag,
3212 sc->ctx_block[i],
3213 sc->ctx_map[i]);
3214 sc->ctx_block[i] = NULL;
3219 if (sc->ctx_tag != NULL) {
3220 bus_dma_tag_destroy(sc->ctx_tag);
3221 sc->ctx_tag = NULL;
3226 for (i = 0; i < sc->tx_pages; i++ ) {
3227 if (sc->tx_bd_chain_paddr[i] != 0) {
3229 sc->tx_bd_chain_tag,
3230 sc->tx_bd_chain_map[i]);
3231 sc->tx_bd_chain_paddr[i] = 0;
3234 if (sc->tx_bd_chain[i] != NULL) {
3236 sc->tx_bd_chain_tag,
3237 sc->tx_bd_chain[i],
3238 sc->tx_bd_chain_map[i]);
3239 sc->tx_bd_chain[i] = NULL;
3244 if (sc->tx_bd_chain_tag != NULL) {
3245 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3246 sc->tx_bd_chain_tag = NULL;
3250 for (i = 0; i < sc->rx_pages; i++ ) {
3251 if (sc->rx_bd_chain_paddr[i] != 0) {
3253 sc->rx_bd_chain_tag,
3254 sc->rx_bd_chain_map[i]);
3255 sc->rx_bd_chain_paddr[i] = 0;
3258 if (sc->rx_bd_chain[i] != NULL) {
3260 sc->rx_bd_chain_tag,
3261 sc->rx_bd_chain[i],
3262 sc->rx_bd_chain_map[i]);
3263 sc->rx_bd_chain[i] = NULL;
3268 if (sc->rx_bd_chain_tag != NULL) {
3269 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3270 sc->rx_bd_chain_tag = NULL;
3275 for (i = 0; i < sc->pg_pages; i++ ) {
3276 if (sc->pg_bd_chain_paddr[i] != 0) {
3278 sc->pg_bd_chain_tag,
3279 sc->pg_bd_chain_map[i]);
3280 sc->pg_bd_chain_paddr[i] = 0;
3283 if (sc->pg_bd_chain[i] != NULL) {
3285 sc->pg_bd_chain_tag,
3286 sc->pg_bd_chain[i],
3287 sc->pg_bd_chain_map[i]);
3288 sc->pg_bd_chain[i] = NULL;
3293 if (sc->pg_bd_chain_tag != NULL) {
3294 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3295 sc->pg_bd_chain_tag = NULL;
3301 if (sc->tx_mbuf_map[i] != NULL) {
3302 bus_dmamap_unload(sc->tx_mbuf_tag,
3303 sc->tx_mbuf_map[i]);
3304 bus_dmamap_destroy(sc->tx_mbuf_tag,
3305 sc->tx_mbuf_map[i]);
3306 sc->tx_mbuf_map[i] = NULL;
3311 if (sc->tx_mbuf_tag != NULL) {
3312 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3313 sc->tx_mbuf_tag = NULL;
3318 if (sc->rx_mbuf_map[i] != NULL) {
3319 bus_dmamap_unload(sc->rx_mbuf_tag,
3320 sc->rx_mbuf_map[i]);
3321 bus_dmamap_destroy(sc->rx_mbuf_tag,
3322 sc->rx_mbuf_map[i]);
3323 sc->rx_mbuf_map[i] = NULL;
3328 if (sc->rx_mbuf_tag != NULL) {
3329 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3330 sc->rx_mbuf_tag = NULL;
3336 if (sc->pg_mbuf_map[i] != NULL) {
3337 bus_dmamap_unload(sc->pg_mbuf_tag,
3338 sc->pg_mbuf_map[i]);
3339 bus_dmamap_destroy(sc->pg_mbuf_tag,
3340 sc->pg_mbuf_map[i]);
3341 sc->pg_mbuf_map[i] = NULL;
3346 if (sc->pg_mbuf_tag != NULL) {
3347 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3348 sc->pg_mbuf_tag = NULL;
3353 if (sc->parent_tag != NULL) {
3354 bus_dma_tag_destroy(sc->parent_tag);
3355 sc->parent_tag = NULL;
3367 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
3390 *busaddr = segs->ds_addr;
3401 /* +-----------------+----------+----------+----------+----------+ */
3403 /* +-----------------+----------+----------+----------+----------+ */
3411 /* +-----------------+----------+----------+----------+----------+ */
3434 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3436 &sc->parent_tag)) {
3448 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3449 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3451 0, NULL, NULL, &sc->status_tag)) {
3458 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3460 &sc->status_map)) {
3467 error = bus_dmamap_load(sc->status_tag, sc->status_map,
3468 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3469 &sc->status_block_paddr, BUS_DMA_NOWAIT);
3471 if (error || sc->status_block_paddr == 0) {
3479 __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3486 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3487 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3489 0, NULL, NULL, &sc->stats_tag)) {
3496 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3497 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3504 error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3505 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3506 &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3508 if (error || sc->stats_block_paddr == 0) {
3516 __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3520 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3521 if (sc->ctx_pages == 0)
3522 sc->ctx_pages = 1;
3524 DBRUNIF((sc->ctx_pages > 512),
3526 __FILE__, __LINE__, sc->ctx_pages));
3534 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3535 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3537 0, NULL, NULL, &sc->ctx_tag)) {
3544 for (i = 0; i < sc->ctx_pages; i++) {
3545 if(bus_dmamem_alloc(sc->ctx_tag,
3546 (void **)&sc->ctx_block[i],
3548 &sc->ctx_map[i])) {
3555 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3556 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3557 &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3559 if (error || sc->ctx_paddr[i] == 0) {
3568 (uintmax_t) sc->ctx_paddr[i]);
3577 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3578 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3580 NULL, NULL, &sc->tx_bd_chain_tag)) {
3587 for (i = 0; i < sc->tx_pages; i++) {
3588 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3589 (void **)&sc->tx_bd_chain[i],
3591 &sc->tx_bd_chain_map[i])) {
3598 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3599 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3601 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3603 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3612 (uintmax_t) sc->tx_bd_chain_paddr[i]);
3627 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3628 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3629 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3638 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3639 &sc->tx_mbuf_map[i])) {
3652 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3654 sc->max_bus_addr, NULL, NULL,
3656 0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3663 for (i = 0; i < sc->rx_pages; i++) {
3664 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3665 (void **)&sc->rx_bd_chain[i],
3667 &sc->rx_bd_chain_map[i])) {
3674 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3675 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3677 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3679 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3688 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3695 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3696 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3703 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3704 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3705 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3714 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3715 &sc->rx_mbuf_map[i])) {
3729 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3730 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3732 0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3739 for (i = 0; i < sc->pg_pages; i++) {
3740 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3741 (void **)&sc->pg_bd_chain[i],
3743 &sc->pg_bd_chain_map[i])) {
3751 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3752 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3754 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3756 if (error || sc->pg_bd_chain_paddr[i] == 0) {
3765 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3771 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3772 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3773 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3782 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3783 &sc->pg_mbuf_map[i])) {
3813 dev = sc->bce_dev;
3817 if (sc->bce_intrhand != NULL) {
3819 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3822 if (sc->bce_res_irq != NULL) {
3825 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3828 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3829 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3833 if (sc->bce_res_mem != NULL) {
3836 sc->bce_res_mem);
3839 if (sc->bce_ifp != NULL) {
3841 if_free(sc->bce_ifp);
3844 if (mtx_initialized(&sc->bce_mtx))
3868 if (sc->bce_fw_timed_out == TRUE) {
3874 sc->bce_fw_wr_seq++;
3875 msg_data |= sc->bce_fw_wr_seq;
3895 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3903 sc->bce_fw_timed_out = TRUE;
3948 /* Reset the processor, un-stall is done later. */
3979 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3980 if (fw->text) {
3983 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3984 REG_WR_IND(sc, offset, fw->text[j]);
3989 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3990 if (fw->data) {
3993 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3994 REG_WR_IND(sc, offset, fw->data[j]);
3999 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4000 if (fw->sbss) {
4003 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4004 REG_WR_IND(sc, offset, fw->sbss[j]);
4009 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4010 if (fw->bss) {
4013 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4014 REG_WR_IND(sc, offset, fw->bss[j]);
4018 /* Load the Read-Only area. */
4019 offset = cpu_reg->spad_base +
4020 (fw->rodata_addr - cpu_reg->mips_view_base);
4021 if (fw->rodata) {
4024 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4025 REG_WR_IND(sc, offset, fw->rodata[j]);
4029 /* Clear the pre-fetch instruction and set the FW start address. */
4030 REG_WR_IND(sc, cpu_reg->inst, 0);
4031 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4052 val = REG_RD_IND(sc, cpu_reg->mode);
4053 val &= ~cpu_reg->mode_value_halt;
4054 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4055 REG_WR_IND(sc, cpu_reg->mode, val);
4074 val = REG_RD_IND(sc, cpu_reg->mode);
4075 val |= cpu_reg->mode_value_halt;
4076 REG_WR_IND(sc, cpu_reg->mode, val);
4077 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4666 val |= (BCM_PAGE_BITS - 8) << 16;
4683 for (i = 0; i < sc->ctx_pages; i++) {
4686 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4689 BCE_ADDR_HI(sc->ctx_paddr[i]));
4719 vcid_addr -= PHY_CTX_SIZE;
4752 * power-on and runtime configuration items in a
4766 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4767 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4768 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4769 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4770 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4771 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4775 "address = %6D\n", sc->eaddr, ":");
4789 u8 *mac_addr = sc->eaddr;
4795 "%6D\n", sc->eaddr, ":");
4824 ifp = sc->bce_ifp;
4826 callout_stop(&sc->bce_tick_callout);
4844 sc->watchdog_timer = 0;
4846 sc->bce_link_up = FALSE;
4869 * been auto-negotiated. Resetting the chip will clobber those
4892 sc->bce_fw_timed_out = FALSE;
4893 sc->bce_drv_cardiac_arrest = FALSE;
4915 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4922 /* Allow up to 30us for reset to complete. */
4952 sc->bce_fw_timed_out = FALSE;
4953 sc->bce_drv_cardiac_arrest = FALSE;
5000 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5010 !(sc->bce_flags & BCE_PCIX_FLAG))
5025 /* Initialize the on-boards CPUs */
5028 /* Enable management frames (NC-SI) to flow to the MCP. */
5029 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5057 val = (BCM_PAGE_BITS - 8) << 24;
5063 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5093 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5094 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
5095 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
5098 sc->last_status_idx = 0;
5099 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5106 BCE_ADDR_LO(sc->status_block_paddr));
5108 BCE_ADDR_HI(sc->status_block_paddr));
5112 BCE_ADDR_LO(sc->stats_block_paddr));
5114 BCE_ADDR_HI(sc->stats_block_paddr));
5123 (sc->bce_tx_quick_cons_trip_int << 16) |
5124 sc->bce_tx_quick_cons_trip);
5126 (sc->bce_rx_quick_cons_trip_int << 16) |
5127 sc->bce_rx_quick_cons_trip);
5129 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5131 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5132 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5144 /* ToDo: Add MSI-X support. */
5145 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5146 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5155 (sc->tx_quick_cons_trip_int << 16) |
5156 sc->tx_quick_cons_trip);
5159 (sc->tx_ticks_int << 16) | sc->tx_ticks);
5166 * INT_MASK bit after an MSI/MSI-X interrupt
5169 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5172 /* Set the MSI-X status blocks to 128 byte boundaries. */
5173 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5217 /* Disable management frames (NC-SI) from flowing to the MCP. */
5218 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5236 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5274 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5275 sc->rx_low_watermark = sc->free_rx_bd);
5276 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5277 sc->rx_empty_count++);
5281 sc->mbuf_alloc_failed_count++;
5282 sc->mbuf_alloc_failed_sim_count++;
5291 sc->rx_bd_mbuf_alloc_size);
5294 sc->mbuf_alloc_failed_count++;
5299 DBRUN(sc->debug_rx_mbuf_alloc++);
5305 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5306 m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5311 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5312 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5319 sc->dma_map_addr_rx_failed_count++;
5322 DBRUN(sc->debug_rx_mbuf_alloc--);
5333 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5335 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5336 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5337 rxbd->rx_bd_len = htole32(segs[0].ds_len);
5338 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5342 sc->rx_mbuf_ptr[chain_prod] = m_new;
5343 sc->free_rx_bd -= nsegs;
5387 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5388 sc->pg_low_watermark = sc->free_pg_bd);
5389 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5393 sc->mbuf_alloc_failed_count++;
5394 sc->mbuf_alloc_failed_sim_count++;
5401 sc->mbuf_alloc_failed_count++;
5406 DBRUN(sc->debug_pg_mbuf_alloc++);
5408 m_new->m_len = MCLBYTES;
5413 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5414 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5422 DBRUN(sc->debug_pg_mbuf_alloc--);
5438 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5440 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5441 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5442 pgbd->rx_bd_len = htole32(MCLBYTES);
5443 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5446 sc->pg_mbuf_ptr[prod_idx] = m_new;
5447 sc->free_pg_bd--;
5485 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5488 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5499 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5502 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5525 sc->tx_prod = 0;
5526 sc->tx_cons = 0;
5527 sc->tx_prod_bseq = 0;
5528 sc->used_tx_bd = 0;
5529 sc->max_tx_bd = USABLE_TX_BD_ALLOC;
5530 DBRUN(sc->tx_hi_watermark = 0);
5531 DBRUN(sc->tx_full_count = 0);
5534 * The NetXtreme II supports a linked-list structure called
5544 for (i = 0; i < sc->tx_pages; i++) {
5547 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5550 if (i == (sc->tx_pages - 1))
5555 txbd->tx_bd_haddr_hi =
5556 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5557 txbd->tx_bd_haddr_lo =
5558 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5584 if (sc->tx_mbuf_ptr[i] != NULL) {
5585 if (sc->tx_mbuf_map[i] != NULL)
5586 bus_dmamap_sync(sc->tx_mbuf_tag,
5587 sc->tx_mbuf_map[i],
5589 m_freem(sc->tx_mbuf_ptr[i]);
5590 sc->tx_mbuf_ptr[i] = NULL;
5591 DBRUN(sc->debug_tx_mbuf_alloc--);
5596 for (i = 0; i < sc->tx_pages; i++)
5597 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5599 sc->used_tx_bd = 0;
5602 DBRUNIF((sc->debug_tx_mbuf_alloc),
5605 sc->debug_tx_mbuf_alloc));
5638 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5675 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5677 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5699 sc->rx_prod = 0;
5700 sc->rx_cons = 0;
5701 sc->rx_prod_bseq = 0;
5702 sc->free_rx_bd = USABLE_RX_BD_ALLOC;
5703 sc->max_rx_bd = USABLE_RX_BD_ALLOC;
5706 for (i = 0; i < sc->rx_pages; i++) {
5709 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5712 if (i == (sc->rx_pages - 1))
5718 rxbd->rx_bd_haddr_hi =
5719 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5720 rxbd->rx_bd_haddr_lo =
5721 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5727 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5728 DBRUN(sc->rx_empty_count = 0);
5729 for (i = 0; i < sc->rx_pages; i++) {
5730 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5763 prod = sc->rx_prod;
5764 prod_bseq = sc->rx_prod_bseq;
5767 while (sc->free_rx_bd > 0) {
5777 sc->rx_prod = prod;
5778 sc->rx_prod_bseq = prod_bseq;
5808 if (sc->rx_mbuf_ptr[i] != NULL) {
5809 if (sc->rx_mbuf_map[i] != NULL)
5810 bus_dmamap_sync(sc->rx_mbuf_tag,
5811 sc->rx_mbuf_map[i],
5813 m_freem(sc->rx_mbuf_ptr[i]);
5814 sc->rx_mbuf_ptr[i] = NULL;
5815 DBRUN(sc->debug_rx_mbuf_alloc--);
5820 for (i = 0; i < sc->rx_pages; i++)
5821 if (sc->rx_bd_chain[i] != NULL)
5822 bzero((char *)sc->rx_bd_chain[i],
5825 sc->free_rx_bd = sc->max_rx_bd;
5828 DBRUNIF((sc->debug_rx_mbuf_alloc),
5830 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5853 sc->pg_prod = 0;
5854 sc->pg_cons = 0;
5855 sc->free_pg_bd = USABLE_PG_BD_ALLOC;
5856 sc->max_pg_bd = USABLE_PG_BD_ALLOC;
5857 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5858 DBRUN(sc->pg_empty_count = 0);
5861 for (i = 0; i < sc->pg_pages; i++) {
5864 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5867 if (i == (sc->pg_pages - 1))
5873 pgbd->rx_bd_haddr_hi =
5874 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5875 pgbd->rx_bd_haddr_lo =
5876 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5886 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
5894 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5896 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5902 for (i = 0; i < sc->pg_pages; i++) {
5903 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
5930 prod = sc->pg_prod;
5933 while (sc->free_pg_bd > 0) {
5943 sc->pg_prod = prod;
5975 if (sc->pg_mbuf_ptr[i] != NULL) {
5976 if (sc->pg_mbuf_map[i] != NULL)
5977 bus_dmamap_sync(sc->pg_mbuf_tag,
5978 sc->pg_mbuf_map[i],
5980 m_freem(sc->pg_mbuf_ptr[i]);
5981 sc->pg_mbuf_ptr[i] = NULL;
5982 DBRUN(sc->debug_pg_mbuf_alloc--);
5987 for (i = 0; i < sc->pg_pages; i++)
5988 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
5990 sc->free_pg_bd = sc->max_pg_bd;
5993 DBRUNIF((sc->debug_pg_mbuf_alloc),
5995 __FUNCTION__, sc->debug_pg_mbuf_alloc));
6008 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6041 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6091 sc->bce_link_up = FALSE;
6092 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6093 ifm = &sc->bce_ifmedia;
6094 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6097 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6098 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6108 if ((sc->bce_phy_flags &
6122 if ((sc->bce_phy_flags &
6135 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6143 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6151 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6161 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6164 * Advertise pause capability for full-duplex media.
6169 if ((sc->bce_phy_flags &
6178 mii = device_get_softc(sc->bce_miibus);
6182 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6198 ifp = sc->bce_ifp;
6201 ifmr->ifm_status = IFM_AVALID;
6202 ifmr->ifm_active = IFM_ETHER;
6206 ifmr->ifm_status |= IFM_ACTIVE;
6208 ifmr->ifm_active |= IFM_NONE;
6214 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6218 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6222 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6226 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6230 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6231 ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6233 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6237 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6238 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6240 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6244 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6245 ifmr->ifm_active |= IFM_NONE;
6248 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6252 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6253 ifmr->ifm_active |= IFM_NONE;
6256 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6260 ifmr->ifm_active |= IFM_NONE;
6265 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6267 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6291 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6294 mii = device_get_softc(sc->bce_miibus);
6296 ifmr->ifm_active = mii->mii_media_active;
6297 ifmr->ifm_status = mii->mii_media_status;
6318 DBRUN(sc->phy_interrupts++);
6320 new_link_state = sc->status_block->status_attn_bits &
6322 old_link_state = sc->status_block->status_attn_bits_ack &
6340 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6343 if_printf(sc->bce_ifp, "link UP\n");
6344 if_link_state_change(sc->bce_ifp,
6348 if_printf(sc->bce_ifp, "link DOWN\n");
6349 if_link_state_change(sc->bce_ifp,
6358 sc->bce_link_up = FALSE;
6359 callout_stop(&sc->bce_tick_callout);
6382 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6398 if_t ifp = sc->bce_ifp;
6408 DBRUN(sc->interrupts_rx++);
6411 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6414 for (int i = 0; i < sc->rx_pages; i++)
6415 bus_dmamap_sync(sc->rx_bd_chain_tag,
6416 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6420 for (int i = 0; i < sc->pg_pages; i++)
6421 bus_dmamap_sync(sc->pg_bd_chain_tag,
6422 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6426 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6429 sw_rx_cons = sc->rx_cons;
6430 sw_pg_cons = sc->pg_cons;
6433 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6434 sc->rx_low_watermark = sc->free_rx_bd);
6435 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6436 sc->rx_empty_count++);
6448 bus_dmamap_sync(sc->rx_mbuf_tag,
6449 sc->rx_mbuf_map[sw_rx_cons_idx],
6451 bus_dmamap_unload(sc->rx_mbuf_tag,
6452 sc->rx_mbuf_map[sw_rx_cons_idx]);
6455 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6456 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6457 DBRUN(sc->debug_rx_mbuf_alloc--);
6458 sc->free_rx_bd++;
6471 * +---------+-----+---------------------+-----+
6473 * +---------+-----+---------------------+-----+
6482 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6483 status = l2fhdr->l2_fhdr_status;
6488 * +---------------------+-----+
6490 * +---------------------+-----+
6504 * sc->rx_bd_mbuf_data_len bytes).
6506 if (pkt_len > m0->m_len) {
6521 DBRUN(sc->split_header_frames_rcvd++);
6531 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6532 DBRUN(sc->split_header_tcp_frames_rcvd++);
6535 rem_len = pkt_len - m0->m_len;
6544 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6545 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6546 DBRUN(sc->debug_pg_mbuf_alloc--);
6547 sc->free_pg_bd++;
6550 bus_dmamap_sync(sc->pg_mbuf_tag,
6551 sc->pg_mbuf_map[sw_pg_cons_idx],
6553 bus_dmamap_unload(sc->pg_mbuf_tag,
6554 sc->pg_mbuf_map[sw_pg_cons_idx]);
6557 if (rem_len < m_pg->m_len) {
6559 m_pg->m_len = rem_len;
6563 rem_len -= m_pg->m_len;
6573 m0->m_pkthdr.len = pkt_len;
6587 m0->m_pkthdr.len = m0->m_len = pkt_len;
6591 m0->m_pkthdr.len = m0->m_len = pkt_len;
6594 m_adj(m0, -ETHER_CRC_LEN);
6598 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6599 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6604 sc->l2fhdr_error_sim_count++;
6612 sc->l2fhdr_error_count++;
6619 m0->m_pkthdr.rcvif = ifp;
6622 m0->m_pkthdr.csum_flags = 0;
6629 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6630 DBRUN(sc->csum_offload_ip++);
6632 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6633 m0->m_pkthdr.csum_flags |=
6643 DBRUN(sc->csum_offload_tcp_udp++);
6644 m0->m_pkthdr.csum_data =
6645 l2fhdr->l2_fhdr_tcp_udp_xsum;
6646 m0->m_pkthdr.csum_flags |=
6655 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6656 DBRUN(sc->vlan_tagged_frames_rcvd++);
6658 DBRUN(sc->vlan_tagged_frames_stripped++);
6659 m0->m_pkthdr.ether_vtag =
6660 l2fhdr->l2_fhdr_vlan_tag;
6661 m0->m_flags |= M_VLANTAG;
6675 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6677 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6679 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6680 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6681 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6682 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6695 sc->rx_cons = sw_rx_cons;
6696 sc->pg_cons = sw_pg_cons;
6703 sw_rx_cons = sc->rx_cons;
6704 sw_pg_cons = sc->pg_cons;
6709 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6714 sc->pg_cons = sw_pg_cons;
6719 sc->rx_cons = sw_rx_cons;
6723 for (int i = 0; i < sc->rx_pages; i++)
6724 bus_dmamap_sync(sc->rx_bd_chain_tag,
6725 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6728 for (int i = 0; i < sc->pg_pages; i++)
6729 bus_dmamap_sync(sc->pg_bd_chain_tag,
6730 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6735 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6752 hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6768 if_t ifp = sc->bce_ifp;
6772 DBRUN(sc->interrupts_tx++);
6775 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6780 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6781 sw_tx_cons = sc->tx_cons;
6784 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6805 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6821 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6823 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6834 bus_dmamap_unload(sc->tx_mbuf_tag,
6835 sc->tx_mbuf_map[sw_tx_chain_cons]);
6838 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6839 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6840 DBRUN(sc->debug_tx_mbuf_alloc--);
6845 sc->used_tx_bd--;
6849 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6852 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6856 /* Clear the TX timeout timer. */
6857 sc->watchdog_timer = 0;
6860 if (sc->used_tx_bd < sc->max_tx_bd) {
6864 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6868 sc->tx_cons = sw_tx_cons;
6872 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6906 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6909 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6913 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6934 ifp = sc->bce_ifp;
6961 bcopy(if_getlladdr(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6975 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len + MCLBYTES)
6976 ether_mtu = sc->rx_bd_mbuf_data_len +
6981 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len)
6982 ether_mtu = sc->rx_bd_mbuf_data_len;
7024 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7047 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7053 ifp = sc->bce_ifp;
7102 DBRUN(sc->tso_frames_requested++);
7110 sc->mbuf_alloc_failed_count++;
7127 etype = ntohs(eh->ether_type);
7132 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7134 if (ip->ip_p != IPPROTO_TCP) {
7135 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7143 ip_hlen = ip->ip_hl << 2;
7152 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7154 tcp_hlen = (th->th_off << 2);
7165 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7166 ip_len = ip->ip_len;
7167 ip->ip_len = 0;
7168 ip->ip_sum = 0;
7196 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7199 DBRUN(sc->tso_frames_completed++);
7231 if (sc->used_tx_bd >= sc->max_tx_bd)
7236 if (m0->m_pkthdr.csum_flags) {
7237 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7240 DBRUN(sc->tso_frames_failed++);
7243 mss = htole16(m0->m_pkthdr.tso_segsz);
7245 if (m0->m_pkthdr.csum_flags & CSUM_IP)
7247 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7253 if (m0->m_flags & M_VLANTAG) {
7255 vlan_tag = m0->m_pkthdr.ether_vtag;
7259 prod = sc->tx_prod;
7261 map = sc->tx_mbuf_map[chain_prod];
7264 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7269 sc->mbuf_frag_count++;
7277 sc->mbuf_alloc_failed_count++;
7284 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7290 sc->dma_map_addr_tx_failed_count++;
7299 sc->dma_map_addr_tx_failed_count++;
7305 sc->dma_map_addr_tx_failed_count++;
7311 sc->dma_map_addr_tx_failed_count++;
7317 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7318 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7324 prod_bseq = sc->tx_prod_bseq;
7343 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7346 txbd->tx_bd_haddr_lo =
7348 txbd->tx_bd_haddr_hi =
7350 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7352 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7353 txbd->tx_bd_flags = htole16(flags);
7356 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7361 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7375 sc->tx_mbuf_ptr[chain_prod] = m0;
7376 sc->used_tx_bd += nsegs;
7379 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7380 sc->tx_hi_watermark = sc->used_tx_bd);
7381 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7382 DBRUNIF(sc->debug_tx_mbuf_alloc++);
7387 sc->tx_prod = prod;
7388 sc->tx_prod_bseq = prod_bseq;
7392 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7394 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7420 tx_prod = sc->tx_prod;
7426 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7429 if (sc->bce_link_up == FALSE) {
7444 while (sc->used_tx_bd < sc->max_tx_bd) {
7464 "tx_bd used = %d\n", sc->used_tx_bd);
7484 /* Set the tx timeout. */
7485 sc->watchdog_timer = BCE_TX_TIMEOUT;
7534 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7535 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7542 (int) if_getmtu(ifp), (int) ifr->ifr_mtu);
7545 if_setmtu(ifp, ifr->ifr_mtu);
7574 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7603 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7604 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7607 mii = device_get_softc(sc->bce_miibus);
7608 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7615 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
7678 /* Transmit timeout handler. */
7694 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7699 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7702 * If link partner has us in XOFF state then wait for
7705 sc->watchdog_timer = BCE_TX_TIMEOUT;
7714 sc->watchdog_timer = BCE_TX_TIMEOUT;
7723 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7739 if_setdrvflagbits(sc->bce_ifp, 0, IFF_DRV_RUNNING);
7742 sc->watchdog_timeouts++;
7769 ifp = sc->bce_ifp;
7777 DBRUN(sc->interrupts_generated++);
7780 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7788 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7789 sc->status_block->status_idx == sc->last_status_idx &&
7808 status_attn_bits = sc->status_block->status_attn_bits;
7813 sc->unexpected_attention_sim_count++;
7819 (sc->status_block->status_attn_bits_ack &
7824 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7831 (sc->status_block->status_attn_bits_ack &
7833 sc->unexpected_attention_count++;
7837 sc->status_block->status_attn_bits);
7848 if (hw_rx_cons != sc->hw_rx_cons)
7852 if (hw_tx_cons != sc->hw_tx_cons)
7856 sc->last_status_idx = sc->status_block->status_idx;
7862 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7872 if ((hw_rx_cons == sc->hw_rx_cons) &&
7873 (hw_tx_cons == sc->hw_tx_cons))
7877 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
7879 /* Re-enable interrupts. */
7923 ifp = sc->bce_ifp;
7926 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7935 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
7969 if (rx_mode != sc->rx_mode) {
7973 sc->rx_mode = rx_mode;
7999 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8001 stats = (struct statistics_block *) sc->stats_block;
8007 sc->stat_IfHCInOctets =
8008 ((u64) stats->stat_IfHCInOctets_hi << 32) +
8009 (u64) stats->stat_IfHCInOctets_lo;
8011 sc->stat_IfHCInBadOctets =
8012 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8013 (u64) stats->stat_IfHCInBadOctets_lo;
8015 sc->stat_IfHCOutOctets =
8016 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8017 (u64) stats->stat_IfHCOutOctets_lo;
8019 sc->stat_IfHCOutBadOctets =
8020 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8021 (u64) stats->stat_IfHCOutBadOctets_lo;
8023 sc->stat_IfHCInUcastPkts =
8024 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8025 (u64) stats->stat_IfHCInUcastPkts_lo;
8027 sc->stat_IfHCInMulticastPkts =
8028 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8029 (u64) stats->stat_IfHCInMulticastPkts_lo;
8031 sc->stat_IfHCInBroadcastPkts =
8032 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8033 (u64) stats->stat_IfHCInBroadcastPkts_lo;
8035 sc->stat_IfHCOutUcastPkts =
8036 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8037 (u64) stats->stat_IfHCOutUcastPkts_lo;
8039 sc->stat_IfHCOutMulticastPkts =
8040 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8041 (u64) stats->stat_IfHCOutMulticastPkts_lo;
8043 sc->stat_IfHCOutBroadcastPkts =
8044 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8045 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8048 /* ToDo: Read the statistics from auto-clear regs? */
8050 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8051 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8053 sc->stat_Dot3StatsCarrierSenseErrors =
8054 stats->stat_Dot3StatsCarrierSenseErrors;
8056 sc->stat_Dot3StatsFCSErrors =
8057 stats->stat_Dot3StatsFCSErrors;
8059 sc->stat_Dot3StatsAlignmentErrors =
8060 stats->stat_Dot3StatsAlignmentErrors;
8062 sc->stat_Dot3StatsSingleCollisionFrames =
8063 stats->stat_Dot3StatsSingleCollisionFrames;
8065 sc->stat_Dot3StatsMultipleCollisionFrames =
8066 stats->stat_Dot3StatsMultipleCollisionFrames;
8068 sc->stat_Dot3StatsDeferredTransmissions =
8069 stats->stat_Dot3StatsDeferredTransmissions;
8071 sc->stat_Dot3StatsExcessiveCollisions =
8072 stats->stat_Dot3StatsExcessiveCollisions;
8074 sc->stat_Dot3StatsLateCollisions =
8075 stats->stat_Dot3StatsLateCollisions;
8077 sc->stat_EtherStatsCollisions =
8078 stats->stat_EtherStatsCollisions;
8080 sc->stat_EtherStatsFragments =
8081 stats->stat_EtherStatsFragments;
8083 sc->stat_EtherStatsJabbers =
8084 stats->stat_EtherStatsJabbers;
8086 sc->stat_EtherStatsUndersizePkts =
8087 stats->stat_EtherStatsUndersizePkts;
8089 sc->stat_EtherStatsOversizePkts =
8090 stats->stat_EtherStatsOversizePkts;
8092 sc->stat_EtherStatsPktsRx64Octets =
8093 stats->stat_EtherStatsPktsRx64Octets;
8095 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8096 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8098 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8099 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8101 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8102 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8104 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8105 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8107 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8108 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8110 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8111 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8113 sc->stat_EtherStatsPktsTx64Octets =
8114 stats->stat_EtherStatsPktsTx64Octets;
8116 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8117 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8119 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8120 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8122 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8123 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8125 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8126 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8128 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8129 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8131 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8132 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8134 sc->stat_XonPauseFramesReceived =
8135 stats->stat_XonPauseFramesReceived;
8137 sc->stat_XoffPauseFramesReceived =
8138 stats->stat_XoffPauseFramesReceived;
8140 sc->stat_OutXonSent =
8141 stats->stat_OutXonSent;
8143 sc->stat_OutXoffSent =
8144 stats->stat_OutXoffSent;
8146 sc->stat_FlowControlDone =
8147 stats->stat_FlowControlDone;
8149 sc->stat_MacControlFramesReceived =
8150 stats->stat_MacControlFramesReceived;
8152 sc->stat_XoffStateEntered =
8153 stats->stat_XoffStateEntered;
8155 sc->stat_IfInFramesL2FilterDiscards =
8156 stats->stat_IfInFramesL2FilterDiscards;
8158 sc->stat_IfInRuleCheckerDiscards =
8159 stats->stat_IfInRuleCheckerDiscards;
8161 sc->stat_IfInFTQDiscards =
8162 stats->stat_IfInFTQDiscards;
8164 sc->stat_IfInMBUFDiscards =
8165 stats->stat_IfInMBUFDiscards;
8167 sc->stat_IfInRuleCheckerP4Hit =
8168 stats->stat_IfInRuleCheckerP4Hit;
8170 sc->stat_CatchupInRuleCheckerDiscards =
8171 stats->stat_CatchupInRuleCheckerDiscards;
8173 sc->stat_CatchupInFTQDiscards =
8174 stats->stat_CatchupInFTQDiscards;
8176 sc->stat_CatchupInMBUFDiscards =
8177 stats->stat_CatchupInMBUFDiscards;
8179 sc->stat_CatchupInRuleCheckerP4Hit =
8180 stats->stat_CatchupInRuleCheckerP4Hit;
8182 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8199 return (sc->stat_EtherStatsCollisions);
8201 return (sc->stat_EtherStatsUndersizePkts +
8202 sc->stat_EtherStatsOversizePkts +
8203 sc->stat_IfInMBUFDiscards +
8204 sc->stat_Dot3StatsAlignmentErrors +
8205 sc->stat_Dot3StatsFCSErrors +
8206 sc->stat_IfInRuleCheckerDiscards +
8207 sc->stat_IfInFTQDiscards +
8208 sc->l2fhdr_error_count +
8209 sc->com_no_buffers);
8211 rv = sc->stat_Dot3StatsExcessiveCollisions +
8212 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8213 sc->stat_Dot3StatsLateCollisions +
8214 sc->watchdog_timeouts;
8222 rv += sc->stat_Dot3StatsCarrierSenseErrors;
8247 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8251 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8255 if (sc->bce_drv_cardiac_arrest == FALSE) {
8256 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8257 sc->bce_drv_cardiac_arrest = TRUE;
8261 __FUNCTION__, sc->bc_state);
8270 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8271 sc->bce_drv_cardiac_arrest = FALSE;
8274 __FUNCTION__, sc->bc_state);
8280 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8299 ifp = sc->bce_ifp;
8306 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8311 /* Ensure page and RX chains get refilled in low-memory situations. */
8320 if (sc->bce_link_up == TRUE)
8324 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8329 sc->bce_link_up = TRUE;
8330 bce_miibus_statchg(sc->bce_dev);
8333 mii = device_get_softc(sc->bce_miibus);
8336 if ((mii->mii_media_status & IFM_ACTIVE) &&
8337 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8340 sc->bce_link_up = TRUE;
8341 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8342 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8343 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8348 if (sc->bce_link_up == TRUE) {
8375 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8377 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8378 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8381 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8404 result = -1;
8407 if (error || !req->newptr)
8431 result = -1;
8434 if (error || !req->newptr)
8458 result = -1;
8461 if (error || !req->newptr)
8485 result = -1;
8488 if (error || !req->newptr)
8513 result = -1;
8516 if (error || !req->newptr)
8523 stats = (struct statistics_block *) sc->stats_block;
8525 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8532 sc->interrupts_rx =
8533 sc->interrupts_tx = 0;
8534 sc->tso_frames_requested =
8535 sc->tso_frames_completed =
8536 sc->tso_frames_failed = 0;
8537 sc->rx_empty_count =
8538 sc->tx_full_count = 0;
8539 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8540 sc->tx_hi_watermark = 0;
8541 sc->l2fhdr_error_count =
8542 sc->l2fhdr_error_sim_count = 0;
8543 sc->mbuf_alloc_failed_count =
8544 sc->mbuf_alloc_failed_sim_count = 0;
8545 sc->dma_map_addr_rx_failed_count =
8546 sc->dma_map_addr_tx_failed_count = 0;
8547 sc->mbuf_frag_count = 0;
8548 sc->csum_offload_tcp_udp =
8549 sc->csum_offload_ip = 0;
8550 sc->vlan_tagged_frames_rcvd =
8551 sc->vlan_tagged_frames_stripped = 0;
8552 sc->split_header_frames_rcvd =
8553 sc->split_header_tcp_frames_rcvd = 0;
8576 result = -1;
8579 if (error || !req->newptr)
8603 result = -1;
8606 if (error || !req->newptr)
8630 result = -1;
8633 if (error || !req->newptr)
8657 result = -1;
8660 if (error || !req->newptr)
8684 result = -1;
8687 if (error || !req->newptr)
8711 result = -1;
8714 if (error || !req->newptr)
8741 result = -1;
8743 if (error || (req->newptr == NULL))
8767 result = -1;
8769 if (error || (req->newptr == NULL))
8799 result = -1;
8801 if (error || (req->newptr == NULL))
8807 dev = sc->bce_dev;
8808 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8827 if (sc->nvram_buf == NULL)
8828 sc->nvram_buf = malloc(sc->bce_flash_size,
8832 if (req->oldlen == sc->bce_flash_size) {
8833 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
8834 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
8838 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
8857 if (sc->nvram_buf == NULL)
8858 sc->nvram_buf = malloc(sc->bce_flash_size,
8861 bzero(sc->nvram_buf, sc->bce_flash_size);
8863 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
8867 if (req->newlen == sc->bce_flash_size)
8868 error = bce_nvram_write(sc, 0, sc->nvram_buf,
8869 sc->bce_flash_size);
8887 result = -1;
8889 if (error || (req->newptr == NULL))
8915 result = -1;
8918 if (error || !req->newptr)
8944 ctx = device_get_sysctl_ctx(sc->bce_dev);
8945 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
8955 CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
8961 CTLFLAG_RD, &sc->l2fhdr_error_count,
8972 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
8978 CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
8983 CTLFLAG_RD, &sc->mbuf_frag_count,
8995 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9002 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9007 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9018 CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9024 CTLFLAG_RW, &sc->unexpected_attention_count,
9035 CTLFLAG_RD, &sc->rx_low_watermark,
9040 CTLFLAG_RD, &sc->rx_empty_count,
9045 CTLFLAG_RD, &sc->tx_hi_watermark,
9050 CTLFLAG_RD, &sc->tx_full_count,
9055 CTLFLAG_RD, &sc->tso_frames_requested,
9060 CTLFLAG_RD, &sc->tso_frames_completed,
9065 CTLFLAG_RD, &sc->tso_frames_failed,
9070 CTLFLAG_RD, &sc->csum_offload_ip,
9075 CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9080 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9085 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9090 CTLFLAG_RD, &sc->interrupts_rx,
9095 CTLFLAG_RD, &sc->interrupts_tx,
9101 CTLFLAG_RD, &sc->split_header_frames_rcvd,
9106 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9125 CTLFLAG_RD, &sc->stat_IfHCInOctets,
9130 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9135 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9140 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9145 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9150 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9155 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9160 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9165 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9170 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9175 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9180 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9185 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9190 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9195 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9200 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9205 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9210 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9215 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9220 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9225 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9230 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9235 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9240 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9245 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9250 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9255 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9260 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9265 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9270 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9275 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9280 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9285 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9290 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9295 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9300 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9305 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9310 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9315 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9320 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9325 CTLFLAG_RD, &sc->stat_OutXonSent,
9330 CTLFLAG_RD, &sc->stat_OutXoffSent,
9335 CTLFLAG_RD, &sc->stat_FlowControlDone,
9340 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9345 CTLFLAG_RD, &sc->stat_XoffStateEntered,
9350 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9355 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9360 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9365 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9371 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9376 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9381 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9386 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9392 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9397 CTLFLAG_RD, &sc->com_no_buffers,
9510 /* Unfreezes the controller after a freeze operation. This may not always */
9545 "-----------------------------"
9547 "-----------------------------\n");
9552 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9553 etype = ntohs(eh->evl_proto);
9556 etype = ntohs(eh->evl_encap_proto);
9562 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9566 ip = (struct ip *)(m->m_data + ehlen);
9567 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9569 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9570 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9572 switch (ip->ip_p) {
9574 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9575 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9577 ntohs(th->th_dport), ntohs(th->th_sport),
9578 (th->th_off << 2), th->th_flags,
9580 "\02SYN\01FIN", ntohs(th->th_sum));
9583 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9584 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9585 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9586 ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9587 ntohs(uh->uh_sum));
9593 BCE_PRINTF("----: Other IP protocol.\n");
9600 BCE_PRINTF("-arp: ");
9601 ah = (struct arphdr *) (m->m_data + ehlen);
9602 switch (ntohs(ah->ar_op)) {
9620 BCE_PRINTF("----: Other protocol.\n");
9624 "-----------------------------"
9625 "--------------"
9626 "-----------------------------\n");
9647 "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9648 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9650 if (mp->m_flags & M_PKTHDR) {
9651 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9652 "csum_flags = %b\n", mp->m_pkthdr.len,
9653 mp->m_flags, M_FLAG_PRINTF,
9654 mp->m_pkthdr.csum_flags, CSUM_BITS);
9657 if (mp->m_flags & M_EXT) {
9658 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9659 mp->m_ext.ext_buf, mp->m_ext.ext_size);
9660 switch (mp->m_ext.ext_type) {
9686 mp = mp->m_next;
9702 "----------------------------"
9704 "----------------------------\n");
9707 m = sc->tx_mbuf_ptr[chain_prod];
9714 "----------------------------"
9715 "----------------"
9716 "----------------------------\n");
9731 "----------------------------"
9733 "----------------------------\n");
9736 m = sc->rx_mbuf_ptr[chain_prod];
9743 "----------------------------"
9744 "----------------"
9745 "----------------------------\n");
9760 "----------------------------"
9762 "----------------------------\n");
9765 m = sc->pg_mbuf_ptr[chain_prod];
9772 "----------------------------"
9773 "----------------"
9774 "----------------------------\n");
9794 "pointer\n", idx, txbd->tx_bd_haddr_hi,
9795 txbd->tx_bd_haddr_lo);
9800 "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9801 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9802 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9804 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9811 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9818 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
9825 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
9832 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
9839 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
9846 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
9853 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
9860 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
9867 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
9870 printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
9874 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
9881 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
9906 "pointer\n", idx, rxbd->rx_bd_haddr_hi,
9907 rxbd->rx_bd_haddr_lo);
9911 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
9912 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
9913 rxbd->rx_bd_flags);
9931 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
9936 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
9937 pgbd->rx_bd_len, pgbd->rx_bd_flags);
9952 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
9953 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
9954 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
9972 "----------------------------"
9974 "----------------------------\n");
9976 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
9979 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
9982 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
9985 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
9987 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
9990 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
9993 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
9996 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
9999 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10002 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10005 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10008 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10013 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10016 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10019 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10023 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10027 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10031 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10036 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10038 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10041 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10045 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10049 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10052 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10059 "----------------------------"
10061 "----------------------------\n");
10072 "----------------------------"
10073 "----------------"
10074 "----------------------------\n");
10089 "----------------------------"
10091 "----------------------------\n");
10095 BCE_PRINTF(" ------- ---------- ---------- ---------- "
10096 "---------- ----------\n");
10222 /* Input queue to the Transmit Patch-Up Processor */
10317 "----------------------------"
10318 "----------------"
10319 "----------------------------\n");
10335 "----------------------------"
10337 "----------------------------\n");
10340 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10346 "----------------------------"
10348 "----------------------------\n");
10352 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10358 "----------------------------"
10359 "----------------"
10360 "----------------------------\n");
10376 "----------------------------"
10378 "----------------------------\n");
10381 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10389 "----------------------------"
10391 "----------------------------\n");
10395 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10401 "----------------------------"
10402 "----------------"
10403 "----------------------------\n");
10419 "----------------------------"
10421 "----------------------------\n");
10424 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10432 "----------------------------"
10434 "----------------------------\n");
10438 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10444 "----------------------------"
10445 "----------------"
10446 "----------------------------\n");
10450 if (sblk->status_rx_quick_consumer_index##arg) \
10451 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \
10452 sblk->status_rx_quick_consumer_index##arg, (u16) \
10453 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \
10457 if (sblk->status_tx_quick_consumer_index##arg) \
10458 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \
10459 sblk->status_tx_quick_consumer_index##arg, (u16) \
10460 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \
10474 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10476 sblk = sc->status_block;
10479 "----------------------------"
10481 "----------------------------\n");
10484 BCE_PRINTF(" 0x%08X - attn_bits\n",
10485 sblk->status_attn_bits);
10487 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
10488 sblk->status_attn_bits_ack);
10493 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
10504 if (sblk->status_completion_producer_index ||
10505 sblk->status_cmd_consumer_index)
10507 sblk->status_completion_producer_index,
10508 sblk->status_cmd_consumer_index);
10511 "----------------------------"
10512 "----------------"
10513 "----------------------------\n");
10517 if (sblk->arg##_lo || sblk->arg##_hi) \
10518 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \
10519 sblk->arg##_lo, #arg);
10522 if (sblk->arg) \
10524 sblk->arg, #arg);
10537 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10539 sblk = sc->stats_block;
10542 "---------------"
10544 "---------------\n");
10603 "----------------------------"
10604 "----------------"
10605 "----------------------------\n");
10620 "-----------------------------"
10622 "-----------------------------\n");
10626 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10629 val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10630 val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10631 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10634 val_hi = BCE_ADDR_HI(sc->status_block);
10635 val_lo = BCE_ADDR_LO(sc->status_block);
10636 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10639 val_hi = BCE_ADDR_HI(sc->stats_block);
10640 val_lo = BCE_ADDR_LO(sc->stats_block);
10641 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10644 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10645 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10646 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10649 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10650 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10651 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10655 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10656 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10657 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10661 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10662 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10663 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10666 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10667 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10668 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10672 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10673 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10674 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10678 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10680 (long long unsigned int) sc->interrupts_generated);
10682 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10684 (long long unsigned int) sc->interrupts_rx);
10686 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10688 (long long unsigned int) sc->interrupts_tx);
10690 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10692 (long long unsigned int) sc->phy_interrupts);
10694 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) "
10695 "status block index\n", sc->last_status_idx);
10697 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10698 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10700 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10701 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10703 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer "
10704 "byte seq index\n", sc->tx_prod_bseq);
10706 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10707 "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10709 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used "
10710 "tx_bd's\n", sc->used_tx_bd);
10712 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10713 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10715 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10716 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10718 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10719 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10721 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer "
10722 "byte seq index\n", sc->rx_prod_bseq);
10724 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/"
10725 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10727 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10728 "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10730 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free "
10731 "rx_bd's\n", sc->free_rx_bd);
10734 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer "
10735 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10737 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10738 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10740 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page "
10741 "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10744 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page "
10745 "rx_bd's\n", sc->free_pg_bd);
10747 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/"
10748 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10750 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
10751 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10753 BCE_PRINTF(" 0x%08X - (sc->bce_flags) "
10754 "bce mac flags\n", sc->bce_flags);
10756 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) "
10757 "bce phy flags\n", sc->bce_phy_flags);
10760 "----------------------------"
10761 "----------------"
10762 "----------------------------\n");
10778 "----------------------------"
10780 "----------------------------\n");
10782 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10785 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10789 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10793 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10797 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10801 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10806 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10810 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10815 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10819 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10823 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10827 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10831 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10835 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10839 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10843 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10847 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
10851 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10855 "----------------------------"
10856 "----------------"
10857 "----------------------------\n");
10860 "----------------------------"
10862 "----------------------------\n");
10871 "----------------------------"
10872 "----------------"
10873 "----------------------------\n");
10887 "----------------------------"
10889 "----------------------------\n");
10891 BCE_PRINTF("0x%08X - Shared memory base address\n",
10892 sc->bce_shmem_base);
10893 BCE_PRINTF("%s - bootcode version\n",
10894 sc->bce_bc_ver);
10897 "----------------------------"
10899 "----------------------------\n");
10908 "----------------------------"
10909 "----------------"
10910 "----------------------------\n");
10923 "----------------------------"
10925 "----------------------------\n");
10928 "----------------------------"
10929 "----------------"
10930 "----------------------------\n");
10939 "----------------------------"
10940 "----------------"
10941 "----------------------------\n");
10956 "----------------------------"
10958 "----------------------------\n");
10960 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10963 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
10967 BCE_PRINTF("0x%08X - (0x%06X) state\n",
10971 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
10975 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
10979 "----------------------------"
10980 "----------------"
10981 "----------------------------\n");
10997 "----------------------------"
10999 "----------------------------\n");
11004 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11007 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11011 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11015 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11020 "----------------------------"
11022 "----------------------------\n");
11037 "----------------------------"
11038 "----------------"
11039 "----------------------------\n");
11055 "----------------------------"
11057 "----------------------------\n");
11063 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11066 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11070 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11074 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11079 "----------------------------"
11081 "----------------------------\n");
11096 "----------------------------"
11097 "----------------"
11098 "----------------------------\n");
11114 "----------------------------"
11116 "----------------------------\n");
11122 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11125 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11129 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11133 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11138 "----------------------------"
11140 "----------------------------\n");
11155 "----------------------------"
11156 "----------------"
11157 "----------------------------\n");
11173 "----------------------------"
11175 "----------------------------\n");
11181 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11184 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11188 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11192 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11197 "----------------------------"
11199 "----------------------------\n");
11214 "----------------------------"
11215 "----------------"
11216 "----------------------------\n");
11232 "----------------------------"
11234 "----------------------------\n");
11240 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11243 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11247 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11251 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11256 "----------------------------"
11258 "----------------------------\n");
11271 "----------------------------"
11272 "----------------"
11273 "----------------------------\n");
11288 "----------------------------"
11290 "----------------------------\n");
11303 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11311 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11325 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11326 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11334 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11335 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11338 "----------------------------"
11339 "----------------"
11340 "----------------------------\n");