Lines Matching +full:0 +full:x68000
109 /* 0 = Never */
120 int l2fhdr_error_sim_control = 0;
123 int unexpected_attention_sim_control = 0;
126 int mbuf_alloc_failed_sim_control = 0;
129 int dma_map_addr_failed_sim_control = 0;
132 int bootcode_running_failure_sim_control = 0;
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
200 { 0, 0, 0, 0, NULL }
212 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
217 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
229 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
234 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
236 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
239 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
244 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
250 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
255 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
260 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
262 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
265 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
267 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
270 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
275 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
277 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
280 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
282 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
285 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
287 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
528 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
533 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
538 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
541 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
544 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
549 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
554 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
559 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
565 &bce_strict_rx_mtu, 0,
568 /* Allowable values are 0 ... 100 */
577 &bce_tx_quick_cons_trip_int, 0,
580 /* Allowable values are 0 ... 100 */
589 &bce_tx_quick_cons_trip, 0,
592 /* Allowable values are 0 ... 100 */
594 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
595 static int bce_tx_ticks_int = 0;
601 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
603 /* Allowable values are 0 ... 100 */
605 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
606 static int bce_tx_ticks = 0;
612 &bce_tx_ticks, 0, "Transmit ticks count");
623 &bce_rx_quick_cons_trip_int, 0,
635 &bce_rx_quick_cons_trip, 0,
638 /* Allowable values are 0 ... 100 */
640 /* Generate an int. if 0us have elapsed since the last received frame. */
641 static int bce_rx_ticks_int = 0;
647 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
649 /* Allowable values are 0 ... 100 */
651 /* Generate an int. if 0us have elapsed since the last received frame. */
652 static int bce_rx_ticks = 0;
658 &bce_rx_ticks, 0, "Receive ticks count");
674 u16 vid = 0, did = 0, svid = 0, sdid = 0;
689 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
690 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
699 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
700 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
721 int i = 0;
726 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
727 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
728 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
748 (bce_hdr_split == TRUE ? sc->pg_pages: 0));
756 if (i > 0) printf("|");
761 if (i > 0) printf("|");
766 if (i > 0) printf("|");
771 if (i > 0) printf("|");
778 if (i > 0) printf("|");
815 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) {
816 if (reg != 0)
821 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
822 if (reg != 0) {
823 u16 link_status = pci_read_config(dev, reg + 0x12, 2);
825 "0x%08X\n", link_status);
826 sc->link_speed = link_status & 0xf;
827 sc->link_width = (link_status >> 4) & 0x3f;
834 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
835 if (reg != 0)
840 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
841 if (reg != 0)
1011 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1013 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1020 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1022 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1037 /* 0 on success, positive value on failure. */
1045 int count, error, rc = 0, rid;
1055 sc->bce_flags = 0;
1056 sc->bce_phy_flags = 0;
1063 rid = PCIR_BAR(0);
1082 count = 0;
1083 #if 0
1091 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1096 count = 0;
1111 (bce_msi_enable >= 1) && (count == 0)) {
1113 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1116 count = 0;
1129 if (count == 0) {
1132 rid = 0;
1136 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1175 0xf0) >> 4) + 'A'), (pci_read_config(dev,
1176 PCIR_REVID, 4) & 0xf));
1204 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1209 for (int i = 0, j = 0; i < 3; i++) {
1215 sc->bce_bc_ver[j++] = (num / k) + '0';
1216 skip0 = 0;
1230 for (int i = 0; i < 30; i++) {
1243 int i = 0;
1246 for (int j = 0; j < 3; j++) {
1338 sc->bce_stats_ticks = 1000000 & 0xffff00;
1374 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1375 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0);
1399 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1410 IFM_ETHER | IFM_2500_SX, 0, NULL);
1412 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1415 IFM_ETHER | IFM_1000_SX, 0, NULL);
1417 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1420 IFM_ETHER | IFM_10_T, 0, NULL);
1422 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1424 IFM_ETHER | IFM_100_TX, 0, NULL);
1426 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1428 IFM_ETHER | IFM_1000_T, 0, NULL);
1430 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1432 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1440 if (rc != 0) {
1450 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1451 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1512 /* 0 on success, positive value on failure. */
1543 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1554 return(0);
1563 /* 0 on success, positive value on failure. */
1584 return (0);
1598 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1612 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1626 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1653 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1678 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1696 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to "
1697 "0x%08X\n", __FUNCTION__, val, offset);
1715 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1716 "0x%08X\n", __FUNCTION__, val, offset);
1736 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1738 "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1745 for (idx = 0; idx < retry_cnt; idx++) {
1747 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1754 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1763 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1764 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1785 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1786 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1788 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1789 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1796 for (idx = 0; idx < retry_cnt; idx++) {
1798 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1805 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1836 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1838 reg += 0x10;
1856 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1872 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1873 val = 0x0;
1889 return (val & 0xffff);
1916 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1918 reg += 0x10;
1936 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1960 return 0;
1984 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2035 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2045 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2057 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2079 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2083 /* 0 on success, positive value on failure. */
2089 int j, rc = 0;
2095 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2116 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2120 /* 0 on success, positive value on failure. */
2126 int j, rc = 0;
2135 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2159 /* 0 on success, positive value on failure. */
2165 int rc = 0;
2178 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2276 /* 0 on success, positive value on failure. */
2282 int j, rc = 0;
2303 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2331 /* 0 on success and the 32 bit value read, positive value on failure. */
2338 int i, rc = 0;
2361 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2379 "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2396 /* 0 on success, positive value on failure. */
2403 int j, rc = 0;
2429 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2437 "offset 0x%08X\n", __FILE__, __LINE__, offset);
2453 /* 0 on success, positive value on failure. */
2459 int j, entry_count, rc = 0;
2481 if (val & 0x40000000) {
2487 for (j = 0, flash = &flash_table[0]; j < entry_count;
2508 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2515 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2550 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2565 /* 0 on success and the data read, positive value on failure. */
2571 int rc = 0;
2576 if (buf_size == 0)
2580 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2588 extra = 0;
2590 cmd_flags = 0;
2637 else if (len32 > 0) {
2642 cmd_flags = 0;
2653 while (len32 > 4 && rc == 0) {
2654 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2690 /* 0 on success, positive value on failure. */
2698 int rc = 0;
2706 align_start = align_end = 0;
2743 written = 0;
2744 while ((written < len32) && (rc == 0)) {
2756 data_start = (written == 0) ? offset32 : page_start;
2762 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2774 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2786 cmd_flags = 0;
2791 if ((rc = bce_enable_nvram_write(sc)) != 0)
2795 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2803 i = 0;
2810 if (rc != 0)
2813 cmd_flags = 0;
2827 if (rc != 0)
2830 cmd_flags = 0;
2845 if (rc != 0)
2848 cmd_flags = 0;
2886 /* 0 on success, positive value on failure. */
2893 int rc = 0;
2900 * the magic value at offset 0.
2902 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2909 * Verify that offset 0 of the NVRAM contains
2912 magic = bce_be32toh(buf[0]);
2916 "Expected: 0x%08X, Found: 0x%08X\n",
2925 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2931 csum = ether_crc32_le(data, 0x100);
2935 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2940 csum = ether_crc32_le(data + 0x100, 0x100);
2944 "information NVRAM CRC! Expected: 0x%08X, "
3048 if (pci_get_function(sc->bce_dev) == 0) {
3050 case 0x4:
3051 case 0x5:
3052 case 0x6:
3064 case 0x1:
3065 case 0x2:
3066 case 0x4:
3158 if (sc->status_block_paddr != 0) {
3162 sc->status_block_paddr = 0;
3179 if (sc->stats_block_paddr != 0) {
3183 sc->stats_block_paddr = 0;
3201 for (i = 0; i < sc->ctx_pages; i++ ) {
3202 if (sc->ctx_paddr[i] != 0) {
3206 sc->ctx_paddr[i] = 0;
3226 for (i = 0; i < sc->tx_pages; i++ ) {
3227 if (sc->tx_bd_chain_paddr[i] != 0) {
3231 sc->tx_bd_chain_paddr[i] = 0;
3250 for (i = 0; i < sc->rx_pages; i++ ) {
3251 if (sc->rx_bd_chain_paddr[i] != 0) {
3255 sc->rx_bd_chain_paddr[i] = 0;
3275 for (i = 0; i < sc->pg_pages; i++ ) {
3276 if (sc->pg_bd_chain_paddr[i] != 0) {
3280 sc->pg_bd_chain_paddr[i] = 0;
3300 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3317 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3335 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3366 /* When the callback is used the OS will return 0 for the mapping function */
3388 *busaddr = 0;
3416 /* 0 for success, positive value for failure. */
3422 int i, error, rc = 0;
3435 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3451 0, NULL, NULL, &sc->status_tag)) {
3471 if (error || sc->status_block_paddr == 0) {
3478 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3489 0, NULL, NULL, &sc->stats_tag)) {
3508 if (error || sc->stats_block_paddr == 0) {
3515 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3520 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3521 if (sc->ctx_pages == 0)
3537 0, NULL, NULL, &sc->ctx_tag)) {
3544 for (i = 0; i < sc->ctx_pages; i++) {
3559 if (error || sc->ctx_paddr[i] == 0) {
3567 "= 0x%jX\n", __FUNCTION__, i,
3579 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3587 for (i = 0; i < sc->tx_pages; i++) {
3603 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3611 "0x%jX\n", __FUNCTION__, i,
3629 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3637 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3656 0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3663 for (i = 0; i < sc->rx_pages; i++) {
3679 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3687 "0x%jX\n", __FUNCTION__, i,
3701 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3705 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3713 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3732 0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3739 for (i = 0; i < sc->pg_pages; i++) {
3756 if (error || sc->pg_bd_chain_paddr[i] == 0) {
3764 "0x%jX\n", __FUNCTION__, i,
3773 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3781 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3835 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3857 /* 0 for success, positive value for failure. */
3862 int i, rc = 0;
3878 "0x%08X\n", msg_data);
3884 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3896 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3932 for (i = 0; i < rv2p_code_len; i += 8) {
3983 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3993 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4003 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4013 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4024 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4030 REG_WR_IND(sc, cpu_reg->inst, 0);
4099 cpu_reg.state_value_clear = 0xffffff;
4106 cpu_reg.mips_view_base = 0x8000000;
4132 cpu_reg.state_value_clear = 0xffffff;
4139 cpu_reg.mips_view_base = 0x8000000;
4149 fw.text_index = 0;
4154 fw.data_index = 0;
4159 fw.sbss_index = 0;
4164 fw.bss_index = 0;
4169 fw.rodata_index = 0;
4179 fw.text_index = 0;
4184 fw.data_index = 0;
4189 fw.sbss_index = 0;
4194 fw.bss_index = 0;
4199 fw.rodata_index = 0;
4229 cpu_reg.state_value_clear = 0xffffff;
4236 cpu_reg.mips_view_base = 0x8000000;
4246 fw.text_index = 0;
4251 fw.data_index = 0;
4256 fw.sbss_index = 0;
4261 fw.bss_index = 0;
4266 fw.rodata_index = 0;
4276 fw.text_index = 0;
4281 fw.data_index = 0;
4286 fw.sbss_index = 0;
4291 fw.bss_index = 0;
4296 fw.rodata_index = 0;
4325 cpu_reg.state_value_clear = 0xffffff;
4332 cpu_reg.mips_view_base = 0x8000000;
4342 fw.text_index = 0;
4347 fw.data_index = 0;
4352 fw.sbss_index = 0;
4357 fw.bss_index = 0;
4362 fw.rodata_index = 0;
4372 fw.text_index = 0;
4377 fw.data_index = 0;
4382 fw.sbss_index = 0;
4387 fw.bss_index = 0;
4392 fw.rodata_index = 0;
4421 cpu_reg.state_value_clear = 0xffffff;
4428 cpu_reg.mips_view_base = 0x8000000;
4438 fw.text_index = 0;
4443 fw.data_index = 0;
4448 fw.sbss_index = 0;
4453 fw.bss_index = 0;
4458 fw.rodata_index = 0;
4468 fw.text_index = 0;
4473 fw.data_index = 0;
4478 fw.sbss_index = 0;
4483 fw.bss_index = 0;
4488 fw.rodata_index = 0;
4517 cpu_reg.state_value_clear = 0xffffff;
4524 cpu_reg.mips_view_base = 0x8000000;
4534 fw.text_index = 0;
4539 fw.data_index = 0;
4544 fw.sbss_index = 0;
4549 fw.bss_index = 0;
4554 fw.rodata_index = 0;
4564 fw.text_index = 0;
4569 fw.data_index = 0;
4574 fw.sbss_index = 0;
4579 fw.bss_index = 0;
4584 fw.rodata_index = 0;
4651 rc = 0;
4670 for (i = 0; i < retry_cnt; i++) {
4676 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4683 for (i = 0; i < sc->ctx_pages; i++) {
4686 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4694 for (j = 0; j < retry_cnt; j++) {
4697 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4701 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4721 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4724 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4725 CTX_WR(sc, 0x00, offset, 0);
4746 u32 mac_lo = 0, mac_hi = 0;
4762 if ((mac_lo == 0) && (mac_hi == 0)) {
4766 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4767 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4771 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4797 val = (mac_addr[0] << 8) | mac_addr[1];
4844 sc->watchdog_timer = 0;
4848 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4857 int i, rc = 0;
4863 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4923 for (i = 0; i < 10; i++) {
4926 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4944 if (val != 0x01020304) {
4979 int rc = 0;
4998 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5022 if ((rc = bce_init_ctx(sc)) != 0)
5035 if ((rc = bce_init_nvram(sc)) != 0)
5052 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5063 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5067 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5079 /* 0 for success, positive value for failure. */
5085 int rc = 0;
5093 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5098 sc->last_status_idx = 0;
5132 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5133 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5135 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5136 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5137 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5143 #if 0
5188 reg = 0);
5192 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5248 /* 0 for success, positive value for failure. */
5256 int nsegs, error, rc = 0;
5266 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5269 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5270 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5335 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5336 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5337 rxbd->rx_bd_len = htole32(segs[0].ds_len);
5339 *prod_bseq += segs[0].ds_len;
5348 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5349 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5362 /* 0 for success, positive value for failure. */
5370 int error, nsegs, rc = 0;
5380 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5383 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5384 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5399 m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5440 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5441 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5452 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5453 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5485 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5488 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5499 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5502 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5514 /* 0 for success, positive value for failure. */
5520 int i, rc = 0;
5525 sc->tx_prod = 0;
5526 sc->tx_cons = 0;
5527 sc->tx_prod_bseq = 0;
5528 sc->used_tx_bd = 0;
5530 DBRUN(sc->tx_hi_watermark = 0);
5531 DBRUN(sc->tx_full_count = 0);
5544 for (i = 0; i < sc->tx_pages; i++) {
5551 j = 0;
5563 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5583 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5596 for (i = 0; i < sc->tx_pages; i++)
5599 sc->used_tx_bd = 0;
5626 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5641 lo_water = 0;
5645 lo_water = 0;
5651 lo_water = 0;
5657 if (hi_water > 0xf)
5658 hi_water = 0xf;
5659 else if (hi_water == 0)
5660 lo_water = 0;
5675 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5677 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5687 /* 0 for success, positive value for failure. */
5693 int i, rc = 0;
5699 sc->rx_prod = 0;
5700 sc->rx_cons = 0;
5701 sc->rx_prod_bseq = 0;
5706 for (i = 0; i < sc->rx_pages; i++) {
5713 j = 0;
5728 DBRUN(sc->rx_empty_count = 0);
5729 for (i = 0; i < sc->rx_pages; i++) {
5737 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5767 while (sc->free_rx_bd > 0) {
5782 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5807 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5820 for (i = 0; i < sc->rx_pages; i++)
5840 /* 0 for success, positive value for failure. */
5846 int i, rc = 0;
5853 sc->pg_prod = 0;
5854 sc->pg_cons = 0;
5858 DBRUN(sc->pg_empty_count = 0);
5861 for (i = 0; i < sc->pg_pages; i++) {
5868 j = 0;
5883 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5894 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5896 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5902 for (i = 0; i < sc->pg_pages; i++) {
5908 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
5933 while (sc->free_pg_bd > 0) {
5946 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5974 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
5987 for (i = 0; i < sc->pg_pages; i++)
6006 advertise = 0;
6007 fdpx = 0;
6008 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6041 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6052 /* 0 for success, positive value for failure. */
6088 error = 0;
6092 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6096 link = 0;
6110 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6116 if (fdx != 0)
6123 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6129 if (fdx != 0)
6137 if (fdx != 0)
6145 if (fdx != 0)
6153 if (fdx != 0)
6166 if (fdx != 0)
6170 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6205 if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6209 if_setbaudrate(ifp, 0);
6230 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6237 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6244 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6252 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6264 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6266 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6286 if ((if_getflags(ifp) & IFF_UP) == 0) {
6291 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6340 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6409 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6410 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6414 for (int i = 0; i < sc->rx_pages; i++)
6420 for (int i = 0; i < sc->pg_pages; i++)
6538 while (rem_len > 0) {
6560 rem_len = 0;
6622 m0->m_pkthdr.csum_flags = 0;
6632 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6642 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6723 for (int i = 0; i < sc->rx_pages; i++)
6728 for (int i = 0; i < sc->pg_pages; i++)
6733 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6734 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6773 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6774 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6784 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6795 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6796 "sw_tx_chain_cons = 0x%04X\n",
6801 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6809 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6830 "from tx_bd[0x%04X]\n", __FUNCTION__,
6852 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6857 sc->watchdog_timer = 0;
6865 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
6870 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6871 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6928 u32 ether_mtu = 0;
7021 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
7022 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
7100 int hdr_len __unused, ip_len __unused, ip_hlen = 0, tcp_hlen = 0;
7104 ip_len = 0;
7106 if (M_WRITABLE(*m_head) == 0) {
7167 ip->ip_len = 0;
7168 ip->ip_sum = 0;
7208 /* 0 for success, positive value for failure. */
7219 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7226 int i, error, nsegs, rc = 0;
7293 } else if (error != 0) {
7308 } else if (error != 0) {
7331 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7332 "prod_bseq = 0x%08X\n",
7341 for (i = 0; i < nsegs ; i++) {
7355 if (i == 0)
7412 int count = 0;
7424 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7425 "tx_prod_bseq = 0x%08X\n",
7461 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
7475 if (count == 0) {
7518 /* 0 for success, positive value for failure. */
7526 int mask, error = 0;
7547 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
7603 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7617 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7624 if_sethwassistbits(ifp, BCE_IF_HWASSIST, 0);
7626 if_sethwassistbits(ifp, 0, BCE_IF_HWASSIST);
7639 if_sethwassistbits(ifp, CSUM_TSO, 0);
7641 if_sethwassistbits(ifp, 0, CSUM_TSO);
7648 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7649 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
7658 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7662 == 0)
7663 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
7692 status = 0;
7694 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7699 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7700 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7707 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7708 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7731 bce_dump_txp_state(sc, 0);
7732 bce_dump_rxp_state(sc, 0);
7733 bce_dump_tpat_state(sc, 0);
7734 bce_dump_cp_state(sc, 0);
7735 bce_dump_com_state(sc, 0));
7739 if_setdrvflagbits(sc->bce_ifp, 0, IFF_DRV_RUNNING);
7788 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7836 "0x%08X\n", __FILE__, __LINE__,
7840 if (unexpected_attention_sim_control == 0)
7862 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7880 bce_enable_intr(sc, 0);
7905 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
7906 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
7915 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7952 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
7954 0xffffffff);
7962 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7971 "0x%08X\n", rx_mode);
7978 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8182 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8260 "(bc_state = 0x%08X)\n",
8273 "driver pulse! (bc_state = 0x%08X)\n",
8324 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8366 ack = 0;
8375 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8376 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8380 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8386 if (ack != 0)
8395 /* 0 for success, positive value for failure. */
8405 error = sysctl_handle_int(oidp, &result, 0, req);
8422 /* 0 for success, positive value for failure. */
8432 error = sysctl_handle_int(oidp, &result, 0, req);
8449 /* 0 for success, positive value for failure. */
8459 error = sysctl_handle_int(oidp, &result, 0, req);
8476 /* 0 for success, positive value for failure. */
8486 error = sysctl_handle_int(oidp, &result, 0, req);
8504 /* 0 for success, positive value for failure. */
8514 error = sysctl_handle_int(oidp, &result, 0, req);
8533 sc->interrupts_tx = 0;
8536 sc->tso_frames_failed = 0;
8538 sc->tx_full_count = 0;
8540 sc->tx_hi_watermark = 0;
8542 sc->l2fhdr_error_sim_count = 0;
8544 sc->mbuf_alloc_failed_sim_count = 0;
8546 sc->dma_map_addr_tx_failed_count = 0;
8547 sc->mbuf_frag_count = 0;
8549 sc->csum_offload_ip = 0;
8551 sc->vlan_tagged_frames_stripped = 0;
8553 sc->split_header_tcp_frames_rcvd = 0;
8556 REG_WR_IND(sc, 0x120084, 0);
8567 /* 0 for success, positive value for failure. */
8577 error = sysctl_handle_int(oidp, &result, 0, req);
8594 /* 0 for success, positive value for failure. */
8604 error = sysctl_handle_int(oidp, &result, 0, req);
8621 /* 0 for success, positive value for failure. */
8631 error = sysctl_handle_int(oidp, &result, 0, req);
8638 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8648 /* 0 for success, positive value for failure. */
8658 error = sysctl_handle_int(oidp, &result, 0, req);
8665 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8675 /* 0 for success, positive value for failure. */
8685 error = sysctl_handle_int(oidp, &result, 0, req);
8692 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8702 /* 0 for success, positive value for failure. */
8712 error = sysctl_handle_int(oidp, &result, 0, req);
8719 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8730 /* 0 for success, positive value for failure. */
8742 error = sysctl_handle_int(oidp, &result, 0, req);
8748 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8758 /* 0 for success, positive value for failure. */
8768 error = sysctl_handle_int(oidp, &result, 0, req);
8773 if (result < 0x8000) {
8775 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8776 } else if (result < 0x0280000) {
8778 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8789 /* 0 for success, positive value for failure. */
8800 error = sysctl_handle_int(oidp, &result, 0, req);
8805 if (result < 0x20) {
8809 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8819 /* 0 for success, positive errno for failure. */
8831 error = 0;
8833 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
8837 if (error == 0)
8849 /* 0 for success, positive errno for failure. */
8864 if (error == 0)
8868 error = bce_nvram_write(sc, 0, sc->nvram_buf,
8879 /* 0 for success, positive value for failure. */
8888 error = sysctl_handle_int(oidp, &result, 0, req);
8906 /* 0 for success, positive value for failure. */
8916 error = sysctl_handle_int(oidp, &result, 0, req);
8934 /* 0 for success, positive value for failure. */
8951 0, "Debug control to force l2fhdr errors");
8956 0, "Number of simulated l2_fhdr errors");
8962 0, "Number of l2_fhdr errors");
8968 0, "Debug control to force mbuf allocation failures");
8973 0, "Number of simulated mbuf cluster allocation failures");
8979 0, "Number of mbuf allocation failures");
8984 0, "Number of fragmented mbufs");
8990 0, "Debug control to force DMA mapping failures");
8996 0, "Number of simulated DMA mapping failures");
9003 0, "Number of RX DMA mapping failures");
9008 0, "Number of TX DMA mapping failures");
9014 0, "Debug control to simulate unexpected attentions");
9019 0, "Number of simulated unexpected attentions");
9025 0, "Number of unexpected attentions");
9031 0, "Debug control to force bootcode running failures");
9036 0, "Lowest level of free rx_bd's");
9046 0, "Highest level of used tx_bd's");
9112 (void *)sc, 0,
9118 (void *)sc, 0,
9176 0, "Internal MAC transmit errors");
9181 0, "Carrier sense errors");
9186 0, "Frame check sequence errors");
9191 0, "Alignment errors");
9196 0, "Single Collision Frames");
9201 0, "Multiple Collision Frames");
9206 0, "Deferred Transmissions");
9211 0, "Excessive Collisions");
9216 0, "Late Collisions");
9221 0, "Collisions");
9226 0, "Fragments");
9231 0, "Jabbers");
9236 0, "Undersize packets");
9241 0, "stat_EtherStatsOversizePkts");
9246 0, "Bytes received in 64 byte packets");
9251 0, "Bytes received in 65 to 127 byte packets");
9256 0, "Bytes received in 128 to 255 byte packets");
9261 0, "Bytes received in 256 to 511 byte packets");
9266 0, "Bytes received in 512 to 1023 byte packets");
9271 0, "Bytes received in 1024 t0 1522 byte packets");
9276 0, "Bytes received in 1523 to 9022 byte packets");
9281 0, "Bytes sent in 64 byte packets");
9286 0, "Bytes sent in 65 to 127 byte packets");
9291 0, "Bytes sent in 128 to 255 byte packets");
9296 0, "Bytes sent in 256 to 511 byte packets");
9301 0, "Bytes sent in 512 to 1023 byte packets");
9306 0, "Bytes sent in 1024 to 1522 byte packets");
9311 0, "Bytes sent in 1523 to 9022 byte packets");
9316 0, "XON pause frames receved");
9321 0, "XOFF pause frames received");
9326 0, "XON pause frames sent");
9331 0, "XOFF pause frames sent");
9336 0, "Flow control done");
9341 0, "MAC control frames received");
9346 0, "XOFF state entered");
9351 0, "Received L2 packets discarded");
9356 0, "Received packets discarded by rule");
9361 0, "Received packet FTQ discards");
9366 0, "Received packets discarded due to lack "
9372 0, "Received packets rule checker hits");
9377 0, "Received packets discarded in Catchup path");
9382 0, "Received packets discarded in FTQ in Catchup path");
9387 0, "Received packets discarded in controller "
9393 0, "Received packets rule checker hits in Catchup path");
9398 0, "Valid packets received but no RX buffers available");
9403 (void *)sc, 0,
9408 (void *)sc, 0,
9413 (void *)sc, 0,
9418 (void *)sc, 0,
9423 (void *)sc, 0,
9428 (void *)sc, 0,
9433 (void *)sc, 0,
9438 (void *)sc, 0,
9443 (void *)sc, 0,
9448 (void *)sc, 0,
9455 (void *)sc, 0,
9461 (void *)sc, 0,
9466 (void *)sc, 0,
9471 (void *)sc, 0,
9476 (void *)sc, 0,
9481 (void *)sc, 0,
9561 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9567 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9568 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9576 "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9585 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9646 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9651 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9706 for (int i = 0; i < count; i++) {
9708 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9735 for (int i = 0; i < count; i++) {
9737 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9764 for (int i = 0; i < count; i++) {
9766 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9786 int i = 0;
9790 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9793 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9798 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9799 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9800 "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9805 if (i>0)
9812 if (i>0)
9819 if (i>0)
9826 if (i>0)
9833 if (i>0)
9840 if (i>0)
9847 if (i>0)
9854 if (i>0)
9861 if (i>0)
9868 if (i>0)
9875 if (i>0)
9882 if (i>0)
9902 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
9905 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9910 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
9911 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
9927 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
9930 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
9934 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
9935 "flags = 0x%08X\n", idx,
9949 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
9950 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
9951 "tcp_udp_xsum = 0x%04X\n", idx,
9958 /* Prints out context memory info. (Only useful for CID 0 to 16.) */
9976 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
9979 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
9982 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
9985 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
9987 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
9990 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
9993 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
9996 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
9999 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10002 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10005 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10008 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10013 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10016 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10019 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10023 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10027 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10031 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10036 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10038 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10041 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10045 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10049 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10052 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10063 for (int i = 0x0; i < 0x300; i += 0x10) {
10064 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10066 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10067 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10068 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10129 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10138 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10147 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10156 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10165 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10174 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10183 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10192 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10201 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10210 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10219 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10228 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10237 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10246 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10255 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10264 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10284 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10293 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10302 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10309 cur_depth = (ctl & 0xFFC00000) >> 22;
10310 max_depth = (ctl & 0x003FF000) >> 12;
10312 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10339 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n",
10341 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10343 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10351 for (int i = 0; i < count; i++) {
10380 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n",
10383 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10386 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10394 for (int i = 0; i < count; i++) {
10423 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n",
10426 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10429 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10437 for (int i = 0; i < count; i++) {
10451 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \
10458 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \
10484 BCE_PRINTF(" 0x%08X - attn_bits\n",
10487 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
10490 BCE_PRINT_RX_CONS(0);
10491 BCE_PRINT_TX_CONS(0)
10493 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
10506 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
10518 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \
10523 BCE_PRINTF(" 0x%08X : %s\n", \
10543 " Stats Block (All Stats Not Shown Are 0) "
10626 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10631 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10636 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10641 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10646 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10651 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10657 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10663 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10668 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10674 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10678 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10682 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10686 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10690 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10694 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) "
10697 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10700 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10703 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer "
10706 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10709 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used "
10712 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10715 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10718 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10721 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer "
10724 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/"
10727 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10730 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free "
10734 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer "
10737 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10740 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page "
10744 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page "
10747 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/"
10750 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
10753 BCE_PRINTF(" 0x%08X - (sc->bce_flags) "
10756 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) "
10785 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10789 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10793 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10797 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10801 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10805 val = REG_RD(sc, 0x2004);
10806 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10807 val, 0x2004);
10810 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10814 val = REG_RD(sc, 0x2c04);
10815 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10816 val, 0x2c04);
10819 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10823 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10827 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10831 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10835 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10839 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10843 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10847 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
10851 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10864 for (int i = 0x400; i < 0x8000; i += 0x10) {
10865 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10866 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10867 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10891 BCE_PRINTF("0x%08X - Shared memory base address\n",
10901 for (int i = 0x0; i < 0x200; i += 0x10) {
10902 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10903 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
10904 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
10932 for (int i = 0x3c00; i < 0x4000; i += 0x10) {
10933 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10934 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10935 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10963 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
10967 BCE_PRINTF("0x%08X - (0x%06X) state\n",
10971 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
10975 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11001 for (int i = 0; i < 3; i++)
11003 (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11007 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11011 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11015 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11024 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11026 if (i < 0x454000 && i > 0x5ffff)
11027 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11028 "0x%08X 0x%08X\n", i,
11030 REG_RD_IND(sc, i + 0x4),
11031 REG_RD_IND(sc, i + 0x8),
11032 REG_RD_IND(sc, i + 0xC));
11059 for (int i = 0; i < 3; i++)
11061 (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11066 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11070 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11074 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11083 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11085 if (i < 0xc5400 && i > 0xdffff)
11086 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11087 "0x%08X 0x%08X\n", i,
11089 REG_RD_IND(sc, i + 0x4),
11090 REG_RD_IND(sc, i + 0x8),
11091 REG_RD_IND(sc, i + 0xC));
11118 for (int i = 0; i < 3; i++)
11120 (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11125 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11129 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11133 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11142 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11144 if (i < 0x854000 && i > 0x9ffff)
11145 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11146 "0x%08X 0x%08X\n", i,
11148 REG_RD_IND(sc, i + 0x4),
11149 REG_RD_IND(sc, i + 0x8),
11150 REG_RD_IND(sc, i + 0xC));
11177 for (int i = 0; i < 3; i++)
11179 (BCE_CP_SCRATCH + 0x10 + i * 4)));
11184 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11188 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11192 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11201 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11203 if (i < 0x185400 && i > 0x19ffff)
11204 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11205 "0x%08X 0x%08X\n", i,
11207 REG_RD_IND(sc, i + 0x4),
11208 REG_RD_IND(sc, i + 0x8),
11209 REG_RD_IND(sc, i + 0xC));
11236 for (int i = 0; i < 3; i++)
11238 (BCE_COM_SCRATCH + 0x10 + i * 4)));
11243 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11247 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11251 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11260 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11261 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11262 "0x%08X 0x%08X\n", i,
11264 REG_RD_IND(sc, i + 0x4),
11265 REG_RD_IND(sc, i + 0x8),
11266 REG_RD_IND(sc, i + 0xC));
11298 val = 0x00000001;
11303 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11306 val = 0x00000001;
11311 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11320 val = 0x68007800;
11325 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11326 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11329 val = 0x68007800;
11334 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11335 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11357 if (0) {
11361 bce_dump_txbd(sc, 0, NULL);
11362 bce_dump_rxbd(sc, 0, NULL);
11363 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11364 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11365 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11366 bce_dump_l2fhdr(sc, 0, NULL);
11369 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11370 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11371 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11377 bce_dump_txp_state(sc, 0);
11378 bce_dump_rxp_state(sc, 0);
11379 bce_dump_tpat_state(sc, 0);
11380 bce_dump_cp_state(sc, 0);
11381 bce_dump_com_state(sc, 0);
11383 bce_dump_pgbd(sc, 0, NULL);