Lines Matching defs:cpu_reg
420 struct cpu_reg *, struct fw_info *);
421 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
422 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
3969 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3976 bce_halt_cpu(sc, cpu_reg);
3979 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3989 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3999 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4009 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4019 offset = cpu_reg->spad_base +
4020 (fw->rodata_addr - cpu_reg->mips_view_base);
4030 REG_WR_IND(sc, cpu_reg->inst, 0);
4031 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4045 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4052 val = REG_RD_IND(sc, cpu_reg->mode);
4053 val &= ~cpu_reg->mode_value_halt;
4054 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4055 REG_WR_IND(sc, cpu_reg->mode, val);
4067 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4074 val = REG_RD_IND(sc, cpu_reg->mode);
4075 val |= cpu_reg->mode_value_halt;
4076 REG_WR_IND(sc, cpu_reg->mode, val);
4077 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4091 struct cpu_reg cpu_reg;
4095 cpu_reg.mode = BCE_RXP_CPU_MODE;
4096 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4097 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4098 cpu_reg.state = BCE_RXP_CPU_STATE;
4099 cpu_reg.state_value_clear = 0xffffff;
4100 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4101 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4102 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4103 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4104 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4105 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4106 cpu_reg.mips_view_base = 0x8000000;
4109 bce_start_cpu(sc, &cpu_reg);
4123 struct cpu_reg cpu_reg;
4128 cpu_reg.mode = BCE_RXP_CPU_MODE;
4129 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4130 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4131 cpu_reg.state = BCE_RXP_CPU_STATE;
4132 cpu_reg.state_value_clear = 0xffffff;
4133 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4134 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4135 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4136 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4137 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4138 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4139 cpu_reg.mips_view_base = 0x8000000;
4204 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4220 struct cpu_reg cpu_reg;
4225 cpu_reg.mode = BCE_TXP_CPU_MODE;
4226 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4227 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4228 cpu_reg.state = BCE_TXP_CPU_STATE;
4229 cpu_reg.state_value_clear = 0xffffff;
4230 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4231 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4232 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4233 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4234 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4235 cpu_reg.spad_base = BCE_TXP_SCRATCH;
4236 cpu_reg.mips_view_base = 0x8000000;
4301 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4302 bce_start_cpu(sc, &cpu_reg);
4316 struct cpu_reg cpu_reg;
4321 cpu_reg.mode = BCE_TPAT_CPU_MODE;
4322 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4323 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4324 cpu_reg.state = BCE_TPAT_CPU_STATE;
4325 cpu_reg.state_value_clear = 0xffffff;
4326 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4327 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4328 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4329 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4330 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4331 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4332 cpu_reg.mips_view_base = 0x8000000;
4397 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4398 bce_start_cpu(sc, &cpu_reg);
4412 struct cpu_reg cpu_reg;
4417 cpu_reg.mode = BCE_CP_CPU_MODE;
4418 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4419 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4420 cpu_reg.state = BCE_CP_CPU_STATE;
4421 cpu_reg.state_value_clear = 0xffffff;
4422 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4423 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4424 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4425 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4426 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4427 cpu_reg.spad_base = BCE_CP_SCRATCH;
4428 cpu_reg.mips_view_base = 0x8000000;
4493 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4494 bce_start_cpu(sc, &cpu_reg);
4508 struct cpu_reg cpu_reg;
4513 cpu_reg.mode = BCE_COM_CPU_MODE;
4514 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4515 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4516 cpu_reg.state = BCE_COM_CPU_STATE;
4517 cpu_reg.state_value_clear = 0xffffff;
4518 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4519 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4520 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4521 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4522 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4523 cpu_reg.spad_base = BCE_COM_SCRATCH;
4524 cpu_reg.mips_view_base = 0x8000000;
4589 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4590 bce_start_cpu(sc, &cpu_reg);