Lines Matching +full:phy +full:- +full:mode
116 #include "xgbe-common.h"
142 /* Rate-change complete wait/retry count */
153 /* SFP port max PHY probe retries */
257 /* Single mode, length of fiber in units of km */
261 /* Single mode, length of fiber in units of 100m */
275 * Optical specification compliance - denotes wavelength
306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
326 /* MDIO PHY reset types */
334 /* Re-driver related definitions */
354 /* PHY related configuration information */
398 /* External PHY support */
407 /* Re-driver support */
429 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
436 struct xgbe_phy_data *phy_data = pdata->phy_data;
461 i2c_op.target = phy_data->redrv_addr;
466 if ((ret == -EAGAIN) && retry--)
475 i2c_op.target = phy_data->redrv_addr;
480 if ((ret == -EAGAIN) && retry--)
488 ret = -EIO;
509 if ((ret == -EAGAIN) && retry--)
534 if ((ret == -EAGAIN) && retry--)
549 if ((ret == -EAGAIN) && retry--)
558 struct xgbe_phy_data *phy_data = pdata->phy_data;
562 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
568 i2c_op.target = phy_data->sfp_mux_address;
578 struct xgbe_phy_data *phy_data = pdata->phy_data;
582 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
586 mux_channel = 1 << phy_data->sfp_mux_channel;
588 i2c_op.target = phy_data->sfp_mux_address;
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
620 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
643 return (-ETIMEDOUT);
650 struct xgbe_phy_data *phy_data = pdata->phy_data;
653 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
654 return (-ENOTSUP);
656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
657 return (-ENOTSUP);
660 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
689 struct xgbe_phy_data *phy_data = pdata->phy_data;
697 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
699 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
702 ret = -ENOTSUP;
712 struct xgbe_phy_data *phy_data = pdata->phy_data;
715 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
716 return (-ENOTSUP);
718 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
719 return (-ENOTSUP);
722 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
751 struct xgbe_phy_data *phy_data = pdata->phy_data;
759 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
761 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
764 ret = -ENOTSUP;
774 struct xgbe_phy_data *phy_data = pdata->phy_data;
776 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
779 XGBE_ZERO_SUP(&pdata->phy);
781 if (phy_data->sfp_mod_absent) {
782 pdata->phy.speed = SPEED_UNKNOWN;
783 pdata->phy.duplex = DUPLEX_UNKNOWN;
784 pdata->phy.autoneg = AUTONEG_ENABLE;
785 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
787 XGBE_SET_SUP(&pdata->phy, Autoneg);
788 XGBE_SET_SUP(&pdata->phy, Pause);
789 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
790 XGBE_SET_SUP(&pdata->phy, TP);
791 XGBE_SET_SUP(&pdata->phy, FIBRE);
793 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
798 switch (phy_data->sfp_base) {
802 pdata->phy.speed = SPEED_100;
803 pdata->phy.duplex = DUPLEX_FULL;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
811 pdata->phy.speed = SPEED_UNKNOWN;
812 pdata->phy.duplex = DUPLEX_UNKNOWN;
813 pdata->phy.autoneg = AUTONEG_ENABLE;
814 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
815 XGBE_SET_SUP(&pdata->phy, Autoneg);
816 XGBE_SET_SUP(&pdata->phy, Pause);
817 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
818 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
820 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
821 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
822 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
824 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
825 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
830 pdata->phy.speed = SPEED_1000;
831 pdata->phy.duplex = DUPLEX_FULL;
832 pdata->phy.autoneg = AUTONEG_DISABLE;
833 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
840 pdata->phy.speed = SPEED_10000;
841 pdata->phy.duplex = DUPLEX_FULL;
842 pdata->phy.autoneg = AUTONEG_DISABLE;
843 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
844 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
845 switch (phy_data->sfp_base) {
847 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
850 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
853 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
856 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
859 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
867 pdata->phy.speed = SPEED_UNKNOWN;
868 pdata->phy.duplex = DUPLEX_UNKNOWN;
869 pdata->phy.autoneg = AUTONEG_DISABLE;
870 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
874 switch (phy_data->sfp_base) {
878 XGBE_SET_SUP(&pdata->phy, TP);
881 XGBE_SET_SUP(&pdata->phy, FIBRE);
885 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
888 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
889 phy_data->sfp_base, pdata->phy.pause_autoneg,
890 pdata->phy.advertising, pdata->phy.supported);
899 sfp_base = sfp_eeprom->base;
929 struct xgbe_phy_data *phy_data = pdata->phy_data;
931 if (phy_data->phydev)
932 phy_data->phydev = 0;
934 if (pdata->axgbe_miibus != NULL) {
935 device_delete_child(pdata->dev, pdata->axgbe_miibus);
936 pdata->axgbe_miibus = NULL;
943 struct xgbe_phy_data *phy_data = pdata->phy_data;
944 unsigned int phy_id = phy_data->phy_id;
946 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
952 /* Enable Base-T AN */
953 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
954 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
957 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
959 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
960 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
961 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
962 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
964 axgbe_printf(3, "Finisar PHY quirk in place\n");
972 struct xgbe_phy_data *phy_data = pdata->phy_data;
973 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
974 unsigned int phy_id = phy_data->phy_id;
977 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
980 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
984 /* For Bel-Fuse, use the extra AN flag */
985 pdata->an_again = 1;
987 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
994 /* Disable RGMII mode */
995 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
996 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
997 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
1000 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1001 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1004 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1008 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1009 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
1011 /* Configure SGMII-to-Copper mode */
1012 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1013 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1016 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1020 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1021 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1024 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1025 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1028 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1032 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1033 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1035 axgbe_printf(3, "BelFuse PHY quirk in place\n");
1053 struct xgbe_phy_data *phy_data = pdata->phy_data;
1057 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
1059 return (-EIO);
1062 phy_data->phy_id = (phy_reg & 0xffff) << 16;
1064 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
1066 return (-EIO);
1069 phy_data->phy_id |= (phy_reg & 0xffff);
1083 struct xgbe_phy_data *phy_data = pdata->phy_data;
1087 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
1088 phy_data->sfp_phy_avail, phy_data->phy_id);
1090 /* If we already have a PHY, just return */
1091 if (phy_data->phydev) {
1092 axgbe_printf(3, "%s: phy present already\n", __func__);
1097 pdata->an_again = 0;
1099 /* Check for the use of an external PHY */
1100 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
1102 phy_data->phydev_mode);
1106 /* For SFP, only use an external PHY if available */
1107 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1108 !phy_data->sfp_phy_avail) {
1110 phy_data->port_mode, phy_data->sfp_phy_avail);
1114 /* Set the proper MDIO mode for the PHY */
1115 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1116 phy_data->phydev_mode);
1119 phy_data->mdio_addr, phy_data->phydev_mode, ret);
1126 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
1128 phy_data->phydev = 1;
1137 struct xgbe_phy_data *phy_data = pdata->phy_data;
1141 phy_data->sfp_changed);
1142 if (!phy_data->sfp_phy_retries && !phy_data->sfp_changed)
1145 phy_data->sfp_phy_avail = 0;
1147 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1150 /* Check access to the PHY by reading CTRL1 */
1153 phy_data->sfp_phy_retries++;
1154 if (phy_data->sfp_phy_retries >= XGBE_SFP_PHY_RETRY_MAX)
1155 phy_data->sfp_phy_retries = 0;
1156 axgbe_printf(1, "%s: ext phy fail %d. retrying.\n", __func__, ret);
1160 /* Successfully accessed the PHY */
1161 phy_data->sfp_phy_avail = 1;
1162 axgbe_printf(3, "Successfully accessed External PHY\n");
1164 /* Attach external PHY to the miibus */
1165 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
1168 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
1178 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1183 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1186 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1195 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1200 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1203 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1212 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1215 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1224 struct xgbe_phy_data *phy_data = pdata->phy_data;
1225 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1229 sfp_base = sfp_eeprom->base;
1242 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1243 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1247 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1248 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1250 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1256 * 1000BASE-CX. To prevent 10G DAC cables to be recognized as
1262 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) &&
1265 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1267 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1269 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1271 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1273 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1275 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1277 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1279 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1281 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1283 phy_data->sfp_base = XGBE_SFP_BASE_100_LX10;
1285 phy_data->sfp_base = XGBE_SFP_BASE_100_FX;
1289 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1292 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1295 phy_data->sfp_base = XGBE_SFP_BASE_PX;
1300 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1305 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1307 switch (phy_data->sfp_base) {
1311 phy_data->sfp_speed = XGBE_SFP_SPEED_100;
1313 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1320 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1327 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1333 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
1334 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
1335 phy_data->sfp_tx_fault);
1346 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1352 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1358 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1364 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1376 for (cc = 0; len; buf++, len--)
1396 struct xgbe_phy_data *phy_data = pdata->phy_data;
1419 base = eeprom->base;
1424 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) {
1426 ret = -EINVAL;
1431 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) {
1433 ret = -EINVAL;
1438 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1439 phy_data->sfp_changed = 1;
1443 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1447 phy_data->sfp_changed = 0;
1458 struct xgbe_phy_data *phy_data = pdata->phy_data;
1460 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
1461 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1465 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
1474 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1478 __func__, phy_data->sfp_gpio_address);
1482 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1483 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
1485 if (prev_sfp_inputs != phy_data->port_sfp_inputs)
1487 phy_data->port_sfp_inputs);
1489 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1492 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
1513 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1523 phy_data->sfp_gpio_outputs = (gpio_ports[1] << 8) | gpio_ports[0];
1525 phy_data->sfp_gpio_polarity = (gpio_ports[1] << 8) | gpio_ports[0];
1527 phy_data->sfp_gpio_configuration = (gpio_ports[1] << 8) | gpio_ports[0];
1542 struct xgbe_phy_data *phy_data = pdata->phy_data;
1544 axgbe_printf(1, "Input port registers: 0x%x\n", phy_data->sfp_gpio_inputs);
1545 axgbe_printf(1, "Output port registers: 0x%x\n", phy_data->sfp_gpio_outputs);
1546 axgbe_printf(1, "Polarity port registers: 0x%x\n", phy_data->sfp_gpio_polarity);
1547 axgbe_printf(1, "Configuration port registers: 0x%x\n", phy_data->sfp_gpio_configuration);
1553 struct xgbe_phy_data *phy_data = pdata->phy_data;
1555 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1556 int rx_los_pos = (1 << phy_data->sfp_gpio_rx_los);
1557 int tx_fault_pos = (1 << phy_data->sfp_gpio_tx_fault);
1558 int mod_abs_pos = (1 << phy_data->sfp_gpio_mod_absent);
1577 if (phy_data->sfp_gpio_polarity) {
1583 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1593 config = phy_data->sfp_gpio_configuration;
1605 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1628 struct xgbe_phy_data *phy_data = pdata->phy_data;
1632 phy_data->sfp_mod_absent = 1;
1633 phy_data->sfp_phy_avail = 0;
1634 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1640 phy_data->sfp_rx_los = 0;
1641 phy_data->sfp_tx_fault = 0;
1642 phy_data->sfp_mod_absent = 1;
1643 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1644 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1645 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1651 struct xgbe_phy_data *phy_data = pdata->phy_data;
1652 int ret, prev_sfp_state = phy_data->sfp_mod_absent;
1660 if (phy_data->sfp_mod_absent) {
1661 if (prev_sfp_state != phy_data->sfp_mod_absent)
1688 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x "
1689 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
1690 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
1698 struct xgbe_phy_data *phy_data = pdata->phy_data;
1703 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1704 ret = -ENXIO;
1708 if (phy_data->sfp_mod_absent) {
1709 ret = -EIO;
1715 ret = -EIO;
1722 ret = -EIO;
1733 ret = -EIO;
1748 ret = -EIO;
1766 struct xgbe_phy_data *phy_data = pdata->phy_data;
1768 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1769 return (-ENXIO);
1771 if (phy_data->sfp_mod_absent)
1772 return (-EIO);
1780 struct xgbe_phy_data *phy_data = pdata->phy_data;
1782 pdata->phy.tx_pause = 0;
1783 pdata->phy.rx_pause = 0;
1785 if (!phy_data->phydev)
1788 if (pdata->phy.pause)
1789 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1791 if (pdata->phy.asym_pause)
1792 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1795 pdata->phy.tx_pause, pdata->phy.rx_pause);
1801 enum xgbe_mode mode;
1803 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1804 XGBE_SET_LP_ADV(&pdata->phy, TP);
1807 pdata->phy.pause_autoneg);
1809 /* Use external PHY to determine flow control */
1810 if (pdata->phy.pause_autoneg)
1813 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1815 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1816 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
1817 mode = XGBE_MODE_SGMII_100;
1819 /* Half-duplex not supported */
1820 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
1821 mode = XGBE_MODE_UNKNOWN;
1827 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1828 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
1829 mode = XGBE_MODE_SGMII_1000;
1831 /* Half-duplex not supported */
1832 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
1833 mode = XGBE_MODE_SGMII_1000;
1838 return (mode);
1844 enum xgbe_mode mode;
1847 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1848 XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
1854 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1856 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1859 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1861 if (pdata->phy.pause_autoneg) {
1862 /* Set flow control based on auto-negotiation result */
1863 pdata->phy.tx_pause = 0;
1864 pdata->phy.rx_pause = 0;
1867 pdata->phy.tx_pause = 1;
1868 pdata->phy.rx_pause = 1;
1871 pdata->phy.rx_pause = 1;
1873 pdata->phy.tx_pause = 1;
1877 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1878 pdata->phy.rx_pause);
1881 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
1885 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1887 return (mode);
1893 struct xgbe_phy_data *phy_data = pdata->phy_data;
1894 enum xgbe_mode mode;
1897 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1898 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1901 pdata->phy.pause_autoneg);
1903 /* Use external PHY to determine flow control */
1904 if (pdata->phy.pause_autoneg)
1911 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1913 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1917 switch (phy_data->port_mode) {
1919 mode = XGBE_MODE_KR;
1922 mode = XGBE_MODE_SFI;
1926 switch (phy_data->port_mode) {
1928 mode = XGBE_MODE_KX_1000;
1931 mode = XGBE_MODE_X;
1934 switch (phy_data->sfp_base) {
1936 if ((phy_data->phydev) &&
1937 (pdata->phy.speed == SPEED_100))
1938 mode = XGBE_MODE_SGMII_100;
1940 mode = XGBE_MODE_SGMII_1000;
1946 mode = XGBE_MODE_X;
1951 if ((phy_data->phydev) &&
1952 (pdata->phy.speed == SPEED_100))
1953 mode = XGBE_MODE_SGMII_100;
1955 mode = XGBE_MODE_SGMII_1000;
1959 mode = XGBE_MODE_UNKNOWN;
1966 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1968 return (mode);
1974 enum xgbe_mode mode;
1977 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1978 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1984 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1986 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1989 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1991 if (pdata->phy.pause_autoneg) {
1992 /* Set flow control based on auto-negotiation result */
1993 pdata->phy.tx_pause = 0;
1994 pdata->phy.rx_pause = 0;
1997 pdata->phy.tx_pause = 1;
1998 pdata->phy.rx_pause = 1;
2001 pdata->phy.rx_pause = 1;
2003 pdata->phy.tx_pause = 1;
2007 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
2008 pdata->phy.rx_pause);
2014 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
2016 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
2020 mode = XGBE_MODE_KR;
2022 mode = XGBE_MODE_KX_1000;
2024 mode = XGBE_MODE_UNKNOWN;
2030 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
2032 return (mode);
2038 switch (pdata->an_mode) {
2055 struct xgbe_phy_data *phy_data = pdata->phy_data;
2057 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
2059 /* Without a re-driver, just return current advertising */
2060 if (!phy_data->redrv)
2063 /* With the KR re-driver we need to advertise a single speed */
2068 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2071 switch (phy_data->port_mode) {
2084 if ((phy_data->phydev) &&
2085 (pdata->phy.speed == SPEED_10000))
2094 switch (phy_data->sfp_base) {
2115 struct xgbe_phy_data *phy_data = pdata->phy_data;
2125 if (!phy_data->phydev)
2134 switch (phy_data->sfp_base) {
2149 struct xgbe_phy_data *phy_data = pdata->phy_data;
2151 /* A KR re-driver will always require CL73 AN */
2152 if (phy_data->redrv)
2155 switch (phy_data->port_mode) {
2179 enum xgbe_phy_redrv_mode mode)
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2184 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2185 redrv_val = (uint16_t)mode;
2187 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
2193 enum xgbe_phy_redrv_mode mode)
2195 struct xgbe_phy_data *phy_data = pdata->phy_data;
2200 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2202 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
2210 struct xgbe_phy_data *phy_data = pdata->phy_data;
2211 enum xgbe_phy_redrv_mode mode;
2214 if (!phy_data->redrv)
2217 mode = XGBE_PHY_REDRV_MODE_CX;
2218 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2219 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2220 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2221 mode = XGBE_PHY_REDRV_MODE_SR;
2227 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
2228 if (phy_data->redrv_if)
2229 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2231 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2296 while (wait--) {
2323 struct xgbe_phy_data *phy_data = pdata->phy_data;
2328 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2330 axgbe_printf(3, "phy powered off\n");
2336 struct xgbe_phy_data *phy_data = pdata->phy_data;
2341 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
2342 phy_data->sfp_cable_len);
2344 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
2347 if (phy_data->sfp_cable_len <= 1)
2349 else if (phy_data->sfp_cable_len <= 3)
2355 phy_data->cur_mode = XGBE_MODE_SFI;
2357 axgbe_printf(3, "10GbE SFI mode set\n");
2363 struct xgbe_phy_data *phy_data = pdata->phy_data;
2370 phy_data->cur_mode = XGBE_MODE_X;
2372 axgbe_printf(3, "1GbE X mode set\n");
2378 struct xgbe_phy_data *phy_data = pdata->phy_data;
2385 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2387 axgbe_printf(2, "1GbE SGMII mode set\n");
2393 struct xgbe_phy_data *phy_data = pdata->phy_data;
2400 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2402 axgbe_printf(3, "100MbE SGMII mode set\n");
2408 struct xgbe_phy_data *phy_data = pdata->phy_data;
2415 phy_data->cur_mode = XGBE_MODE_KR;
2417 axgbe_printf(3, "10GbE KR mode set\n");
2423 struct xgbe_phy_data *phy_data = pdata->phy_data;
2430 phy_data->cur_mode = XGBE_MODE_KX_2500;
2432 axgbe_printf(3, "2.5GbE KX mode set\n");
2438 struct xgbe_phy_data *phy_data = pdata->phy_data;
2445 phy_data->cur_mode = XGBE_MODE_KX_1000;
2447 axgbe_printf(3, "1GbE KX mode set\n");
2453 struct xgbe_phy_data *phy_data = pdata->phy_data;
2455 return (phy_data->cur_mode);
2461 struct xgbe_phy_data *phy_data = pdata->phy_data;
2463 /* No switching if not 10GBase-T */
2464 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2486 /* If we are in KR switch to KX, and vice-versa */
2499 struct xgbe_phy_data *phy_data = pdata->phy_data;
2501 switch (phy_data->port_mode) {
2513 /* No switching, so just return current mode */
2557 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2596 struct xgbe_phy_data *phy_data = pdata->phy_data;
2598 switch (phy_data->port_mode) {
2618 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2620 switch (mode) {
2650 struct xgbe_phy_data *phy_data = pdata->phy_data;
2652 switch (pdata->phy.speed) {
2654 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2655 ifmr->ifm_active |= IFM_10G_KR;
2656 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
2657 ifmr->ifm_active |= IFM_10G_T;
2658 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
2659 ifmr->ifm_active |= IFM_10G_KR;
2660 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2661 ifmr->ifm_active |= IFM_10G_SFI;
2663 ifmr->ifm_active |= IFM_OTHER;
2666 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
2667 ifmr->ifm_active |= IFM_2500_KX;
2669 ifmr->ifm_active |= IFM_OTHER;
2672 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2673 ifmr->ifm_active |= IFM_1000_KX;
2674 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
2675 ifmr->ifm_active |= IFM_1000_T;
2677 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
2678 ifmr->ifm_active |= IFM_1000_SX;
2679 ifmr->ifm_active |= IFM_1000_LX;
2680 ifmr->ifm_active |= IFM_1000_CX;
2682 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2683 ifmr->ifm_active |= IFM_1000_SGMII;
2685 ifmr->ifm_active |= IFM_OTHER;
2688 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
2689 ifmr->ifm_active |= IFM_100_T;
2690 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2691 ifmr->ifm_active |= IFM_100_SGMII;
2693 ifmr->ifm_active |= IFM_OTHER;
2696 ifmr->ifm_active |= IFM_OTHER;
2697 axgbe_printf(1, "Unknown mode detected\n");
2703 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
2707 if (pdata->phy.autoneg == AUTONEG_ENABLE)
2712 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2713 if (cur_mode == mode)
2721 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2724 switch (mode) {
2726 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2729 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2737 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2740 axgbe_printf(3, "%s: check mode %d\n", __func__, mode);
2741 switch (mode) {
2743 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2746 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2749 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2752 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2760 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2762 struct xgbe_phy_data *phy_data = pdata->phy_data;
2764 switch (mode) {
2766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2768 return (xgbe_phy_check_mode(pdata, mode,
2769 XGBE_ADV(&pdata->phy, 1000baseX_Full)));
2771 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2773 return (xgbe_phy_check_mode(pdata, mode,
2774 XGBE_ADV(&pdata->phy, 100baseT_Full)));
2776 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2778 return (xgbe_phy_check_mode(pdata, mode,
2779 XGBE_ADV(&pdata->phy, 1000baseT_Full)));
2781 if (phy_data->sfp_mod_absent)
2783 return (xgbe_phy_check_mode(pdata, mode,
2784 XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
2785 XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
2786 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
2787 XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
2788 XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
2795 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2798 switch (mode) {
2800 return (xgbe_phy_check_mode(pdata, mode,
2801 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
2808 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2811 switch (mode) {
2813 return (xgbe_phy_check_mode(pdata, mode,
2814 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
2816 return (xgbe_phy_check_mode(pdata, mode,
2817 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
2824 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2828 switch (phy_data->port_mode) {
2830 return (xgbe_phy_use_bp_mode(pdata, mode));
2832 return (xgbe_phy_use_bp_2500_mode(pdata, mode));
2835 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
2838 return (xgbe_phy_use_baset_mode(pdata, mode));
2841 return (xgbe_phy_use_basex_mode(pdata, mode));
2843 return (xgbe_phy_use_sfp_mode(pdata, mode));
2855 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2857 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2872 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2874 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2886 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100) ||
2887 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2889 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2890 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2892 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2926 struct xgbe_phy_data *phy_data = pdata->phy_data;
2928 switch (phy_data->port_mode) {
2952 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
2953 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2954 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2959 pdata->phy.link = 0;
2961 pdata->phy.link = 1;
2963 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
2982 if (AUTONEG_ENABLE == pdata->phy.autoneg) {
2983 if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
2984 pdata->phy.supported == SUPPORTED_1000baseT_Full) {
2985 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2990 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
3001 return (-ENOLINK);
3004 if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
3005 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);
3006 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
3007 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);
3012 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
3016 if (pdata->phy.supported == SUPPORTED_Autoneg)
3017 XGBE_SET_ADV(&pdata->phy, Autoneg);
3019 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
3025 pdata->phy.speed = SPEED_10;
3026 pdata->phy.duplex = DUPLEX_HALF;
3027 pdata->phy.pause = 0;
3028 pdata->phy.asym_pause = 0;
3035 pdata->phy.speed = SPEED_1000;
3038 pdata->phy.duplex = DUPLEX_FULL;
3041 pdata->phy.speed = SPEED_100;
3044 pdata->phy.duplex = DUPLEX_FULL;
3047 pdata->phy.duplex = DUPLEX_FULL;
3049 if (pdata->phy.duplex == DUPLEX_FULL) {
3050 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
3051 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
3054 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
3059 pdata->phy.duplex = DUPLEX_FULL;
3061 pdata->phy.duplex = DUPLEX_HALF;
3064 pdata->phy.speed = SPEED_1000;
3066 pdata->phy.speed = SPEED_100;
3068 pdata->phy.speed = SPEED_10;
3070 pdata->phy.pause = 0;
3071 pdata->phy.asym_pause = 0;
3073 "autoneg %#x\n", __func__, pdata->phy.speed,
3074 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3083 struct xgbe_phy_data *phy_data = pdata->phy_data;
3086 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
3088 phy_data->rrc_count);
3089 phy_data->rrc_count = 0;
3090 if (pdata->link_workaround) {
3093 axgbe_error("Error resetting phy\n");
3102 struct xgbe_phy_data *phy_data = pdata->phy_data;
3109 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
3111 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3114 if (phy_data->sfp_changed) {
3120 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
3122 __func__, phy_data->sfp_mod_absent,
3123 phy_data->sfp_rx_los);
3125 if (!phy_data->sfp_mod_absent) {
3133 if (phy_data->phydev || phy_data->port_mode != XGBE_PORT_MODE_SFP) {
3134 if (pdata->axgbe_miibus == NULL) {
3139 mii = device_get_softc(pdata->axgbe_miibus);
3149 "autoneg %#x\n", __func__, pdata->phy.speed,
3150 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3151 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
3154 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
3157 if (pdata->phy.link)
3183 struct xgbe_phy_data *phy_data = pdata->phy_data;
3185 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
3186 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
3187 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3189 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3191 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3193 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3195 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3198 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
3199 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
3200 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
3201 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
3203 phy_data->sfp_gpio_mod_absent);
3205 phy_data->sfp_gpio_rate_select);
3211 struct xgbe_phy_data *phy_data = pdata->phy_data;
3214 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
3215 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
3219 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
3220 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
3221 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
3224 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
3225 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
3238 struct xgbe_phy_data *phy_data = pdata->phy_data;
3241 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3245 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3253 struct xgbe_phy_data *phy_data = pdata->phy_data;
3259 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3271 if (phy_data->mdio_reset_gpio < 8)
3272 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3274 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3277 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3283 if (phy_data->mdio_reset_gpio < 8)
3284 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3286 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3289 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3298 struct xgbe_phy_data *phy_data = pdata->phy_data;
3301 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3308 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3310 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3321 if (!phy_data->redrv)
3324 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3327 switch (phy_data->redrv_model) {
3329 if (phy_data->redrv_lane > 3)
3333 if (phy_data->redrv_lane > 1)
3346 struct xgbe_phy_data *phy_data = pdata->phy_data;
3348 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3351 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3352 switch (phy_data->mdio_reset) {
3359 phy_data->mdio_reset);
3360 return (-EINVAL);
3363 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3364 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3365 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
3366 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3368 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3369 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3378 struct xgbe_phy_data *phy_data = pdata->phy_data;
3380 switch (phy_data->port_mode) {
3382 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3383 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3387 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3391 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3392 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3396 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3400 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3401 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3402 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3406 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3407 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3408 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3412 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3416 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3417 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3418 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3431 struct xgbe_phy_data *phy_data = pdata->phy_data;
3433 switch (phy_data->port_mode) {
3436 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3444 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3448 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3462 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3464 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3473 struct xgbe_phy_data *phy_data = pdata->phy_data;
3476 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3478 if (!pdata->sysctl_an_cdr_workaround)
3481 if (!phy_data->phy_cdr_notrack)
3484 DELAY(phy_data->phy_cdr_delay + 500);
3489 phy_data->phy_cdr_notrack = 0;
3497 struct xgbe_phy_data *phy_data = pdata->phy_data;
3500 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3502 if (!pdata->sysctl_an_cdr_workaround)
3505 if (phy_data->phy_cdr_notrack)
3513 phy_data->phy_cdr_notrack = 1;
3519 if (!pdata->sysctl_an_cdr_track_early)
3526 if (pdata->sysctl_an_cdr_track_early)
3533 struct xgbe_phy_data *phy_data = pdata->phy_data;
3535 switch (pdata->an_mode) {
3538 if (phy_data->cur_mode != XGBE_MODE_KR)
3543 switch (pdata->an_result) {
3548 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3549 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3551 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3563 struct xgbe_phy_data *phy_data = pdata->phy_data;
3565 switch (pdata->an_mode) {
3568 if (phy_data->cur_mode != XGBE_MODE_KR)
3581 struct xgbe_phy_data *phy_data = pdata->phy_data;
3583 /* If we have an external PHY, free it */
3593 /* Power off the PHY */
3597 pdata->i2c_if.i2c_stop(pdata);
3603 struct xgbe_phy_data *phy_data = pdata->phy_data;
3607 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
3610 ret = pdata->i2c_if.i2c_start(pdata);
3616 /* Set the proper MDIO mode for the re-driver */
3617 if (phy_data->redrv && !phy_data->redrv_if) {
3618 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3622 phy_data->redrv_addr);
3627 /* Start in highest supported mode */
3628 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3634 switch (phy_data->port_mode) {
3636 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3645 phy_data->sfp_phy_retries = 0;
3652 /* If we have an external PHY, start it */
3655 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret);
3663 pdata->i2c_if.i2c_stop(pdata);
3671 struct xgbe_phy_data *phy_data = pdata->phy_data;
3675 /* Reset by power cycling the PHY */
3676 cur_mode = phy_data->cur_mode;
3680 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode);
3681 if (!phy_data->phydev) {
3686 /* Reset the external PHY */
3706 pdata = &sc->pdata;
3709 mtx_lock_spin(&pdata->mdio_mutex);
3710 mii = device_get_softc(pdata->axgbe_miibus);
3712 mii->mii_media_active, mii->mii_media_status);
3714 ifmr->ifm_active = mii->mii_media_active;
3715 ifmr->ifm_status = mii->mii_media_status;
3716 mtx_unlock_spin(&pdata->mdio_mutex);
3729 pdata = &sc->pdata;
3732 mtx_lock_spin(&pdata->mdio_mutex);
3733 mii = device_get_softc(pdata->axgbe_miibus);
3734 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3737 mtx_unlock_spin(&pdata->mdio_mutex);
3745 if (pdata->axgbe_miibus != NULL)
3746 device_delete_child(pdata->dev, pdata->axgbe_miibus);
3749 free(pdata->phy_data, M_AXGBE);
3760 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF);
3765 return (-ENODEV);
3769 ret = pdata->i2c_if.i2c_init(pdata);
3774 pdata->phy_data = phy_data;
3776 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3777 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3778 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3779 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3780 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3782 pdata->mdio_addr = phy_data->mdio_addr;
3783 DBGPR("port mode=%u\n", phy_data->port_mode);
3784 DBGPR("port id=%u\n", phy_data->port_id);
3785 DBGPR("port speeds=%#x\n", phy_data->port_speeds);
3786 DBGPR("conn type=%u\n", phy_data->conn_type);
3787 DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
3789 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3790 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3791 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3792 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3793 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3795 if (phy_data->redrv) {
3797 DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
3798 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
3799 DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
3800 DBGPR("redrv model=%u\n", phy_data->redrv_model);
3804 phy_data->redrv_addr, phy_data->redrv_if);
3807 axgbe_error("phy mode/connection mismatch "
3808 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
3809 return (-EINVAL);
3812 /* Validate the mode requested */
3814 axgbe_error("phy mode/speed mismatch "
3815 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
3816 return (-EINVAL);
3826 /* Validate the re-driver information */
3828 axgbe_error("phy re-driver settings error\n");
3829 return (-EINVAL);
3831 pdata->kr_redrv = phy_data->redrv;
3833 /* Indicate current mode is unknown */
3834 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3837 XGBE_ZERO_SUP(&pdata->phy);
3839 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
3840 switch (phy_data->port_mode) {
3843 XGBE_SET_SUP(&pdata->phy, Autoneg);
3844 XGBE_SET_SUP(&pdata->phy, Pause);
3845 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3846 XGBE_SET_SUP(&pdata->phy, Backplane);
3847 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3848 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
3849 phy_data->start_mode = XGBE_MODE_KX_1000;
3851 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3852 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
3853 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3854 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3855 phy_data->start_mode = XGBE_MODE_KR;
3858 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3861 XGBE_SET_SUP(&pdata->phy, Pause);
3862 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3863 XGBE_SET_SUP(&pdata->phy, Backplane);
3864 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
3865 phy_data->start_mode = XGBE_MODE_KX_2500;
3867 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3870 /* MDIO 1GBase-T support */
3872 XGBE_SET_SUP(&pdata->phy, Autoneg);
3873 XGBE_SET_SUP(&pdata->phy, Pause);
3874 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3875 XGBE_SET_SUP(&pdata->phy, TP);
3876 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3877 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3878 phy_data->start_mode = XGBE_MODE_SGMII_100;
3880 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3881 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3882 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3885 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3888 /* MDIO Base-X support */
3890 XGBE_SET_SUP(&pdata->phy, Autoneg);
3891 XGBE_SET_SUP(&pdata->phy, Pause);
3892 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3893 XGBE_SET_SUP(&pdata->phy, FIBRE);
3894 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
3895 phy_data->start_mode = XGBE_MODE_X;
3897 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3900 /* MDIO NBase-T support */
3902 XGBE_SET_SUP(&pdata->phy, Autoneg);
3903 XGBE_SET_SUP(&pdata->phy, Pause);
3904 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3905 XGBE_SET_SUP(&pdata->phy, TP);
3906 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3907 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3908 phy_data->start_mode = XGBE_MODE_SGMII_100;
3910 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3911 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3912 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3914 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3915 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
3916 phy_data->start_mode = XGBE_MODE_KX_2500;
3919 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3922 /* 10GBase-T support */
3924 XGBE_SET_SUP(&pdata->phy, Autoneg);
3925 XGBE_SET_SUP(&pdata->phy, Pause);
3926 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3927 XGBE_SET_SUP(&pdata->phy, TP);
3928 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3929 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3930 phy_data->start_mode = XGBE_MODE_SGMII_100;
3932 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3933 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3934 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3936 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3937 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
3938 phy_data->start_mode = XGBE_MODE_KR;
3941 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3944 /* 10GBase-R support */
3946 XGBE_SET_SUP(&pdata->phy, Autoneg);
3947 XGBE_SET_SUP(&pdata->phy, Pause);
3948 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3949 XGBE_SET_SUP(&pdata->phy, FIBRE);
3950 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
3951 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
3952 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
3953 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
3954 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3955 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3956 phy_data->start_mode = XGBE_MODE_SFI;
3958 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3963 XGBE_SET_SUP(&pdata->phy, Autoneg);
3964 XGBE_SET_SUP(&pdata->phy, Pause);
3965 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3966 XGBE_SET_SUP(&pdata->phy, TP);
3967 XGBE_SET_SUP(&pdata->phy, FIBRE);
3968 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3969 phy_data->start_mode = XGBE_MODE_SGMII_100;
3970 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3971 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3972 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3973 phy_data->start_mode = XGBE_MODE_SFI;
3975 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3978 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__,
3979 phy_data->start_mode, phy_data->phydev_mode,
3980 pdata->phy.advertising);
3983 return (-EINVAL);
3986 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__,
3987 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3989 DBGPR("%s: conn type %d mode %d\n", __func__,
3990 phy_data->conn_type, phy_data->phydev_mode);
3991 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3992 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3993 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3994 phy_data->phydev_mode);
3997 phy_data->mdio_addr, phy_data->phydev_mode);
3998 return (-EINVAL);
4002 if (phy_data->redrv && !phy_data->redrv_if) {
4003 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
4007 phy_data->redrv_addr);
4008 return (-EINVAL);
4012 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
4014 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
4015 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
4018 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
4022 return (-EINVAL);
4034 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
4036 phy_impl->init = xgbe_phy_init;
4037 phy_impl->exit = xgbe_phy_exit;
4039 phy_impl->reset = xgbe_phy_reset;
4040 phy_impl->start = xgbe_phy_start;
4041 phy_impl->stop = xgbe_phy_stop;
4043 phy_impl->link_status = xgbe_phy_link_status;
4045 phy_impl->valid_speed = xgbe_phy_valid_speed;
4047 phy_impl->use_mode = xgbe_phy_use_mode;
4048 phy_impl->set_mode = xgbe_phy_set_mode;
4049 phy_impl->get_mode = xgbe_phy_get_mode;
4050 phy_impl->switch_mode = xgbe_phy_switch_mode;
4051 phy_impl->cur_mode = xgbe_phy_cur_mode;
4052 phy_impl->get_type = xgbe_phy_get_type;
4054 phy_impl->an_mode = xgbe_phy_an_mode;
4056 phy_impl->an_config = xgbe_phy_an_config;
4058 phy_impl->an_advertising = xgbe_phy_an_advertising;
4060 phy_impl->an_outcome = xgbe_phy_an_outcome;
4062 phy_impl->an_pre = xgbe_phy_an_pre;
4063 phy_impl->an_post = xgbe_phy_an_post;
4065 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
4066 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
4068 phy_impl->module_info = xgbe_phy_module_info;
4069 phy_impl->module_eeprom = xgbe_phy_module_eeprom;