Lines Matching defs:phy_data
436 struct xgbe_phy_data *phy_data = pdata->phy_data;
461 i2c_op.target = phy_data->redrv_addr;
475 i2c_op.target = phy_data->redrv_addr;
558 struct xgbe_phy_data *phy_data = pdata->phy_data;
562 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
568 i2c_op.target = phy_data->sfp_mux_address;
578 struct xgbe_phy_data *phy_data = pdata->phy_data;
582 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
586 mux_channel = 1 << phy_data->sfp_mux_channel;
588 i2c_op.target = phy_data->sfp_mux_address;
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
620 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
650 struct xgbe_phy_data *phy_data = pdata->phy_data;
653 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
689 struct xgbe_phy_data *phy_data = pdata->phy_data;
697 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
699 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
712 struct xgbe_phy_data *phy_data = pdata->phy_data;
715 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
718 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
751 struct xgbe_phy_data *phy_data = pdata->phy_data;
759 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
761 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
774 struct xgbe_phy_data *phy_data = pdata->phy_data;
776 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
781 if (phy_data->sfp_mod_absent) {
798 switch (phy_data->sfp_base) {
818 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
821 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
824 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
844 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
845 switch (phy_data->sfp_base) {
874 switch (phy_data->sfp_base) {
889 phy_data->sfp_base, pdata->phy.pause_autoneg,
929 struct xgbe_phy_data *phy_data = pdata->phy_data;
931 if (phy_data->phydev)
932 phy_data->phydev = 0;
943 struct xgbe_phy_data *phy_data = pdata->phy_data;
944 unsigned int phy_id = phy_data->phy_id;
946 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
953 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
954 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
959 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
960 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
961 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
962 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
972 struct xgbe_phy_data *phy_data = pdata->phy_data;
973 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
974 unsigned int phy_id = phy_data->phy_id;
977 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
995 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
996 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
997 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
1000 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1001 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1004 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1008 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1009 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
1012 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1013 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1016 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1020 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1021 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1024 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1025 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1028 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1032 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1033 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1053 struct xgbe_phy_data *phy_data = pdata->phy_data;
1057 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
1062 phy_data->phy_id = (phy_reg & 0xffff) << 16;
1064 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
1069 phy_data->phy_id |= (phy_reg & 0xffff);
1083 struct xgbe_phy_data *phy_data = pdata->phy_data;
1087 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
1088 phy_data->sfp_phy_avail, phy_data->phy_id);
1091 if (phy_data->phydev) {
1100 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
1102 phy_data->phydev_mode);
1107 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1108 !phy_data->sfp_phy_avail) {
1110 phy_data->port_mode, phy_data->sfp_phy_avail);
1115 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1116 phy_data->phydev_mode);
1119 phy_data->mdio_addr, phy_data->phydev_mode, ret);
1126 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
1128 phy_data->phydev = 1;
1137 struct xgbe_phy_data *phy_data = pdata->phy_data;
1141 phy_data->sfp_changed);
1142 if (!phy_data->sfp_phy_retries && !phy_data->sfp_changed)
1145 phy_data->sfp_phy_avail = 0;
1147 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1153 phy_data->sfp_phy_retries++;
1154 if (phy_data->sfp_phy_retries >= XGBE_SFP_PHY_RETRY_MAX)
1155 phy_data->sfp_phy_retries = 0;
1161 phy_data->sfp_phy_avail = 1;
1176 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1178 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1183 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1186 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1193 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1195 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1200 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1203 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1210 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1212 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1215 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1224 struct xgbe_phy_data *phy_data = pdata->phy_data;
1225 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1242 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1243 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1247 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1248 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1250 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1262 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) &&
1265 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1267 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1269 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1271 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1273 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1275 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1277 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1279 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1281 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1283 phy_data->sfp_base = XGBE_SFP_BASE_100_LX10;
1285 phy_data->sfp_base = XGBE_SFP_BASE_100_FX;
1289 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1292 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1295 phy_data->sfp_base = XGBE_SFP_BASE_PX;
1300 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1305 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1307 switch (phy_data->sfp_base) {
1311 phy_data->sfp_speed = XGBE_SFP_SPEED_100;
1313 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1320 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1327 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1333 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
1334 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
1335 phy_data->sfp_tx_fault);
1396 struct xgbe_phy_data *phy_data = pdata->phy_data;
1438 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1439 phy_data->sfp_changed = 1;
1443 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1447 phy_data->sfp_changed = 0;
1458 struct xgbe_phy_data *phy_data = pdata->phy_data;
1460 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
1461 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1465 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
1474 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1478 __func__, phy_data->sfp_gpio_address);
1482 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1483 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
1485 if (prev_sfp_inputs != phy_data->port_sfp_inputs)
1487 phy_data->port_sfp_inputs);
1489 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1492 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
1513 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1523 phy_data->sfp_gpio_outputs = (gpio_ports[1] << 8) | gpio_ports[0];
1525 phy_data->sfp_gpio_polarity = (gpio_ports[1] << 8) | gpio_ports[0];
1527 phy_data->sfp_gpio_configuration = (gpio_ports[1] << 8) | gpio_ports[0];
1542 struct xgbe_phy_data *phy_data = pdata->phy_data;
1544 axgbe_printf(1, "Input port registers: 0x%x\n", phy_data->sfp_gpio_inputs);
1545 axgbe_printf(1, "Output port registers: 0x%x\n", phy_data->sfp_gpio_outputs);
1546 axgbe_printf(1, "Polarity port registers: 0x%x\n", phy_data->sfp_gpio_polarity);
1547 axgbe_printf(1, "Configuration port registers: 0x%x\n", phy_data->sfp_gpio_configuration);
1553 struct xgbe_phy_data *phy_data = pdata->phy_data;
1555 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1556 int rx_los_pos = (1 << phy_data->sfp_gpio_rx_los);
1557 int tx_fault_pos = (1 << phy_data->sfp_gpio_tx_fault);
1558 int mod_abs_pos = (1 << phy_data->sfp_gpio_mod_absent);
1577 if (phy_data->sfp_gpio_polarity) {
1583 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1593 config = phy_data->sfp_gpio_configuration;
1605 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1628 struct xgbe_phy_data *phy_data = pdata->phy_data;
1632 phy_data->sfp_mod_absent = 1;
1633 phy_data->sfp_phy_avail = 0;
1634 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1638 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1640 phy_data->sfp_rx_los = 0;
1641 phy_data->sfp_tx_fault = 0;
1642 phy_data->sfp_mod_absent = 1;
1643 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1644 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1645 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1651 struct xgbe_phy_data *phy_data = pdata->phy_data;
1652 int ret, prev_sfp_state = phy_data->sfp_mod_absent;
1660 if (phy_data->sfp_mod_absent) {
1661 if (prev_sfp_state != phy_data->sfp_mod_absent)
1676 xgbe_phy_sfp_reset(phy_data);
1698 struct xgbe_phy_data *phy_data = pdata->phy_data;
1703 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1708 if (phy_data->sfp_mod_absent) {
1766 struct xgbe_phy_data *phy_data = pdata->phy_data;
1768 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1771 if (phy_data->sfp_mod_absent)
1780 struct xgbe_phy_data *phy_data = pdata->phy_data;
1785 if (!phy_data->phydev)
1893 struct xgbe_phy_data *phy_data = pdata->phy_data;
1917 switch (phy_data->port_mode) {
1926 switch (phy_data->port_mode) {
1934 switch (phy_data->sfp_base) {
1936 if ((phy_data->phydev) &&
1951 if ((phy_data->phydev) &&
2055 struct xgbe_phy_data *phy_data = pdata->phy_data;
2060 if (!phy_data->redrv)
2071 switch (phy_data->port_mode) {
2084 if ((phy_data->phydev) &&
2094 switch (phy_data->sfp_base) {
2115 struct xgbe_phy_data *phy_data = pdata->phy_data;
2125 if (!phy_data->phydev)
2132 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
2134 switch (phy_data->sfp_base) {
2149 struct xgbe_phy_data *phy_data = pdata->phy_data;
2152 if (phy_data->redrv)
2155 switch (phy_data->port_mode) {
2171 return (xgbe_phy_an_sfp_mode(phy_data));
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2184 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2187 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
2195 struct xgbe_phy_data *phy_data = pdata->phy_data;
2200 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2210 struct xgbe_phy_data *phy_data = pdata->phy_data;
2214 if (!phy_data->redrv)
2218 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2219 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2220 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2227 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
2228 if (phy_data->redrv_if)
2323 struct xgbe_phy_data *phy_data = pdata->phy_data;
2328 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2336 struct xgbe_phy_data *phy_data = pdata->phy_data;
2341 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
2342 phy_data->sfp_cable_len);
2344 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
2347 if (phy_data->sfp_cable_len <= 1)
2349 else if (phy_data->sfp_cable_len <= 3)
2355 phy_data->cur_mode = XGBE_MODE_SFI;
2363 struct xgbe_phy_data *phy_data = pdata->phy_data;
2370 phy_data->cur_mode = XGBE_MODE_X;
2378 struct xgbe_phy_data *phy_data = pdata->phy_data;
2385 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2393 struct xgbe_phy_data *phy_data = pdata->phy_data;
2400 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2408 struct xgbe_phy_data *phy_data = pdata->phy_data;
2415 phy_data->cur_mode = XGBE_MODE_KR;
2423 struct xgbe_phy_data *phy_data = pdata->phy_data;
2430 phy_data->cur_mode = XGBE_MODE_KX_2500;
2438 struct xgbe_phy_data *phy_data = pdata->phy_data;
2445 phy_data->cur_mode = XGBE_MODE_KX_1000;
2453 struct xgbe_phy_data *phy_data = pdata->phy_data;
2455 return (phy_data->cur_mode);
2461 struct xgbe_phy_data *phy_data = pdata->phy_data;
2464 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2499 struct xgbe_phy_data *phy_data = pdata->phy_data;
2501 switch (phy_data->port_mode) {
2521 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2534 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2551 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2557 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2596 struct xgbe_phy_data *phy_data = pdata->phy_data;
2598 switch (phy_data->port_mode) {
2606 return (xgbe_phy_get_baset_mode(phy_data, speed));
2609 return (xgbe_phy_get_basex_mode(phy_data, speed));
2611 return (xgbe_phy_get_sfp_mode(phy_data, speed));
2650 struct xgbe_phy_data *phy_data = pdata->phy_data;
2654 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2656 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
2658 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
2660 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2666 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
2672 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2674 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
2677 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
2682 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2688 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
2690 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2762 struct xgbe_phy_data *phy_data = pdata->phy_data;
2766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2771 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2776 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2781 if (phy_data->sfp_mod_absent)
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2828 switch (phy_data->port_mode) {
2850 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2855 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2857 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2864 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2872 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2874 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2881 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2886 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100) ||
2887 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2889 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2890 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2892 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2926 struct xgbe_phy_data *phy_data = pdata->phy_data;
2928 switch (phy_data->port_mode) {
2936 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed));
2939 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed));
2941 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed));
3083 struct xgbe_phy_data *phy_data = pdata->phy_data;
3086 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
3088 phy_data->rrc_count);
3089 phy_data->rrc_count = 0;
3102 struct xgbe_phy_data *phy_data = pdata->phy_data;
3109 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
3114 if (phy_data->sfp_changed) {
3120 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
3122 __func__, phy_data->sfp_mod_absent,
3123 phy_data->sfp_rx_los);
3125 if (!phy_data->sfp_mod_absent) {
3133 if (phy_data->phydev || phy_data->port_mode != XGBE_PORT_MODE_SFP) {
3183 struct xgbe_phy_data *phy_data = pdata->phy_data;
3185 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
3187 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3189 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3191 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3193 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3195 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3198 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
3199 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
3200 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
3201 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
3203 phy_data->sfp_gpio_mod_absent);
3205 phy_data->sfp_gpio_rate_select);
3211 struct xgbe_phy_data *phy_data = pdata->phy_data;
3219 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
3220 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
3221 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
3224 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
3225 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
3238 struct xgbe_phy_data *phy_data = pdata->phy_data;
3241 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3245 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3253 struct xgbe_phy_data *phy_data = pdata->phy_data;
3259 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3271 if (phy_data->mdio_reset_gpio < 8)
3272 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3274 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3277 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3283 if (phy_data->mdio_reset_gpio < 8)
3284 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3286 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3289 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3298 struct xgbe_phy_data *phy_data = pdata->phy_data;
3301 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3308 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3310 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3319 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3321 if (!phy_data->redrv)
3324 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3327 switch (phy_data->redrv_model) {
3329 if (phy_data->redrv_lane > 3)
3333 if (phy_data->redrv_lane > 1)
3346 struct xgbe_phy_data *phy_data = pdata->phy_data;
3348 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3351 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3352 switch (phy_data->mdio_reset) {
3359 phy_data->mdio_reset);
3363 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3364 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3366 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3368 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3369 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3378 struct xgbe_phy_data *phy_data = pdata->phy_data;
3380 switch (phy_data->port_mode) {
3382 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3383 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3387 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3391 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3392 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3396 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3400 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3401 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3402 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3406 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3407 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3408 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3412 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3416 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3417 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3418 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3431 struct xgbe_phy_data *phy_data = pdata->phy_data;
3433 switch (phy_data->port_mode) {
3436 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3444 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3448 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3473 struct xgbe_phy_data *phy_data = pdata->phy_data;
3476 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3481 if (!phy_data->phy_cdr_notrack)
3484 DELAY(phy_data->phy_cdr_delay + 500);
3489 phy_data->phy_cdr_notrack = 0;
3497 struct xgbe_phy_data *phy_data = pdata->phy_data;
3500 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3505 if (phy_data->phy_cdr_notrack)
3513 phy_data->phy_cdr_notrack = 1;
3533 struct xgbe_phy_data *phy_data = pdata->phy_data;
3538 if (phy_data->cur_mode != XGBE_MODE_KR)
3548 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3549 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3551 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3563 struct xgbe_phy_data *phy_data = pdata->phy_data;
3568 if (phy_data->cur_mode != XGBE_MODE_KR)
3581 struct xgbe_phy_data *phy_data = pdata->phy_data;
3587 xgbe_phy_sfp_reset(phy_data);
3603 struct xgbe_phy_data *phy_data = pdata->phy_data;
3607 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
3617 if (phy_data->redrv && !phy_data->redrv_if) {
3618 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3622 phy_data->redrv_addr);
3628 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3634 switch (phy_data->port_mode) {
3645 phy_data->sfp_phy_retries = 0;
3671 struct xgbe_phy_data *phy_data = pdata->phy_data;
3676 cur_mode = phy_data->cur_mode;
3681 if (!phy_data->phydev) {
3748 /* free phy_data structure */
3749 free(pdata->phy_data, M_AXGBE);
3755 struct xgbe_phy_data *phy_data;
3773 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
3774 pdata->phy_data = phy_data;
3776 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3777 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3778 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3779 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3780 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3782 pdata->mdio_addr = phy_data->mdio_addr;
3783 DBGPR("port mode=%u\n", phy_data->port_mode);
3784 DBGPR("port id=%u\n", phy_data->port_id);
3785 DBGPR("port speeds=%#x\n", phy_data->port_speeds);
3786 DBGPR("conn type=%u\n", phy_data->conn_type);
3787 DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
3789 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3790 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3791 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3792 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3793 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3795 if (phy_data->redrv) {
3797 DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
3798 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
3799 DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
3800 DBGPR("redrv model=%u\n", phy_data->redrv_model);
3804 phy_data->redrv_addr, phy_data->redrv_if);
3808 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
3815 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
3827 if (xgbe_phy_redrv_error(phy_data)) {
3831 pdata->kr_redrv = phy_data->redrv;
3834 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3839 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
3840 switch (phy_data->port_mode) {
3847 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3849 phy_data->start_mode = XGBE_MODE_KX_1000;
3851 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3855 phy_data->start_mode = XGBE_MODE_KR;
3858 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3865 phy_data->start_mode = XGBE_MODE_KX_2500;
3867 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3876 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3878 phy_data->start_mode = XGBE_MODE_SGMII_100;
3880 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3882 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3885 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3895 phy_data->start_mode = XGBE_MODE_X;
3897 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3906 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3908 phy_data->start_mode = XGBE_MODE_SGMII_100;
3910 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3912 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3914 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3916 phy_data->start_mode = XGBE_MODE_KX_2500;
3919 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3928 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3930 phy_data->start_mode = XGBE_MODE_SGMII_100;
3932 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3934 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3936 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3938 phy_data->start_mode = XGBE_MODE_KR;
3941 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3956 phy_data->start_mode = XGBE_MODE_SFI;
3958 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3968 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3969 phy_data->start_mode = XGBE_MODE_SGMII_100;
3970 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3971 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3972 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3973 phy_data->start_mode = XGBE_MODE_SFI;
3975 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3979 phy_data->start_mode, phy_data->phydev_mode,
3987 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3990 phy_data->conn_type, phy_data->phydev_mode);
3991 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3992 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3993 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3994 phy_data->phydev_mode);
3997 phy_data->mdio_addr, phy_data->phydev_mode);
4002 if (phy_data->redrv && !phy_data->redrv_if) {
4003 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
4007 phy_data->redrv_addr);
4012 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
4014 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {