Lines Matching defs:pdata
421 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
422 static int xgbe_phy_reset(struct xgbe_prv_data *pdata);
427 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op)
429 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
433 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
436 struct xgbe_phy_data *phy_data = pdata->phy_data;
464 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
478 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
495 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val,
508 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
516 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,
531 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
547 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
556 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
558 struct xgbe_phy_data *phy_data = pdata->phy_data;
572 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
576 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
578 struct xgbe_phy_data *phy_data = pdata->phy_data;
592 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
596 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
602 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
615 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
616 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
626 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
627 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
633 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
634 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
647 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
650 struct xgbe_phy_data *phy_data = pdata->phy_data;
660 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
664 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)
670 ret = xgbe_phy_sfp_get_mux(pdata);
678 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
681 xgbe_phy_sfp_put_mux(pdata);
687 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)
689 struct xgbe_phy_data *phy_data = pdata->phy_data;
693 ret = xgbe_phy_get_comm_ownership(pdata);
698 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
700 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
704 xgbe_phy_put_comm_ownership(pdata);
710 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
712 struct xgbe_phy_data *phy_data = pdata->phy_data;
722 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
726 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
732 ret = xgbe_phy_sfp_get_mux(pdata);
737 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
743 xgbe_phy_sfp_put_mux(pdata);
749 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
751 struct xgbe_phy_data *phy_data = pdata->phy_data;
755 ret = xgbe_phy_get_comm_ownership(pdata);
760 ret = xgbe_phy_i2c_mii_read(pdata, reg);
762 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
766 xgbe_phy_put_comm_ownership(pdata);
772 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
774 struct xgbe_phy_data *phy_data = pdata->phy_data;
779 XGBE_ZERO_SUP(&pdata->phy);
782 pdata->phy.speed = SPEED_UNKNOWN;
783 pdata->phy.duplex = DUPLEX_UNKNOWN;
784 pdata->phy.autoneg = AUTONEG_ENABLE;
785 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
787 XGBE_SET_SUP(&pdata->phy, Autoneg);
788 XGBE_SET_SUP(&pdata->phy, Pause);
789 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
790 XGBE_SET_SUP(&pdata->phy, TP);
791 XGBE_SET_SUP(&pdata->phy, FIBRE);
793 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
802 pdata->phy.speed = SPEED_100;
803 pdata->phy.duplex = DUPLEX_FULL;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
811 pdata->phy.speed = SPEED_UNKNOWN;
812 pdata->phy.duplex = DUPLEX_UNKNOWN;
813 pdata->phy.autoneg = AUTONEG_ENABLE;
814 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
815 XGBE_SET_SUP(&pdata->phy, Autoneg);
816 XGBE_SET_SUP(&pdata->phy, Pause);
817 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
820 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
822 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
825 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
830 pdata->phy.speed = SPEED_1000;
831 pdata->phy.duplex = DUPLEX_FULL;
832 pdata->phy.autoneg = AUTONEG_DISABLE;
833 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
840 pdata->phy.speed = SPEED_10000;
841 pdata->phy.duplex = DUPLEX_FULL;
842 pdata->phy.autoneg = AUTONEG_DISABLE;
843 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
847 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
850 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
853 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
856 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
859 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
867 pdata->phy.speed = SPEED_UNKNOWN;
868 pdata->phy.duplex = DUPLEX_UNKNOWN;
869 pdata->phy.autoneg = AUTONEG_DISABLE;
870 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
878 XGBE_SET_SUP(&pdata->phy, TP);
881 XGBE_SET_SUP(&pdata->phy, FIBRE);
885 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
888 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
889 phy_data->sfp_base, pdata->phy.pause_autoneg,
890 pdata->phy.advertising, pdata->phy.supported);
927 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
929 struct xgbe_phy_data *phy_data = pdata->phy_data;
934 if (pdata->axgbe_miibus != NULL) {
935 device_delete_child(pdata->dev, pdata->axgbe_miibus);
936 pdata->axgbe_miibus = NULL;
941 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
943 struct xgbe_phy_data *phy_data = pdata->phy_data;
953 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
954 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
959 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
960 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
961 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
962 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
970 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
972 struct xgbe_phy_data *phy_data = pdata->phy_data;
985 pdata->an_again = 1;
995 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
996 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
997 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
1000 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1001 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1004 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1008 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1009 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
1012 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1013 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1016 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1020 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1021 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1024 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1025 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1028 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1032 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1033 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1041 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
1043 if (xgbe_phy_belfuse_phy_quirks(pdata))
1046 if (xgbe_phy_finisar_phy_quirks(pdata))
1051 xgbe_get_phy_id(struct xgbe_prv_data *pdata)
1053 struct xgbe_phy_data *phy_data = pdata->phy_data;
1057 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
1064 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
1081 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1083 struct xgbe_phy_data *phy_data = pdata->phy_data;
1097 pdata->an_again = 0;
1115 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1123 ret = xgbe_get_phy_id(pdata);
1129 xgbe_phy_external_phy_quirks(pdata);
1135 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1137 struct xgbe_phy_data *phy_data = pdata->phy_data;
1151 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1165 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
1168 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
1222 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1224 struct xgbe_phy_data *phy_data = pdata->phy_data;
1339 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1383 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base)
1394 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1396 struct xgbe_phy_data *phy_data = pdata->phy_data;
1401 ret = xgbe_phy_sfp_get_mux(pdata);
1409 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1420 dump_sfp_eeprom(pdata, base);
1441 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1445 xgbe_phy_free_phy_device(pdata);
1450 xgbe_phy_sfp_put_mux(pdata);
1456 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1458 struct xgbe_phy_data *phy_data = pdata->phy_data;
1467 ret = xgbe_phy_sfp_get_mux(pdata);
1474 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1495 xgbe_phy_sfp_put_mux(pdata);
1499 xgbe_read_gpio_expander(struct xgbe_prv_data *pdata)
1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
1505 ret = xgbe_phy_sfp_get_mux(pdata);
1513 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1534 xgbe_phy_sfp_put_mux(pdata);
1540 xgbe_log_gpio_expander(struct xgbe_prv_data *pdata)
1542 struct xgbe_phy_data *phy_data = pdata->phy_data;
1551 xgbe_phy_validate_gpio_expander(struct xgbe_prv_data *pdata)
1553 struct xgbe_phy_data *phy_data = pdata->phy_data;
1563 ret = xgbe_phy_get_comm_ownership(pdata);
1567 ret = xgbe_read_gpio_expander(pdata);
1571 ret = xgbe_phy_sfp_get_mux(pdata);
1580 xgbe_log_gpio_expander(pdata);
1583 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1595 xgbe_log_gpio_expander(pdata);
1605 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1617 xgbe_phy_sfp_put_mux(pdata);
1620 xgbe_phy_put_comm_ownership(pdata);
1626 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1628 struct xgbe_phy_data *phy_data = pdata->phy_data;
1630 xgbe_phy_free_phy_device(pdata);
1649 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1651 struct xgbe_phy_data *phy_data = pdata->phy_data;
1654 ret = xgbe_phy_get_comm_ownership(pdata);
1659 xgbe_phy_sfp_signals(pdata);
1663 xgbe_phy_sfp_mod_absent(pdata);
1667 ret = xgbe_phy_sfp_read_eeprom(pdata);
1671 ret = xgbe_read_gpio_expander(pdata);
1674 xgbe_log_gpio_expander(pdata);
1677 xgbe_phy_sfp_mod_absent(pdata);
1681 xgbe_phy_sfp_parse_eeprom(pdata);
1683 xgbe_phy_sfp_external_phy(pdata);
1686 xgbe_phy_sfp_phy_settings(pdata);
1689 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
1690 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
1692 xgbe_phy_put_comm_ownership(pdata);
1696 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata)
1698 struct xgbe_phy_data *phy_data = pdata->phy_data;
1713 ret = xgbe_phy_get_comm_ownership(pdata);
1719 ret = xgbe_phy_sfp_get_mux(pdata);
1728 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1742 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1754 xgbe_phy_sfp_put_mux(pdata);
1757 xgbe_phy_put_comm_ownership(pdata);
1764 xgbe_phy_module_info(struct xgbe_prv_data *pdata)
1766 struct xgbe_phy_data *phy_data = pdata->phy_data;
1778 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1780 struct xgbe_phy_data *phy_data = pdata->phy_data;
1782 pdata->phy.tx_pause = 0;
1783 pdata->phy.rx_pause = 0;
1788 if (pdata->phy.pause)
1789 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1791 if (pdata->phy.asym_pause)
1792 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1795 pdata->phy.tx_pause, pdata->phy.rx_pause);
1799 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1803 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1804 XGBE_SET_LP_ADV(&pdata->phy, TP);
1807 pdata->phy.pause_autoneg);
1810 if (pdata->phy.pause_autoneg)
1811 xgbe_phy_phydev_flowctrl(pdata);
1813 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1815 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1816 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
1820 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
1827 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1828 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
1832 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
1842 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1847 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1848 XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
1851 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1852 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1854 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1856 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1859 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1861 if (pdata->phy.pause_autoneg) {
1863 pdata->phy.tx_pause = 0;
1864 pdata->phy.rx_pause = 0;
1867 pdata->phy.tx_pause = 1;
1868 pdata->phy.rx_pause = 1;
1871 pdata->phy.rx_pause = 1;
1873 pdata->phy.tx_pause = 1;
1877 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1878 pdata->phy.rx_pause);
1881 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
1891 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1893 struct xgbe_phy_data *phy_data = pdata->phy_data;
1897 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1898 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1901 pdata->phy.pause_autoneg);
1904 if (pdata->phy.pause_autoneg)
1905 xgbe_phy_phydev_flowctrl(pdata);
1908 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1909 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1911 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1913 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1937 (pdata->phy.speed == SPEED_100))
1952 (pdata->phy.speed == SPEED_100))
1963 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1964 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1966 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1972 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1977 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1978 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1981 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1982 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1984 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1986 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1989 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1991 if (pdata->phy.pause_autoneg) {
1993 pdata->phy.tx_pause = 0;
1994 pdata->phy.rx_pause = 0;
1997 pdata->phy.tx_pause = 1;
1998 pdata->phy.rx_pause = 1;
2001 pdata->phy.rx_pause = 1;
2003 pdata->phy.tx_pause = 1;
2007 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
2008 pdata->phy.rx_pause);
2011 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
2012 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
2014 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
2016 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
2027 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
2028 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
2030 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
2036 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
2038 switch (pdata->an_mode) {
2040 return (xgbe_phy_an73_outcome(pdata));
2042 return (xgbe_phy_an73_redrv_outcome(pdata));
2044 return (xgbe_phy_an37_outcome(pdata));
2046 return (xgbe_phy_an37_sgmii_outcome(pdata));
2053 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
2055 struct xgbe_phy_data *phy_data = pdata->phy_data;
2057 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
2068 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2085 (pdata->phy.speed == SPEED_10000))
2113 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
2115 struct xgbe_phy_data *phy_data = pdata->phy_data;
2118 ret = xgbe_phy_find_phy_device(pdata);
2147 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
2149 struct xgbe_phy_data *phy_data = pdata->phy_data;
2178 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2187 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
2192 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
2195 struct xgbe_phy_data *phy_data = pdata->phy_data;
2202 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
2208 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
2210 struct xgbe_phy_data *phy_data = pdata->phy_data;
2223 ret = xgbe_phy_get_comm_ownership(pdata);
2229 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2231 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2233 xgbe_phy_put_comm_ownership(pdata);
2237 xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2239 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2247 xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2251 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2260 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2263 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2271 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd,
2277 xgbe_phy_pll_ctrl(pdata, false);
2280 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2282 xgbe_phy_rx_reset(pdata);
2290 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2291 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2292 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2297 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2308 xgbe_phy_pll_ctrl(pdata, true);
2312 xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2315 xgbe_phy_perform_ratechange(pdata, 5, 0);
2321 xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2323 struct xgbe_phy_data *phy_data = pdata->phy_data;
2326 xgbe_phy_perform_ratechange(pdata, 0, 0);
2334 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2336 struct xgbe_phy_data *phy_data = pdata->phy_data;
2338 xgbe_phy_set_redrv_mode(pdata);
2345 xgbe_phy_perform_ratechange(pdata, 3, 0);
2348 xgbe_phy_perform_ratechange(pdata, 3, 1);
2350 xgbe_phy_perform_ratechange(pdata, 3, 2);
2352 xgbe_phy_perform_ratechange(pdata, 3, 3);
2361 xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2363 struct xgbe_phy_data *phy_data = pdata->phy_data;
2365 xgbe_phy_set_redrv_mode(pdata);
2368 xgbe_phy_perform_ratechange(pdata, 1, 3);
2376 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2378 struct xgbe_phy_data *phy_data = pdata->phy_data;
2380 xgbe_phy_set_redrv_mode(pdata);
2383 xgbe_phy_perform_ratechange(pdata, 1, 2);
2391 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2393 struct xgbe_phy_data *phy_data = pdata->phy_data;
2395 xgbe_phy_set_redrv_mode(pdata);
2398 xgbe_phy_perform_ratechange(pdata, 1, 1);
2406 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2408 struct xgbe_phy_data *phy_data = pdata->phy_data;
2410 xgbe_phy_set_redrv_mode(pdata);
2413 xgbe_phy_perform_ratechange(pdata, 4, 0);
2421 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2423 struct xgbe_phy_data *phy_data = pdata->phy_data;
2425 xgbe_phy_set_redrv_mode(pdata);
2428 xgbe_phy_perform_ratechange(pdata, 2, 0);
2436 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2438 struct xgbe_phy_data *phy_data = pdata->phy_data;
2440 xgbe_phy_set_redrv_mode(pdata);
2443 xgbe_phy_perform_ratechange(pdata, 1, 3);
2451 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2453 struct xgbe_phy_data *phy_data = pdata->phy_data;
2459 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2461 struct xgbe_phy_data *phy_data = pdata->phy_data;
2465 return (xgbe_phy_cur_mode(pdata));
2467 switch (xgbe_phy_cur_mode(pdata)) {
2478 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2484 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2487 switch (xgbe_phy_cur_mode(pdata)) {
2497 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2499 struct xgbe_phy_data *phy_data = pdata->phy_data;
2503 return (xgbe_phy_switch_bp_mode(pdata));
2505 return (xgbe_phy_switch_bp_2500_mode(pdata));
2509 return (xgbe_phy_switch_baset_mode(pdata));
2514 return (xgbe_phy_cur_mode(pdata));
2594 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
2596 struct xgbe_phy_data *phy_data = pdata->phy_data;
2618 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2622 xgbe_phy_kx_1000_mode(pdata);
2625 xgbe_phy_kx_2500_mode(pdata);
2628 xgbe_phy_kr_mode(pdata);
2631 xgbe_phy_sgmii_100_mode(pdata);
2634 xgbe_phy_sgmii_1000_mode(pdata);
2637 xgbe_phy_x_mode(pdata);
2640 xgbe_phy_sfi_mode(pdata);
2648 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
2650 struct xgbe_phy_data *phy_data = pdata->phy_data;
2652 switch (pdata->phy.speed) {
2703 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
2707 if (pdata->phy.autoneg == AUTONEG_ENABLE)
2712 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2721 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2726 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2729 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2737 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2743 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2746 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2749 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2752 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2760 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2762 struct xgbe_phy_data *phy_data = pdata->phy_data;
2768 return (xgbe_phy_check_mode(pdata, mode,
2769 XGBE_ADV(&pdata->phy, 1000baseX_Full)));
2773 return (xgbe_phy_check_mode(pdata, mode,
2774 XGBE_ADV(&pdata->phy, 100baseT_Full)));
2778 return (xgbe_phy_check_mode(pdata, mode,
2779 XGBE_ADV(&pdata->phy, 1000baseT_Full)));
2783 return (xgbe_phy_check_mode(pdata, mode,
2784 XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
2785 XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
2786 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
2787 XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
2788 XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
2795 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2800 return (xgbe_phy_check_mode(pdata, mode,
2801 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
2808 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2813 return (xgbe_phy_check_mode(pdata, mode,
2814 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
2816 return (xgbe_phy_check_mode(pdata, mode,
2817 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
2824 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2830 return (xgbe_phy_use_bp_mode(pdata, mode));
2832 return (xgbe_phy_use_bp_2500_mode(pdata, mode));
2835 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
2838 return (xgbe_phy_use_baset_mode(pdata, mode));
2841 return (xgbe_phy_use_basex_mode(pdata, mode));
2843 return (xgbe_phy_use_sfp_mode(pdata, mode));
2924 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2926 struct xgbe_phy_data *phy_data = pdata->phy_data;
2948 xgbe_upd_link(struct xgbe_prv_data *pdata)
2952 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
2953 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2954 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2959 pdata->phy.link = 0;
2961 pdata->phy.link = 1;
2963 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
2968 xgbe_phy_read_status(struct xgbe_prv_data *pdata)
2976 ret = xgbe_upd_link(pdata);
2982 if (AUTONEG_ENABLE == pdata->phy.autoneg) {
2983 if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
2984 pdata->phy.supported == SUPPORTED_1000baseT_Full) {
2985 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2990 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
3004 if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
3005 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);
3006 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
3007 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);
3012 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
3016 if (pdata->phy.supported == SUPPORTED_Autoneg)
3017 XGBE_SET_ADV(&pdata->phy, Autoneg);
3019 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
3025 pdata->phy.speed = SPEED_10;
3026 pdata->phy.duplex = DUPLEX_HALF;
3027 pdata->phy.pause = 0;
3028 pdata->phy.asym_pause = 0;
3035 pdata->phy.speed = SPEED_1000;
3038 pdata->phy.duplex = DUPLEX_FULL;
3041 pdata->phy.speed = SPEED_100;
3044 pdata->phy.duplex = DUPLEX_FULL;
3047 pdata->phy.duplex = DUPLEX_FULL;
3049 if (pdata->phy.duplex == DUPLEX_FULL) {
3050 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
3051 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
3054 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
3059 pdata->phy.duplex = DUPLEX_FULL;
3061 pdata->phy.duplex = DUPLEX_HALF;
3064 pdata->phy.speed = SPEED_1000;
3066 pdata->phy.speed = SPEED_100;
3068 pdata->phy.speed = SPEED_10;
3070 pdata->phy.pause = 0;
3071 pdata->phy.asym_pause = 0;
3073 "autoneg %#x\n", __func__, pdata->phy.speed,
3074 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3081 xgbe_rrc(struct xgbe_prv_data *pdata)
3083 struct xgbe_phy_data *phy_data = pdata->phy_data;
3090 if (pdata->link_workaround) {
3091 ret = xgbe_phy_reset(pdata);
3095 xgbe_phy_rrc(pdata);
3100 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
3102 struct xgbe_phy_data *phy_data = pdata->phy_data;
3112 xgbe_phy_sfp_detect(pdata);
3126 xgbe_rrc(pdata);
3134 if (pdata->axgbe_miibus == NULL) {
3139 mii = device_get_softc(pdata->axgbe_miibus);
3142 ret = xgbe_phy_read_status(pdata);
3149 "autoneg %#x\n", __func__, pdata->phy.speed,
3150 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3151 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
3154 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
3157 if (pdata->phy.link)
3160 xgbe_rrc(pdata);
3168 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
3169 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
3175 xgbe_rrc(pdata);
3181 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
3183 struct xgbe_phy_data *phy_data = pdata->phy_data;
3186 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
3187 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3189 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3191 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3193 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3195 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3209 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
3211 struct xgbe_phy_data *phy_data = pdata->phy_data;
3214 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
3215 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
3221 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
3229 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
3231 xgbe_phy_sfp_comm_setup(pdata);
3232 xgbe_phy_sfp_gpio_setup(pdata);
3236 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
3238 struct xgbe_phy_data *phy_data = pdata->phy_data;
3241 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3245 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3251 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
3253 struct xgbe_phy_data *phy_data = pdata->phy_data;
3259 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3277 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3289 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3296 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3298 struct xgbe_phy_data *phy_data = pdata->phy_data;
3304 ret = xgbe_phy_get_comm_ownership(pdata);
3309 ret = xgbe_phy_i2c_mdio_reset(pdata);
3311 ret = xgbe_phy_int_mdio_reset(pdata);
3313 xgbe_phy_put_comm_ownership(pdata);
3344 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3346 struct xgbe_phy_data *phy_data = pdata->phy_data;
3351 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3365 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
3366 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3369 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3376 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3378 struct xgbe_phy_data *phy_data = pdata->phy_data;
3429 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3431 struct xgbe_phy_data *phy_data = pdata->phy_data;
3459 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3462 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3464 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3471 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3473 struct xgbe_phy_data *phy_data = pdata->phy_data;
3476 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3478 if (!pdata->sysctl_an_cdr_workaround)
3486 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3495 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3497 struct xgbe_phy_data *phy_data = pdata->phy_data;
3500 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3502 if (!pdata->sysctl_an_cdr_workaround)
3508 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3511 xgbe_phy_rrc(pdata);
3517 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3519 if (!pdata->sysctl_an_cdr_track_early)
3520 xgbe_phy_cdr_track(pdata);
3524 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3526 if (pdata->sysctl_an_cdr_track_early)
3527 xgbe_phy_cdr_track(pdata);
3531 xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3533 struct xgbe_phy_data *phy_data = pdata->phy_data;
3535 switch (pdata->an_mode) {
3541 xgbe_phy_cdr_track(pdata);
3543 switch (pdata->an_result) {
3561 xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3563 struct xgbe_phy_data *phy_data = pdata->phy_data;
3565 switch (pdata->an_mode) {
3571 xgbe_phy_cdr_notrack(pdata);
3579 xgbe_phy_stop(struct xgbe_prv_data *pdata)
3581 struct xgbe_phy_data *phy_data = pdata->phy_data;
3584 xgbe_phy_free_phy_device(pdata);
3588 xgbe_phy_sfp_mod_absent(pdata);
3591 xgbe_phy_cdr_track(pdata);
3594 xgbe_phy_power_off(pdata);
3597 pdata->i2c_if.i2c_stop(pdata);
3601 xgbe_phy_start(struct xgbe_prv_data *pdata)
3603 struct xgbe_phy_data *phy_data = pdata->phy_data;
3610 ret = pdata->i2c_if.i2c_start(pdata);
3618 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3628 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3631 xgbe_phy_cdr_track(pdata);
3643 xgbe_phy_validate_gpio_expander(pdata);
3646 xgbe_phy_sfp_detect(pdata);
3653 ret = xgbe_phy_find_phy_device(pdata);
3663 pdata->i2c_if.i2c_stop(pdata);
3669 xgbe_phy_reset(struct xgbe_prv_data *pdata)
3671 struct xgbe_phy_data *phy_data = pdata->phy_data;
3677 xgbe_phy_power_off(pdata);
3678 xgbe_phy_set_mode(pdata, cur_mode);
3687 ret = xgbe_phy_mdio_reset(pdata);
3702 struct xgbe_prv_data *pdata;
3706 pdata = &sc->pdata;
3709 mtx_lock_spin(&pdata->mdio_mutex);
3710 mii = device_get_softc(pdata->axgbe_miibus);
3716 mtx_unlock_spin(&pdata->mdio_mutex);
3722 struct xgbe_prv_data *pdata;
3729 pdata = &sc->pdata;
3732 mtx_lock_spin(&pdata->mdio_mutex);
3733 mii = device_get_softc(pdata->axgbe_miibus);
3737 mtx_unlock_spin(&pdata->mdio_mutex);
3743 xgbe_phy_exit(struct xgbe_prv_data *pdata)
3745 if (pdata->axgbe_miibus != NULL)
3746 device_delete_child(pdata->dev, pdata->axgbe_miibus);
3749 free(pdata->phy_data, M_AXGBE);
3753 xgbe_phy_init(struct xgbe_prv_data *pdata)
3763 if (!xgbe_phy_port_enabled(pdata)) {
3769 ret = pdata->i2c_if.i2c_init(pdata);
3774 pdata->phy_data = phy_data;
3776 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3777 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3778 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3779 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3780 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3782 pdata->mdio_addr = phy_data->mdio_addr;
3789 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3790 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3791 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3792 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3793 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3806 if (xgbe_phy_conn_type_mismatch(pdata)) {
3813 if (xgbe_phy_port_mode_mismatch(pdata)) {
3820 ret = xgbe_phy_mdio_reset_setup(pdata);
3831 pdata->kr_redrv = phy_data->redrv;
3837 XGBE_ZERO_SUP(&pdata->phy);
3843 XGBE_SET_SUP(&pdata->phy, Autoneg);
3844 XGBE_SET_SUP(&pdata->phy, Pause);
3845 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3846 XGBE_SET_SUP(&pdata->phy, Backplane);
3848 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
3852 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
3853 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3854 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3861 XGBE_SET_SUP(&pdata->phy, Pause);
3862 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3863 XGBE_SET_SUP(&pdata->phy, Backplane);
3864 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
3872 XGBE_SET_SUP(&pdata->phy, Autoneg);
3873 XGBE_SET_SUP(&pdata->phy, Pause);
3874 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3875 XGBE_SET_SUP(&pdata->phy, TP);
3877 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3881 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3890 XGBE_SET_SUP(&pdata->phy, Autoneg);
3891 XGBE_SET_SUP(&pdata->phy, Pause);
3892 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3893 XGBE_SET_SUP(&pdata->phy, FIBRE);
3894 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
3902 XGBE_SET_SUP(&pdata->phy, Autoneg);
3903 XGBE_SET_SUP(&pdata->phy, Pause);
3904 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3905 XGBE_SET_SUP(&pdata->phy, TP);
3907 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3911 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3915 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
3924 XGBE_SET_SUP(&pdata->phy, Autoneg);
3925 XGBE_SET_SUP(&pdata->phy, Pause);
3926 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3927 XGBE_SET_SUP(&pdata->phy, TP);
3929 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3933 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3937 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
3946 XGBE_SET_SUP(&pdata->phy, Autoneg);
3947 XGBE_SET_SUP(&pdata->phy, Pause);
3948 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3949 XGBE_SET_SUP(&pdata->phy, FIBRE);
3950 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
3951 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
3952 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
3953 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
3954 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3955 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3963 XGBE_SET_SUP(&pdata->phy, Autoneg);
3964 XGBE_SET_SUP(&pdata->phy, Pause);
3965 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3966 XGBE_SET_SUP(&pdata->phy, TP);
3967 XGBE_SET_SUP(&pdata->phy, FIBRE);
3977 xgbe_phy_sfp_setup(pdata);
3980 pdata->phy.advertising);
3987 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3993 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
4003 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
4015 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
4018 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);