Lines Matching +full:charge +full:- +full:ctrl +full:- +full:value
4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
34 * granted, free of charge, to any person obtaining a copy of this software
91 * granted, free of charge, to any person obtaining a copy of this software
116 #include "xgbe-common.h"
122 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
131 rate = pdata->sysclk_rate;
134 * Convert the input usec value to the watchdog timer value. Each
135 * watchdog timer value is equivalent to 256 clock cycles.
136 * Calculate the required value as:
150 rate = pdata->sysclk_rate;
153 * Convert the input watchdog timer value to the usec value. Each
154 * watchdog timer value is equivalent to 256 clock cycles.
155 * Calculate the required value as:
170 pbl = pdata->pbl;
172 if (pdata->pbl > 32) {
177 for (i = 0; i < pdata->channel_count; i++) {
178 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
181 if (pdata->channel[i]->tx_ring)
182 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
185 if (pdata->channel[i]->rx_ring)
186 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
198 for (i = 0; i < pdata->channel_count; i++) {
199 if (!pdata->channel[i]->tx_ring)
202 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
203 pdata->tx_osp_mode);
214 for (i = 0; i < pdata->rx_q_count; i++)
225 for (i = 0; i < pdata->tx_q_count; i++)
236 for (i = 0; i < pdata->rx_q_count; i++)
247 for (i = 0; i < pdata->tx_q_count; i++)
258 for (i = 0; i < pdata->channel_count; i++) {
259 if (!pdata->channel[i]->rx_ring)
262 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
263 pdata->rx_riwt);
280 for (i = 0; i < pdata->channel_count; i++) {
281 if (!pdata->channel[i]->rx_ring)
284 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
285 pdata->rx_buf_size);
294 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO);
296 for (i = 0; i < pdata->channel_count; i++) {
297 if (!pdata->channel[i]->tx_ring)
301 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0);
312 pdata->sph_enable, sph_enable_flag);
314 if (pdata->sph_enable && sph_enable_flag)
317 for (i = 0; i < pdata->channel_count; i++) {
318 if (!pdata->channel[i]->rx_ring)
320 if (pdata->sph_enable && sph_enable_flag) {
322 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
325 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0);
328 /* per-channel confirmation of SPH being disabled/enabled */
329 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH);
334 if (pdata->sph_enable && sph_enable_flag)
345 mtx_lock(&pdata->rss_mutex);
348 ret = -EBUSY;
360 while (wait--) {
367 ret = -EBUSY;
370 mtx_unlock(&pdata->rss_mutex);
378 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t);
379 unsigned int *key = (unsigned int *)&pdata->rss_key;
382 while (key_regs--) {
398 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
400 pdata->rss_table[i]);
411 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
421 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
422 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
432 if (!pdata->hw_feat.rss)
433 return (-EOPNOTSUPP);
446 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
459 if (!pdata->hw_feat.rss)
460 return (-EOPNOTSUPP);
474 if (!pdata->hw_feat.rss)
478 if (pdata->enable_rss)
495 for (i = 0; i < pdata->rx_q_count; i++)
500 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
521 for (i = 0; i < pdata->rx_q_count; i++) {
524 if (pdata->rx_rfd[i]) {
526 /* TODO - enable pfc/ets support */
538 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
576 if (pdata->tx_pause)
587 if (pdata->rx_pause)
611 if (pdata->channel_irq_mode)
613 pdata->channel_irq_mode);
615 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
617 for (i = 0; i < pdata->channel_count; i++) {
618 channel = pdata->channel[i];
625 channel->curr_ier = 0;
628 * NIE - Normal Interrupt Summary Enable
629 * AIE - Abnormal Interrupt Summary Enable
630 * FBEE - Fatal Bus Error Enable
633 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
634 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
636 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
637 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
639 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
641 if (channel->tx_ring) {
643 * TIE - Transmit Interrupt Enable (unless using
647 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
648 XGMAC_SET_BITS(channel->curr_ier,
651 if (channel->rx_ring) {
653 * RBUE - Receive Buffer Unavailable Enable
654 * RIE - Receive Interrupt Enable (unless using
658 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
659 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
660 XGMAC_SET_BITS(channel->curr_ier,
664 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
674 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
719 return (-EINVAL);
737 /* Check only C-TAG (0x8100) packets */
740 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
773 /* Only filter on the lower 12-bits of the VLAN tag */
836 /* Generate the VLAN Hash Table value */
837 bit_foreach(pdata->active_vlans, VLAN_NVID, vid) {
838 /* Get the CRC32 value of the VLAN ID */
874 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
934 addn_macs = pdata->hw_feat.addn_mac;
936 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg);
937 addn_macs--;
940 while (addn_macs--)
947 /* TODO - add support to set mac hash table */
973 pr_mode = ((if_getflags(pdata->netdev) & IFF_PROMISC) != 0);
974 am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0);
990 return (-EINVAL);
1006 return (-EINVAL);
1026 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1033 * The mmio interface is based on 16-bit offsets and values. All
1038 index = mmd_address & ~pdata->xpcs_window_mask;
1039 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1041 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1042 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1044 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1059 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1066 * The mmio interface is based on 16-bit offsets and values. All
1071 index = mmd_address & ~pdata->xpcs_window_mask;
1072 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1074 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1075 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1077 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1090 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1097 * The mmio interface is based on 32-bit offsets and values. All
1101 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1104 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1119 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1126 * The mmio interface is based on 32-bit offsets and values. All
1130 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1133 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1139 switch (pdata->vdata->xpcs_access) {
1153 switch (pdata->vdata->xpcs_access) {
1184 mtx_lock_spin(&pdata->mdio_mutex);
1195 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
1198 mtx_unlock_spin(&pdata->mdio_mutex);
1199 return (-ETIMEDOUT);
1202 mtx_unlock_spin(&pdata->mdio_mutex);
1211 mtx_lock_spin(&pdata->mdio_mutex);
1221 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
1224 mtx_unlock_spin(&pdata->mdio_mutex);
1225 return (-ETIMEDOUT);
1228 mtx_unlock_spin(&pdata->mdio_mutex);
1242 return (-EINVAL);
1248 return (-EINVAL);
1259 return (!XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN));
1283 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1291 rdesc->desc0 = 0;
1292 rdesc->desc1 = 0;
1293 rdesc->desc2 = 0;
1294 rdesc->desc3 = 0;
1302 struct xgbe_ring *ring = channel->tx_ring;
1305 int start_index = ring->cur;
1308 for (i = 0; i < ring->rdesc_count; i++) {
1316 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1321 upper_32_bits(rdata->rdata_paddr));
1323 lower_32_bits(rdata->rdata_paddr));
1329 struct xgbe_ring *ring = channel->rx_ring;
1331 unsigned int start_index = ring->cur;
1339 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1344 upper_32_bits(rdata->rdata_paddr));
1346 lower_32_bits(rdata->rdata_paddr));
1352 struct xgbe_prv_data *pdata = channel->pdata;
1353 struct xgbe_ring *ring = channel->rx_ring;
1356 struct xgbe_packet_data *packet = &ring->packet_data;
1359 axgbe_printf(1, "-->xgbe_dev_read: cur = %d\n", ring->cur);
1361 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1362 rdesc = rdata->rdesc;
1365 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1370 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1371 /* TODO - Timestamp Context Descriptor */
1372 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1374 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1380 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1383 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1384 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1388 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
1389 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1391 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1393 if (rdata->rx.hdr_len)
1394 pdata->ext_stats.rx_split_header_packets++;
1396 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1400 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1401 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1404 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1406 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1409 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV4;
1412 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV4;
1415 packet->rss_hash_type = M_HASHTYPE_RSS_TCP_IPV6;
1418 packet->rss_hash_type = M_HASHTYPE_RSS_UDP_IPV6;
1421 packet->rss_hash_type = M_HASHTYPE_OPAQUE;
1427 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1429 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1435 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1439 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1442 /* TODO - add tunneling support */
1443 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1447 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1448 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1454 (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
1455 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1457 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1459 axgbe_printf(1, "vlan-ctag=%#06x\n", packet->vlan_ctag);
1462 unsigned int tnp = XGMAC_GET_BITS(packet->attributes,
1468 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1470 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1472 pdata->ext_stats.rx_csum_errors++;
1476 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1478 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1480 pdata->ext_stats.rx_vxlan_csum_errors++;
1485 __func__, channel->queue_index,
1489 __func__, ring->cur, ring->dirty);
1490 axgbe_printf(1, "%s: Desc 0x%08x-0x%08x-0x%08x-0x%08x\n",
1491 __func__, rdesc->desc0, rdesc->desc1, rdesc->desc2,
1492 rdesc->desc3);
1493 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1498 axgbe_printf(1, "<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n",
1499 channel->name, ring->cur & (ring->rdesc_count - 1), ring->cur);
1508 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT));
1515 return (XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD));
1521 struct xgbe_prv_data *pdata = channel->pdata;
1523 axgbe_printf(1, "enable_int: DMA_CH_IER read - 0x%x\n",
1524 channel->curr_ier);
1528 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
1531 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
1534 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
1537 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
1540 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
1543 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
1546 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
1547 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
1550 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
1553 channel->curr_ier |= channel->saved_ier;
1556 return (-1);
1559 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
1561 axgbe_printf(1, "enable_int: DMA_CH_IER write - 0x%x\n",
1562 channel->curr_ier);
1570 struct xgbe_prv_data *pdata = channel->pdata;
1572 axgbe_printf(1, "disable_int: DMA_CH_IER read - 0x%x\n",
1573 channel->curr_ier);
1577 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
1580 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
1583 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
1586 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
1589 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
1592 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
1595 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
1596 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
1599 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
1602 channel->saved_ier = channel->curr_ier;
1603 channel->curr_ier = 0;
1606 return (-1);
1609 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
1611 axgbe_printf(1, "disable_int: DMA_CH_IER write - 0x%x\n",
1612 channel->curr_ier);
1627 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1631 return (-EBUSY);
1658 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1661 for (i = 0; i < pdata->tx_q_count; i++)
1665 for (i = 0; i < pdata->tx_q_count; i++) {
1667 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
1672 return (-EBUSY);
1690 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
1691 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
1698 if (pdata->vdata->tx_desc_prefetch)
1700 pdata->vdata->tx_desc_prefetch);
1702 if (pdata->vdata->rx_desc_prefetch)
1704 pdata->vdata->rx_desc_prefetch);
1710 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
1711 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
1712 if (pdata->awarcr)
1713 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
1725 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1746 /* TODO - add pfc/ets related support */
1755 pdata->rx_rfa[queue] = 0;
1756 pdata->rx_rfd[queue] = 0;
1762 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
1763 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
1768 /* Between 4096 and max-frame */
1769 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
1770 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
1775 /* Between max-frame and 3 max-frames,
1779 rfa = q_fifo_size - frame_fifo_size;
1782 /* Above 3 max-frames - trigger when just over
1790 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
1791 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
1793 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]);
1803 for (i = 0; i < pdata->rx_q_count; i++) {
1806 axgbe_printf(1, "%s: fifo[%d] - 0x%x q_fifo_size 0x%x\n",
1817 for (i = 0; i < pdata->rx_q_count; i++) {
1819 pdata->rx_rfa[i], pdata->rx_rfd[i]);
1822 pdata->rx_rfa[i]);
1824 pdata->rx_rfd[i]);
1834 /* The configured value may not be the actual amount of fifo RAM */
1835 return (min_t(unsigned int, pdata->tx_max_fifo_size,
1836 pdata->hw_feat.tx_fifo_size));
1842 /* The configured value may not be the actual amount of fifo RAM */
1843 return (min_t(unsigned int, pdata->rx_max_fifo_size,
1844 pdata->hw_feat.rx_fifo_size));
1863 p_fifo--;
1886 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
1887 fifo_size -= XGMAC_FIFO_MIN_ALLOC;
1903 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
1905 for (i = 0; i < pdata->tx_q_count; i++) {
1912 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
1923 /* TODO - add pfc/ets related support */
1927 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
1929 fifo_size, pdata->rx_q_count, prio_queues);
1931 /* Assign a minimum fifo to the non-VLAN priority queues */
1932 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
1936 for (i = 0; i < pdata->rx_q_count; i++) {
1946 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
1961 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1962 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1964 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1969 pdata->q2tc_map[queue++] = i;
1976 pdata->q2tc_map[queue++] = i;
1981 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
1992 pdata->prio2q_map[prio++] = i;
1998 pdata->prio2q_map[prio++] = i;
2014 for (i = 0; i < pdata->rx_q_count;) {
2017 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2030 xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev));
2039 if (pdata->hw_feat.hash_table_size) {
2051 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2059 xgbe_set_speed(pdata, pdata->phy_speed);
2065 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM))
2078 /* Set the current VLAN Hash Table register value */
2081 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
2089 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
2104 if (pdata->vdata->mmc_64bit) {
2144 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2148 stats->txoctetcount_gb +=
2152 stats->txframecount_gb +=
2156 stats->txbroadcastframes_g +=
2160 stats->txmulticastframes_g +=
2164 stats->tx64octets_gb +=
2168 stats->tx65to127octets_gb +=
2172 stats->tx128to255octets_gb +=
2176 stats->tx256to511octets_gb +=
2180 stats->tx512to1023octets_gb +=
2184 stats->tx1024tomaxoctets_gb +=
2188 stats->txunicastframes_gb +=
2192 stats->txmulticastframes_gb +=
2196 stats->txbroadcastframes_g +=
2200 stats->txunderflowerror +=
2204 stats->txoctetcount_g +=
2208 stats->txframecount_g +=
2212 stats->txpauseframes +=
2216 stats->txvlanframes_g +=
2223 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2227 stats->rxframecount_gb +=
2231 stats->rxoctetcount_gb +=
2235 stats->rxoctetcount_g +=
2239 stats->rxbroadcastframes_g +=
2243 stats->rxmulticastframes_g +=
2247 stats->rxcrcerror +=
2251 stats->rxrunterror +=
2255 stats->rxjabbererror +=
2259 stats->rxundersize_g +=
2263 stats->rxoversize_g +=
2267 stats->rx64octets_gb +=
2271 stats->rx65to127octets_gb +=
2275 stats->rx128to255octets_gb +=
2279 stats->rx256to511octets_gb +=
2283 stats->rx512to1023octets_gb +=
2287 stats->rx1024tomaxoctets_gb +=
2291 stats->rxunicastframes_g +=
2295 stats->rxlengtherror +=
2299 stats->rxoutofrangetype +=
2303 stats->rxpauseframes +=
2307 stats->rxfifooverflow +=
2311 stats->rxvlanframes_gb +=
2315 stats->rxwatchdogerror +=
2322 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2327 stats->txoctetcount_gb +=
2330 stats->txframecount_gb +=
2333 stats->txbroadcastframes_g +=
2336 stats->txmulticastframes_g +=
2339 stats->tx64octets_gb +=
2342 stats->tx65to127octets_gb +=
2345 stats->tx128to255octets_gb +=
2348 stats->tx256to511octets_gb +=
2351 stats->tx512to1023octets_gb +=
2354 stats->tx1024tomaxoctets_gb +=
2357 stats->txunicastframes_gb +=
2360 stats->txmulticastframes_gb +=
2363 stats->txbroadcastframes_gb +=
2366 stats->txunderflowerror +=
2369 stats->txoctetcount_g +=
2372 stats->txframecount_g +=
2375 stats->txpauseframes +=
2378 stats->txvlanframes_g +=
2381 stats->rxframecount_gb +=
2384 stats->rxoctetcount_gb +=
2387 stats->rxoctetcount_g +=
2390 stats->rxbroadcastframes_g +=
2393 stats->rxmulticastframes_g +=
2396 stats->rxcrcerror +=
2399 stats->rxrunterror +=
2402 stats->rxjabbererror +=
2405 stats->rxundersize_g +=
2408 stats->rxoversize_g +=
2411 stats->rx64octets_gb +=
2414 stats->rx65to127octets_gb +=
2417 stats->rx128to255octets_gb +=
2420 stats->rx256to511octets_gb +=
2423 stats->rx512to1023octets_gb +=
2426 stats->rx1024tomaxoctets_gb +=
2429 stats->rxunicastframes_g +=
2432 stats->rxlengtherror +=
2435 stats->rxoutofrangetype +=
2438 stats->rxpauseframes +=
2441 stats->rxfifooverflow +=
2444 stats->rxvlanframes_gb +=
2447 stats->rxwatchdogerror +=
2450 /* Un-freeze counters */
2496 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
2504 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
2537 for (i = 0; i < pdata->channel_count; i++) {
2538 if (!pdata->channel[i]->tx_ring)
2541 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
2545 for (i = 0; i < pdata->tx_q_count; i++)
2559 for (i = 0; i < pdata->tx_q_count; i++)
2566 for (i = 0; i < pdata->tx_q_count; i++)
2570 for (i = 0; i < pdata->channel_count; i++) {
2571 if (!pdata->channel[i]->tx_ring)
2574 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
2609 for (i = 0; i < pdata->channel_count; i++) {
2610 if (!pdata->channel[i]->rx_ring)
2613 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
2618 for (i = 0; i < pdata->rx_q_count; i++)
2641 for (i = 0; i < pdata->rx_q_count; i++)
2648 for (i = 0; i < pdata->channel_count; i++) {
2649 if (!pdata->channel[i]->rx_ring)
2652 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
2662 for (i = 0; i < pdata->channel_count; i++) {
2663 if (!pdata->channel[i]->tx_ring)
2666 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
2679 for (i = 0; i < pdata->tx_q_count; i++)
2686 for (i = 0; i < pdata->channel_count; i++) {
2687 if (!pdata->channel[i]->tx_ring)
2690 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
2700 for (i = 0; i < pdata->channel_count; i++) {
2701 if (!pdata->channel[i]->rx_ring)
2704 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
2714 for (i = 0; i < pdata->channel_count; i++) {
2715 if (!pdata->channel[i]->rx_ring)
2718 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
2725 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2748 desc_if->wrapper_tx_desc_init(pdata);
2749 desc_if->wrapper_rx_desc_init(pdata);
2757 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2758 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2759 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2760 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2788 hw_if->tx_complete = xgbe_tx_complete;
2790 hw_if->set_mac_address = xgbe_set_mac_address;
2791 hw_if->config_rx_mode = xgbe_config_rx_mode;
2793 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2794 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2796 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2797 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2798 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2799 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2800 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2802 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2803 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2805 hw_if->set_speed = xgbe_set_speed;
2807 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
2808 hw_if->read_ext_mii_regs = xgbe_read_ext_mii_regs;
2809 hw_if->write_ext_mii_regs = xgbe_write_ext_mii_regs;
2811 hw_if->set_gpio = xgbe_set_gpio;
2812 hw_if->clr_gpio = xgbe_clr_gpio;
2814 hw_if->enable_tx = xgbe_enable_tx;
2815 hw_if->disable_tx = xgbe_disable_tx;
2816 hw_if->enable_rx = xgbe_enable_rx;
2817 hw_if->disable_rx = xgbe_disable_rx;
2819 hw_if->powerup_tx = xgbe_powerup_tx;
2820 hw_if->powerdown_tx = xgbe_powerdown_tx;
2821 hw_if->powerup_rx = xgbe_powerup_rx;
2822 hw_if->powerdown_rx = xgbe_powerdown_rx;
2824 hw_if->dev_read = xgbe_dev_read;
2825 hw_if->enable_int = xgbe_enable_int;
2826 hw_if->disable_int = xgbe_disable_int;
2827 hw_if->init = xgbe_init;
2828 hw_if->exit = xgbe_exit;
2831 hw_if->tx_desc_init = xgbe_tx_desc_init;
2832 hw_if->rx_desc_init = xgbe_rx_desc_init;
2833 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2834 hw_if->is_last_desc = xgbe_is_last_desc;
2835 hw_if->is_context_desc = xgbe_is_context_desc;
2837 /* For FLOW ctrl */
2838 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2839 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2842 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2843 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2844 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2845 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2848 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2849 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2852 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2853 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2856 hw_if->config_osp_mode = xgbe_config_osp_mode;
2859 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2860 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2861 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2864 hw_if->enable_rss = xgbe_enable_rss;
2865 hw_if->disable_rss = xgbe_disable_rss;
2866 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2867 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;