Lines Matching defs:pdata
120 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
122 return (if_getmtu(pdata->netdev) + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
126 xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, unsigned int usec)
131 rate = pdata->sysclk_rate;
145 xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, unsigned int riwt)
150 rate = pdata->sysclk_rate;
164 xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
170 pbl = pdata->pbl;
172 if (pdata->pbl > 32) {
177 for (i = 0; i < pdata->channel_count; i++) {
178 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
181 if (pdata->channel[i]->tx_ring)
182 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
185 if (pdata->channel[i]->rx_ring)
186 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
194 xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
198 for (i = 0; i < pdata->channel_count; i++) {
199 if (!pdata->channel[i]->tx_ring)
202 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
203 pdata->tx_osp_mode);
210 xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
214 for (i = 0; i < pdata->rx_q_count; i++)
215 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
221 xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
225 for (i = 0; i < pdata->tx_q_count; i++)
226 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
232 xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, unsigned int val)
236 for (i = 0; i < pdata->rx_q_count; i++)
237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
243 xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, unsigned int val)
247 for (i = 0; i < pdata->tx_q_count; i++)
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
254 xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
258 for (i = 0; i < pdata->channel_count; i++) {
259 if (!pdata->channel[i]->rx_ring)
262 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
263 pdata->rx_riwt);
270 xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
276 xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
280 for (i = 0; i < pdata->channel_count; i++) {
281 if (!pdata->channel[i]->rx_ring)
284 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
285 pdata->rx_buf_size);
290 xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
294 int tso_enabled = (if_getcapenable(pdata->netdev) & IFCAP_TSO);
296 for (i = 0; i < pdata->channel_count; i++) {
297 if (!pdata->channel[i]->tx_ring)
301 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, tso_enabled ? 1 : 0);
306 xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
309 int sph_enable_flag = XGMAC_IOREAD_BITS(pdata, MAC_HWF1R, SPHEN);
312 pdata->sph_enable, sph_enable_flag);
314 if (pdata->sph_enable && sph_enable_flag)
317 for (i = 0; i < pdata->channel_count; i++) {
318 if (!pdata->channel[i]->rx_ring)
320 if (pdata->sph_enable && sph_enable_flag) {
322 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
325 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0);
329 int val = XGMAC_DMA_IOREAD_BITS(pdata->channel[i], DMA_CH_CR, SPH);
334 if (pdata->sph_enable && sph_enable_flag)
335 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
339 xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
345 mtx_lock(&pdata->rss_mutex);
347 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
352 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
354 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
355 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
356 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
357 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
361 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
370 mtx_unlock(&pdata->rss_mutex);
376 xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
378 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(uint32_t);
379 unsigned int *key = (unsigned int *)&pdata->rss_key;
383 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
393 xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
398 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
399 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_LOOKUP_TABLE_TYPE, i,
400 pdata->rss_table[i]);
409 xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const uint8_t *key)
411 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
413 return (xgbe_write_rss_hash_key(pdata));
417 xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, const uint32_t *table)
421 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
422 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
424 return (xgbe_write_rss_lookup_table(pdata));
428 xgbe_enable_rss(struct xgbe_prv_data *pdata)
432 if (!pdata->hw_feat.rss)
436 ret = xgbe_write_rss_hash_key(pdata);
441 ret = xgbe_write_rss_lookup_table(pdata);
446 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
449 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
457 xgbe_disable_rss(struct xgbe_prv_data *pdata)
459 if (!pdata->hw_feat.rss)
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
470 xgbe_config_rss(struct xgbe_prv_data *pdata)
474 if (!pdata->hw_feat.rss)
478 if (pdata->enable_rss)
479 ret = xgbe_enable_rss(pdata);
481 ret = xgbe_disable_rss(pdata);
488 xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
495 for (i = 0; i < pdata->rx_q_count; i++)
496 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
500 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
503 reg_val = XGMAC_IOREAD(pdata, reg);
505 XGMAC_IOWRITE(pdata, reg, reg_val);
514 xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
521 for (i = 0; i < pdata->rx_q_count; i++) {
524 if (pdata->rx_rfd[i]) {
530 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
538 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
541 reg_val = XGMAC_IOREAD(pdata, reg);
549 XGMAC_IOWRITE(pdata, reg, reg_val);
558 xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
560 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
566 xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
568 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
574 xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
576 if (pdata->tx_pause)
577 xgbe_enable_tx_flow_control(pdata);
579 xgbe_disable_tx_flow_control(pdata);
585 xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
587 if (pdata->rx_pause)
588 xgbe_enable_rx_flow_control(pdata);
590 xgbe_disable_rx_flow_control(pdata);
596 xgbe_config_flow_control(struct xgbe_prv_data *pdata)
598 xgbe_config_tx_flow_control(pdata);
599 xgbe_config_rx_flow_control(pdata);
601 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
605 xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
611 if (pdata->channel_irq_mode)
612 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
613 pdata->channel_irq_mode);
615 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
617 for (i = 0; i < pdata->channel_count; i++) {
618 channel = pdata->channel[i];
647 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
659 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
669 xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
674 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
677 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
678 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
681 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
686 xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
693 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
696 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
697 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
700 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
704 xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
722 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
723 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
729 xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
732 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
735 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
738 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
741 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
744 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
752 xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
762 xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
765 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
768 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
771 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
774 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
782 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
790 xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
793 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
826 xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
834 XGMAC_IOREAD(pdata, MAC_VLANHTR));
837 bit_foreach(pdata->active_vlans, VLAN_NVID, vid) {
849 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
852 XGMAC_IOREAD(pdata, MAC_VLANHTR));
858 xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, unsigned int enable)
862 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
867 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
872 xgbe_disable_rx_vlan_filtering(pdata);
874 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
876 xgbe_enable_rx_vlan_filtering(pdata);
884 xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, unsigned int enable)
888 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
892 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
898 xgbe_set_mac_reg(struct xgbe_prv_data *pdata, char *addr, unsigned int *mac_reg)
921 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
923 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
928 xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
934 addn_macs = pdata->hw_feat.addn_mac;
936 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg);
941 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
945 xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
948 xgbe_set_mac_addn_addrs(pdata);
954 xgbe_set_mac_address(struct xgbe_prv_data *pdata, uint8_t *addr)
962 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
963 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
969 xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
973 pr_mode = ((if_getflags(pdata->netdev) & IFF_PROMISC) != 0);
974 am_mode = ((if_getflags(pdata->netdev) & IFF_ALLMULTI) != 0);
976 xgbe_set_promiscuous_mode(pdata, pr_mode);
977 xgbe_set_all_multicast_mode(pdata, am_mode);
979 xgbe_add_mac_addresses(pdata);
985 xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
992 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
995 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1001 xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1008 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1011 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1017 xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
1026 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1038 index = mmd_address & ~pdata->xpcs_window_mask;
1039 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1041 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1042 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1043 mmd_data = XPCS16_IOREAD(pdata, offset);
1044 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1050 xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
1059 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1071 index = mmd_address & ~pdata->xpcs_window_mask;
1072 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask);
1074 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1075 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1076 XPCS16_IOWRITE(pdata, offset, mmd_data);
1077 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1081 xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
1090 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1101 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1102 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1103 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
1104 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1110 xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
1119 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1130 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1131 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1132 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
1133 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1137 xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg)
1139 switch (pdata->vdata->xpcs_access) {
1141 return (xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg));
1145 return (xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg));
1150 xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, int mmd_reg,
1153 switch (pdata->vdata->xpcs_access) {
1155 return (xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data));
1159 return (xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data));
1179 xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg,
1184 mtx_lock_spin(&pdata->mdio_mutex);
1187 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1193 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1195 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
1198 mtx_unlock_spin(&pdata->mdio_mutex);
1202 mtx_unlock_spin(&pdata->mdio_mutex);
1207 xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, int reg)
1211 mtx_lock_spin(&pdata->mdio_mutex);
1214 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1219 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1221 if (msleep_spin(pdata, &pdata->mdio_mutex, "mdio_xfer", hz / 8) ==
1224 mtx_unlock_spin(&pdata->mdio_mutex);
1228 mtx_unlock_spin(&pdata->mdio_mutex);
1230 return (XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA));
1234 xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
1237 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
1251 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
1263 xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
1265 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
1272 xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
1274 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
1352 struct xgbe_prv_data *pdata = channel->pdata;
1394 pdata->ext_stats.rx_split_header_packets++;
1454 (if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
1472 pdata->ext_stats.rx_csum_errors++;
1480 pdata->ext_stats.rx_vxlan_csum_errors++;
1521 struct xgbe_prv_data *pdata = channel->pdata;
1570 struct xgbe_prv_data *pdata = channel->pdata;
1618 __xgbe_exit(struct xgbe_prv_data *pdata)
1623 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1627 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1637 xgbe_exit(struct xgbe_prv_data *pdata)
1644 ret = __xgbe_exit(pdata);
1650 return (__xgbe_exit(pdata));
1654 xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1658 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1661 for (i = 0; i < pdata->tx_q_count; i++)
1662 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1665 for (i = 0; i < pdata->tx_q_count; i++) {
1667 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
1679 xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1683 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
1690 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
1691 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
1692 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
1693 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
1695 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
1698 if (pdata->vdata->tx_desc_prefetch)
1699 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
1700 pdata->vdata->tx_desc_prefetch);
1702 if (pdata->vdata->rx_desc_prefetch)
1703 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
1704 pdata->vdata->rx_desc_prefetch);
1708 xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1710 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
1711 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
1712 if (pdata->awarcr)
1713 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
1717 xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1722 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1725 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1726 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1728 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1732 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1736 xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
1742 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
1755 pdata->rx_rfa[queue] = 0;
1756 pdata->rx_rfd[queue] = 0;
1762 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
1763 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
1769 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
1770 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
1790 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
1791 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
1793 queue, pdata->rx_rfa[queue], pdata->rx_rfd[queue]);
1797 xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
1803 for (i = 0; i < pdata->rx_q_count; i++) {
1808 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
1813 xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
1817 for (i = 0; i < pdata->rx_q_count; i++) {
1819 pdata->rx_rfa[i], pdata->rx_rfd[i]);
1821 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
1822 pdata->rx_rfa[i]);
1823 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
1824 pdata->rx_rfd[i]);
1827 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1832 xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
1835 return (min_t(unsigned int, pdata->tx_max_fifo_size,
1836 pdata->hw_feat.tx_fifo_size));
1840 xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
1843 return (min_t(unsigned int, pdata->rx_max_fifo_size,
1844 pdata->hw_feat.rx_fifo_size));
1894 xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1900 fifo_size = xgbe_get_tx_fifo_size(pdata);
1903 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
1905 for (i = 0; i < pdata->tx_q_count; i++) {
1906 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
1908 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1912 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
1916 xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1926 fifo_size = xgbe_get_rx_fifo_size(pdata);
1927 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
1929 fifo_size, pdata->rx_q_count, prio_queues);
1932 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
1936 for (i = 0; i < pdata->rx_q_count; i++) {
1937 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
1939 XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1942 xgbe_calculate_flow_control_threshold(pdata, fifo);
1943 xgbe_config_flow_control_threshold(pdata);
1946 pdata->rx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
1950 xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
1961 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1962 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1964 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1967 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1969 pdata->q2tc_map[queue++] = i;
1974 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1976 pdata->q2tc_map[queue++] = i;
1981 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
1992 pdata->prio2q_map[prio++] = i;
1998 pdata->prio2q_map[prio++] = i;
2006 XGMAC_IOWRITE(pdata, reg, reg_val);
2014 for (i = 0; i < pdata->rx_q_count;) {
2017 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2020 XGMAC_IOWRITE(pdata, reg, reg_val);
2028 xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2030 xgbe_set_mac_address(pdata, if_getlladdr(pdata->netdev));
2036 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, RA, 1);
2039 if (pdata->hw_feat.hash_table_size) {
2040 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2041 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2042 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2047 xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2051 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2053 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2057 xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2059 xgbe_set_speed(pdata, pdata->phy_speed);
2063 xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2065 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM))
2066 xgbe_enable_rx_csum(pdata);
2068 xgbe_disable_rx_csum(pdata);
2072 xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2075 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2076 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2079 xgbe_update_vlan_hash_table(pdata);
2081 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWFILTER)) {
2083 xgbe_enable_rx_vlan_filtering(pdata);
2086 xgbe_disable_rx_vlan_filtering(pdata);
2089 if ((if_getcapenable(pdata->netdev) & IFCAP_VLAN_HWTAGGING)) {
2091 xgbe_enable_rx_vlan_stripping(pdata);
2094 xgbe_disable_rx_vlan_stripping(pdata);
2099 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2104 if (pdata->vdata->mmc_64bit) {
2133 val = XGMAC_IOREAD(pdata, reg_lo);
2136 val |= ((uint64_t)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2142 xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2144 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2145 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2149 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2153 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2157 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2161 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2165 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2169 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2173 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2177 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2181 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2185 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2189 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2193 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2197 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2201 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2205 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2209 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2213 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2217 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2221 xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2223 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2224 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2228 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2232 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2236 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2240 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2244 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2248 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2252 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2256 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2260 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2264 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2268 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2272 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2276 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2280 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2284 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2288 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2292 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2296 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2300 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2304 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2308 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2312 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2316 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2320 xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2322 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2325 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2328 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2331 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2334 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2337 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2340 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2343 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2346 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2349 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2352 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2355 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2358 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2361 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2364 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2367 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2370 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2373 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2376 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2379 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2382 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2385 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2388 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2391 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2394 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2397 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2400 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2403 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2406 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2409 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2412 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2415 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2418 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2421 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2424 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2427 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2430 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2433 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2436 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2439 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2442 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2445 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2448 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2451 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2455 xgbe_config_mmc(struct xgbe_prv_data *pdata)
2458 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2461 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2465 xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
2476 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
2490 xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
2496 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
2497 return (xgbe_txq_prepare_tx_stop(pdata, queue));
2517 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2532 xgbe_enable_tx(struct xgbe_prv_data *pdata)
2537 for (i = 0; i < pdata->channel_count; i++) {
2538 if (!pdata->channel[i]->tx_ring)
2541 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
2545 for (i = 0; i < pdata->tx_q_count; i++)
2546 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2550 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2554 xgbe_disable_tx(struct xgbe_prv_data *pdata)
2559 for (i = 0; i < pdata->tx_q_count; i++)
2560 xgbe_prepare_tx_stop(pdata, i);
2563 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2566 for (i = 0; i < pdata->tx_q_count; i++)
2567 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2570 for (i = 0; i < pdata->channel_count; i++) {
2571 if (!pdata->channel[i]->tx_ring)
2574 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
2579 xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, unsigned int queue)
2590 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
2604 xgbe_enable_rx(struct xgbe_prv_data *pdata)
2609 for (i = 0; i < pdata->channel_count; i++) {
2610 if (!pdata->channel[i]->rx_ring)
2613 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
2618 for (i = 0; i < pdata->rx_q_count; i++)
2620 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2623 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2624 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2625 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2626 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2630 xgbe_disable_rx(struct xgbe_prv_data *pdata)
2635 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2636 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2637 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2638 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2641 for (i = 0; i < pdata->rx_q_count; i++)
2642 xgbe_prepare_rx_stop(pdata, i);
2645 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2648 for (i = 0; i < pdata->channel_count; i++) {
2649 if (!pdata->channel[i]->rx_ring)
2652 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
2657 xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2662 for (i = 0; i < pdata->channel_count; i++) {
2663 if (!pdata->channel[i]->tx_ring)
2666 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
2670 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2674 xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2679 for (i = 0; i < pdata->tx_q_count; i++)
2680 xgbe_prepare_tx_stop(pdata, i);
2683 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2686 for (i = 0; i < pdata->channel_count; i++) {
2687 if (!pdata->channel[i]->tx_ring)
2690 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
2695 xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2700 for (i = 0; i < pdata->channel_count; i++) {
2701 if (!pdata->channel[i]->rx_ring)
2704 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
2709 xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2714 for (i = 0; i < pdata->channel_count; i++) {
2715 if (!pdata->channel[i]->rx_ring)
2718 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
2723 xgbe_init(struct xgbe_prv_data *pdata)
2725 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2729 ret = xgbe_flush_tx_queues(pdata);
2738 xgbe_config_dma_bus(pdata);
2739 xgbe_config_dma_cache(pdata);
2740 xgbe_config_osp_mode(pdata);
2741 xgbe_config_pbl_val(pdata);
2742 xgbe_config_rx_coalesce(pdata);
2743 xgbe_config_tx_coalesce(pdata);
2744 xgbe_config_rx_buffer_size(pdata);
2745 xgbe_config_tso_mode(pdata);
2746 xgbe_config_sph_mode(pdata);
2747 xgbe_config_rss(pdata);
2748 desc_if->wrapper_tx_desc_init(pdata);
2749 desc_if->wrapper_rx_desc_init(pdata);
2750 xgbe_enable_dma_interrupts(pdata);
2755 xgbe_config_mtl_mode(pdata);
2756 xgbe_config_queue_mapping(pdata);
2757 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2758 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2759 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2760 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2761 xgbe_config_tx_fifo_size(pdata);
2762 xgbe_config_rx_fifo_size(pdata);
2766 xgbe_enable_mtl_interrupts(pdata);
2771 xgbe_config_mac_address(pdata);
2772 xgbe_config_rx_mode(pdata);
2773 xgbe_config_jumbo_enable(pdata);
2774 xgbe_config_flow_control(pdata);
2775 xgbe_config_mac_speed(pdata);
2776 xgbe_config_checksum_offload(pdata);
2777 xgbe_config_vlan_support(pdata);
2778 xgbe_config_mmc(pdata);
2779 xgbe_enable_mac_interrupts(pdata);