Lines Matching +full:queue +full:- +full:sizes

4  * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
135 /* DMA register entry bit positions and sizes */
218 /* DMA channel register entry bit positions and sizes */
367 /* MAC register entry bit positions and sizes */
703 /* MMC register entry bit positions and sizes */
818 /* MTL register entry bit positions and sizes */
824 /* MTL queue register offsets
825  *   Multiple queues can be active.  The first queue has registers
826  *   that begin at 0x1100.  Each subsequent queue has registers that
827  *   are accessed using an offset of 0x80 from the previous queue.
846 /* MTL queue register entry bit positions and sizes */
880 /* MTL queue register value */
909  *   that begin at 0x1100.  Each subsequent queue has registers that
910  *   are accessed using an offset of 0x80 from the previous queue.
919 /* MTL traffic class register entry bit positions and sizes */
942 /* PCS register entry bit positions and sizes */
953 /* SerDes integration register entry bit positions and sizes */
980 /* SerDes RxTx register entry bit positions and sizes */
1012 /* MAC Control register entry bit positions and sizes */
1141 /* I2C Control register entry bit positions and sizes */
1183 /* Descriptor/Packet entry bit positions and sizes */
1451 	(((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1455 	(_var) &= ~(((0x1 << (_width)) - 1) << (_index));		\
1456 	(_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index));	\
1460 	((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1464 	(_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index)));	\
1466 			      ((0x1 << (_width)) - 1)) << (_index)));	\
1505 	bus_read_4((_pdata)->xgmac_res, _reg)
1513 	bus_write_4((_pdata)->xgmac_res, _reg, (_val))
1524 /* Macros for reading or writing MTL queue or traffic class registers
1526  *  base register value is calculated by the queue or traffic class number
1529 	bus_read_4((_pdata)->xgmac_res,					\
1538 	bus_write_4((_pdata)->xgmac_res,				\
1555 	bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg)
1563 	bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle,	\
1589 	bus_write_4((_pdata)->xpcs_res, (_off), _val)
1592 	bus_read_4((_pdata)->xpcs_res, (_off))
1595 	bus_write_2((_pdata)->xpcs_res, (_off), _val)
1598 	bus_read_2((_pdata)->xpcs_res, (_off))
1614 	bus_read_2((_pdata)->sir0_res, _reg)
1622 	bus_write_2((_pdata)->sir0_res, _reg, (_val))
1634 	bus_read_2((_pdata)->sir1_res, _reg)
1642 	bus_write_2((_pdata)->sir1_res, _reg, (_val))
1657 	bus_read_2((_pdata)->rxtx_res, _reg)
1665 	bus_write_2((_pdata)->rxtx_res, _reg, (_val))
1690 	bus_read_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET)
1698 	bus_write_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET,	\
1724 	bus_read_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET)
1732 	bus_write_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET,	\
1750 	((_pdata)->hw_if.read_mmd_regs((_pdata), 0,			\
1757 	((_pdata)->hw_if.write_mmd_regs((_pdata), 0,			\