Lines Matching +full:smi +full:- +full:mdio
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
54 #include "xgbe-common.h"
138 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
144 { -1, 0 }
320 struct xgbe_prv_data *pdata = &sc->pdata;
335 struct xgbe_prv_data *pdata = &sc->pdata;
348 struct xgbe_prv_data *pdata = &sc->pdata;
349 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
350 if_t ifp = pdata->netdev;
353 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
354 pdata->phy_link);
360 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
363 switch (IFM_SUBTYPE(mii->mii_media_active)) {
366 pdata->phy.link = 1;
371 pdata->phy.link = 1;
374 pdata->phy.link = 0;
378 pdata->phy_link = 0;
380 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
406 sc->pdata.dev = dev = iflib_get_dev(ctx);
407 sc->sctx = sctx = iflib_get_sctx(ctx);
408 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
409 sc->media = iflib_get_media(ctx);
410 sc->ctx = ctx;
411 sc->link_status = LINK_STATE_DOWN;
412 pdata = &sc->pdata;
413 pdata->netdev = iflib_get_ifp(ctx);
415 spin_lock_init(&pdata->xpcs_lock);
418 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
419 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
422 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
423 pdata->num_active_vlans = 0;
428 sc->pdata.vdata = &xgbe_v2a;
430 sc->pdata.vdata = &xgbe_v2b;
439 sc->pdata.xgmac_res = mac_res[0];
440 sc->pdata.xpcs_res = mac_res[1];
453 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
454 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
456 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
457 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
461 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
462 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
463 pdata->xpcs_window <<= 6;
464 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
465 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
466 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
468 pdata->xpcs_window_def_reg);
470 pdata->xpcs_window_sel_reg);
472 pdata->xpcs_window);
474 pdata->xpcs_window_size);
476 pdata->xpcs_window_mask);
484 pdata->mac_addr[0] = ma_lo & 0xff;
485 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
486 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
487 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
488 pdata->mac_addr[4] = ma_hi & 0xff;
489 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
495 iflib_set_mac(ctx, pdata->mac_addr);
498 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
499 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
502 pdata->coherent = 1;
503 pdata->arcr = XGBE_DMA_PCI_ARCR;
504 pdata->awcr = XGBE_DMA_PCI_AWCR;
505 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
508 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
509 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
510 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
511 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
512 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
513 DBGPR("port property 0 = %#010x\n", pdata->pp0);
514 DBGPR("port property 1 = %#010x\n", pdata->pp1);
515 DBGPR("port property 2 = %#010x\n", pdata->pp2);
516 DBGPR("port property 3 = %#010x\n", pdata->pp3);
517 DBGPR("port property 4 = %#010x\n", pdata->pp4);
520 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
522 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
524 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
526 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
529 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
531 pdata->tx_max_q_count, pdata->rx_max_q_count);
536 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
538 pdata->tx_max_fifo_size *= 16384;
539 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
540 pdata->vdata->tx_max_fifo_size);
541 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
543 pdata->rx_max_fifo_size *= 16384;
544 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
545 pdata->vdata->rx_max_fifo_size);
547 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
559 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
562 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
563 taskqueue_thread_enqueue, &pdata->dev_workqueue);
564 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
578 taskqueue_free(pdata->dev_workqueue);
585 free(pdata->active_vlans, M_AXGBE);
593 xgbe_init_function_ptrs_dev(&pdata->hw_if);
594 xgbe_init_function_ptrs_phy(&pdata->phy_if);
595 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
596 xgbe_init_function_ptrs_desc(&pdata->desc_if);
598 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
605 struct xgbe_prv_data *pdata = &sc->pdata;
614 if (!pdata->tx_max_channel_count)
615 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
616 if (!pdata->rx_max_channel_count)
617 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
619 if (!pdata->tx_max_q_count)
620 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
621 if (!pdata->rx_max_q_count)
622 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
626 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
629 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
633 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
635 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
640 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
641 pdata->tx_ring_count = min(pdata->tx_ring_count,
642 pdata->tx_max_channel_count);
643 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
645 pdata->tx_q_count = pdata->tx_ring_count;
647 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
648 pdata->rx_ring_count = min(pdata->rx_ring_count,
649 pdata->rx_max_channel_count);
651 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
654 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
656 pdata->tx_max_q_count, pdata->rx_max_q_count);
658 pdata->tx_ring_count, pdata->rx_ring_count);
660 pdata->tx_q_count, pdata->rx_q_count);
666 struct xgbe_prv_data *pdata = &sc->pdata;
667 if_softc_ctx_t scctx = sc->scctx;
668 if_shared_ctx_t sctx = sc->sctx;
671 scctx->isc_nrxqsets = pdata->rx_q_count;
672 scctx->isc_ntxqsets = pdata->tx_q_count;
673 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
674 scctx->isc_tx_nsegments = 32;
676 for (i = 0; i < sctx->isc_ntxqs; i++) {
677 scctx->isc_txqsizes[i] =
678 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
680 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
683 for (i = 0; i < sctx->isc_nrxqs; i++) {
684 scctx->isc_rxqsizes[i] =
685 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
687 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
690 scctx->isc_tx_tso_segments_max = 32;
691 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
692 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
700 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
703 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
708 scctx->isc_capabilities = scctx->isc_capenable;
714 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
716 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
717 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
719 scctx->isc_txrx = &axgbe_txrx;
732 rss_getkey((uint8_t *)&pdata->rss_key);
737 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
739 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
741 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
743 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
745 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
746 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
747 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
753 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
754 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
756 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
757 i % pdata->rx_ring_count);
767 struct xgbe_prv_data *pdata = &sc->pdata;
771 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
772 pdata->rx_ring_count);
775 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
784 free(pdata->channel[j], M_AXGBE);
785 pdata->channel[j] = NULL;
790 pdata->channel[i] = channel;
793 pdata->total_channel_count = count;
794 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
798 channel = pdata->channel[i];
799 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
801 channel->pdata = pdata;
802 channel->queue_index = i;
803 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
804 bus_space_subregion(channel->dma_tag,
805 rman_get_bushandle(pdata->xgmac_res),
807 &channel->dma_handle);
808 channel->tx_ring = NULL;
809 channel->rx_ring = NULL;
818 struct xgbe_prv_data *pdata = &sc->pdata;
821 for (i = 0; i < pdata->total_channel_count ; i++) {
822 free(pdata->channel[i], M_AXGBE);
823 pdata->channel[i] = NULL;
826 pdata->total_channel_count = 0;
827 pdata->channel_count = 0;
838 prev_state = pdata->phy.link;
840 pdata->phy_if.phy_status(pdata);
842 if (prev_state != pdata->phy.link) {
843 pdata->phy_link = pdata->phy.link;
844 axgbe_if_update_admin_status(sc->ctx);
847 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
855 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
861 callout_init(&pdata->service_timer, 1);
867 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
873 callout_drain(&pdata->service_timer);
874 callout_stop(&pdata->service_timer);
894 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
896 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
898 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
901 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
904 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
907 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
970 channel = pdata->channel[i];
1237 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1241 pdata->hw_if.read_mmc_stats(pdata);
1244 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1246 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1248 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1250 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1252 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1254 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1256 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1258 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1260 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1262 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1264 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1266 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1268 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1270 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1272 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1274 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1276 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1278 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1280 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1282 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1284 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1286 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1288 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1290 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1292 MMC_RXRUNTERROR, stats->rxrunterror);
1294 MMC_RXJABBERERROR, stats->rxjabbererror);
1296 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1298 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1300 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1302 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1304 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1306 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1308 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1310 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1312 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1314 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1316 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1318 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1320 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1322 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1324 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1369 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1377 pdata->blen = DMA_SBMR_BLEN_64;
1378 pdata->pbl = DMA_PBL_128;
1379 pdata->aal = 1;
1380 pdata->rd_osr_limit = 8;
1381 pdata->wr_osr_limit = 8;
1382 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1383 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1384 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1385 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1386 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1387 pdata->pause_autoneg = 1;
1388 pdata->phy_speed = SPEED_UNKNOWN;
1389 pdata->power_down = 0;
1390 pdata->enable_rss = 1;
1397 struct xgbe_prv_data *pdata = &sc->pdata;
1398 if_t ifp = pdata->netdev;
1399 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1400 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1401 if_softc_ctx_t scctx = sc->scctx;
1405 pdata->sph_enable = axgbe_sph_enable;
1408 pdata->tx_sec_period = ticks;
1409 pdata->tx_ded_period = ticks;
1410 pdata->rx_sec_period = ticks;
1411 pdata->rx_ded_period = ticks;
1412 pdata->desc_sec_period = ticks;
1413 pdata->desc_ded_period = ticks;
1416 ret = hw_if->exit(&sc->pdata);
1426 if (!pdata->tx_max_fifo_size)
1427 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1428 if (!pdata->rx_max_fifo_size)
1429 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1432 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1436 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1438 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1441 if (pdata->channel_irq_count) {
1442 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1443 pdata->channel_irq_count);
1444 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1445 pdata->channel_irq_count);
1448 pdata->tx_ring_count, pdata->tx_q_count,
1449 pdata->rx_ring_count, pdata->rx_q_count);
1453 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1454 scctx->isc_nrxqsets);
1455 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1460 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1461 phy_if->phy_init(pdata);
1464 xgbe_init_rx_coalesce(&sc->pdata);
1465 xgbe_init_tx_coalesce(&sc->pdata);
1467 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1468 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1469 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1470 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1471 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1472 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1473 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1474 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1475 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1476 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1477 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1478 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1479 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1482 pdata->phy_link = -1;
1483 pdata->phy_speed = SPEED_UNKNOWN;
1484 ret = phy_if->phy_reset(pdata);
1489 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1490 pdata->rx_buf_size = ret;
1498 set_bit(XGBE_DOWN, &pdata->dev_state);
1501 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1502 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1514 bus_teardown_intr(pdata->dev, res, tag);
1517 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1524 struct xgbe_prv_data *pdata = &sc->pdata;
1525 if_softc_ctx_t scctx = sc->scctx;
1530 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1533 iflib_irq_free(ctx, &pdata->dev_irq);
1536 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1537 pdata->ecc_rid);
1540 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1541 pdata->i2c_rid);
1544 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1545 pdata->an_rid);
1547 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1549 channel = pdata->channel[i];
1550 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1551 irq.ii_res = channel->dma_irq_res;
1552 irq.ii_tag = channel->dma_irq_tag;
1561 struct xgbe_prv_data *pdata = &sc->pdata;
1562 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1565 mac_res[0] = pdata->xgmac_res;
1566 mac_res[1] = pdata->xpcs_res;
1568 phy_if->phy_stop(pdata);
1569 phy_if->phy_exit(pdata);
1575 taskqueue_free(pdata->dev_workqueue);
1581 free(pdata->active_vlans, M_AXGBE);
1591 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1592 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1595 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1600 hw_if->init(pdata);
1602 ret = phy_if->phy_start(pdata);
1605 ret = hw_if->exit(pdata);
1611 hw_if->enable_tx(pdata);
1612 hw_if->enable_rx(pdata);
1616 clear_bit(XGBE_DOWN, &pdata->dev_state);
1620 xgbe_dump_dma_registers(pdata, -1);
1630 struct xgbe_prv_data *pdata = &sc->pdata;
1639 struct xgbe_prv_data *pdata = &sc->pdata;
1640 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1643 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1649 taskqueue_drain_all(pdata->dev_workqueue);
1651 hw_if->disable_tx(pdata);
1652 hw_if->disable_rx(pdata);
1654 ret = hw_if->exit(pdata);
1658 set_bit(XGBE_DOWN, &pdata->dev_state);
1670 /* TODO - implement */
1676 /* TODO - implement */
1684 struct xgbe_prv_data *pdata = &sc->pdata;
1685 if_softc_ctx_t scctx = sc->scctx;
1690 MPASS(scctx->isc_ntxqsets > 0);
1691 MPASS(scctx->isc_ntxqsets == ntxqsets);
1695 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1699 channel = pdata->channel[i];
1709 channel->tx_ring = tx_ring;
1712 tx_ring->rdata =
1713 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1717 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1718 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1719 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1720 spin_lock_init(&tx_ring->lock);
1724 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1732 channel = pdata->channel[j];
1734 tx_ring = channel->tx_ring;
1736 if (tx_ring && tx_ring->rdata)
1737 free(tx_ring->rdata, M_AXGBE);
1739 free(channel->tx_ring, M_AXGBE);
1741 channel->tx_ring = NULL;
1753 struct xgbe_prv_data *pdata = &sc->pdata;
1754 if_softc_ctx_t scctx = sc->scctx;
1759 MPASS(scctx->isc_nrxqsets > 0);
1760 MPASS(scctx->isc_nrxqsets == nrxqsets);
1761 if (!pdata->sph_enable) {
1768 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1772 channel = pdata->channel[i];
1782 channel->rx_ring = rx_ring;
1785 rx_ring->rdata =
1786 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1790 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1791 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1792 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1793 spin_lock_init(&rx_ring->lock);
1797 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1805 channel = pdata->channel[j];
1807 rx_ring = channel->rx_ring;
1809 if (rx_ring && rx_ring->rdata)
1810 free(rx_ring->rdata, M_AXGBE);
1812 free(channel->rx_ring, M_AXGBE);
1814 channel->rx_ring = NULL;
1825 struct xgbe_prv_data *pdata = &sc->pdata;
1826 if_softc_ctx_t scctx = sc->scctx;
1827 if_shared_ctx_t sctx = sc->sctx;
1833 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1835 channel = pdata->channel[i];
1837 tx_ring = channel->tx_ring;
1838 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1839 if (tx_ring && tx_ring->rdata)
1840 free(tx_ring->rdata, M_AXGBE);
1842 free(channel->tx_ring, M_AXGBE);
1843 channel->tx_ring = NULL;
1846 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1848 channel = pdata->channel[i];
1850 rx_ring = channel->rx_ring;
1851 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1852 if (rx_ring && rx_ring->rdata)
1853 free(rx_ring->rdata, M_AXGBE);
1855 free(channel->rx_ring, M_AXGBE);
1856 channel->rx_ring = NULL;
1866 struct xgbe_prv_data *pdata = &sc->pdata;
1867 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1869 if (!bit_test(pdata->active_vlans, vtag)) {
1872 bit_set(pdata->active_vlans, vtag);
1873 hw_if->update_vlan_hash_table(pdata);
1874 pdata->num_active_vlans++;
1877 pdata->num_active_vlans);
1888 struct xgbe_prv_data *pdata = &sc->pdata;
1889 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1891 if (pdata->num_active_vlans == 0) {
1896 if (bit_test(pdata->active_vlans, vtag)){
1897 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1899 bit_clear(pdata->active_vlans, vtag);
1900 hw_if->update_vlan_hash_table(pdata);
1901 pdata->num_active_vlans--;
1904 pdata->num_active_vlans);
1927 struct xgbe_prv_data *pdata = &sc->pdata;
1928 if_softc_ctx_t scctx = sc->scctx;
1934 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1936 pdata->isr_as_tasklet = 1;
1938 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1939 pdata->irq_count = 1;
1940 pdata->channel_irq_count = 1;
1945 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1951 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1961 pdata->ecc_rid = rid;
1962 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1964 if (!pdata->ecc_irq_res) {
1970 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1971 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1980 pdata->i2c_rid = rid;
1981 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1983 if (!pdata->i2c_irq_res) {
1989 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1990 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1999 pdata->an_rid = rid;
2000 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2002 if (!pdata->an_irq_res) {
2008 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2009 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2016 pdata->per_channel_irq = 1;
2017 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2019 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2021 channel = pdata->channel[i];
2025 axgbe_msix_que, channel, channel->queue_index, buf);
2033 channel->dma_irq_rid = rid;
2034 channel->dma_irq_res = irq.ii_res;
2035 channel->dma_irq_tag = irq.ii_tag;
2037 __func__, scctx->isc_nrxqsets, i, rid);
2039 pdata->irq_count = msix;
2040 pdata->channel_irq_count = scctx->isc_nrxqsets;
2042 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2044 channel = pdata->channel[i];
2047 irq.ii_res = channel->dma_irq_res;
2049 channel->queue_index, buf);
2058 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2061 if (channel->tx_ring && channel->rx_ring)
2063 else if (channel->tx_ring)
2065 else if (channel->rx_ring)
2068 return (-1);
2071 __func__, channel->queue_index, int_id);
2072 return (hw_if->enable_int(channel, int_id));
2078 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2081 if (channel->tx_ring && channel->rx_ring)
2083 else if (channel->tx_ring)
2085 else if (channel->rx_ring)
2091 __func__, channel->queue_index, int_id);
2092 hw_if->disable_int(channel, int_id);
2100 for (i = 0; i < pdata->channel_count; i++)
2101 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2108 struct xgbe_prv_data *pdata = channel->pdata;
2112 __func__, channel->queue_index,
2137 struct xgbe_prv_data *pdata = &sc->pdata;
2139 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2150 for (i = 0; i < pdata->channel_count; i++) {
2155 channel = pdata->channel[i];
2159 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2167 if (!pdata->per_channel_irq &&
2185 pdata->ext_stats.rx_buffer_unavailable++;
2204 hw_if->tx_mmc_int(pdata);
2207 hw_if->rx_mmc_int(pdata);
2209 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2227 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2233 /* TODO - implement */
2241 sc->pdata.phy_if.an_isr(&sc->pdata);
2248 struct xgbe_prv_data *pdata = &sc->pdata;
2251 if (qid < pdata->tx_q_count) {
2252 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2267 struct xgbe_prv_data *pdata = &sc->pdata;
2270 if (qid < pdata->rx_q_count) {
2271 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2286 struct xgbe_prv_data *pdata = &sc->pdata;
2289 pdata->phy_link, sc->link_status, pdata->phy.speed);
2291 if (pdata->phy_link < 0)
2294 if (pdata->phy_link) {
2295 if (sc->link_status == LINK_STATE_DOWN) {
2296 sc->link_status = LINK_STATE_UP;
2297 if (pdata->phy.speed & SPEED_10000)
2300 else if (pdata->phy.speed & SPEED_2500)
2303 else if (pdata->phy.speed & SPEED_1000)
2306 else if (pdata->phy.speed & SPEED_100)
2309 else if (pdata->phy.speed & SPEED_10)
2314 if (sc->link_status == LINK_STATE_UP) {
2315 sc->link_status = LINK_STATE_DOWN;
2327 sx_xlock(&sc->pdata.an_mutex);
2328 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2331 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2333 sc->pdata.phy.speed = SPEED_10000;
2334 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2337 sc->pdata.phy.speed = SPEED_2500;
2338 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2341 sc->pdata.phy.speed = SPEED_1000;
2342 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2345 sc->pdata.phy.speed = SPEED_100;
2346 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2349 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2352 sx_xunlock(&sc->pdata.an_mutex);
2354 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2361 struct xgbe_prv_data *pdata = &sc->pdata;
2362 if_t ifp = pdata->netdev;
2404 struct xgbe_prv_data *pdata = &sc->pdata;
2405 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2407 pdata->hw_if.read_mmc_stats(pdata);
2411 return (pstats->rxframecount_gb);
2413 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2414 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2416 return (pstats->txframecount_gb);
2418 return (pstats->txframecount_gb - pstats->txframecount_g);
2420 return (pstats->rxoctetcount_gb);
2422 return (pstats->txoctetcount_gb);
2432 struct xgbe_prv_data *pdata = &sc->pdata;
2438 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2439 pdata->rx_buf_size = ret;
2442 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2450 struct xgbe_prv_data *pdata = &sc->pdata;
2452 ifmr->ifm_status = IFM_AVALID;
2453 if (!sc->pdata.phy.link)
2456 ifmr->ifm_active = IFM_ETHER;
2457 ifmr->ifm_status |= IFM_ACTIVE;
2459 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2460 pdata->phy_if.phy_impl.cur_mode(pdata));
2461 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2463 ifmr->ifm_active |= IFM_FDX;
2464 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2465 ifmr->ifm_active |= IFM_ETH_RXPAUSE;