Lines Matching defs:pdata
320 struct xgbe_prv_data *pdata = &sc->pdata;
325 val = xgbe_phy_mii_read(pdata, phy, reg);
335 struct xgbe_prv_data *pdata = &sc->pdata;
339 xgbe_phy_mii_write(pdata, phy, reg, val);
348 struct xgbe_prv_data *pdata = &sc->pdata;
349 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
350 if_t ifp = pdata->netdev;
353 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
354 pdata->phy_link);
366 pdata->phy.link = 1;
371 pdata->phy.link = 1;
374 pdata->phy.link = 0;
378 pdata->phy_link = 0;
380 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
386 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
395 struct xgbe_prv_data *pdata;
406 sc->pdata.dev = dev = iflib_get_dev(ctx);
412 pdata = &sc->pdata;
413 pdata->netdev = iflib_get_ifp(ctx);
415 spin_lock_init(&pdata->xpcs_lock);
418 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
419 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
422 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
423 pdata->num_active_vlans = 0;
428 sc->pdata.vdata = &xgbe_v2a;
430 sc->pdata.vdata = &xgbe_v2b;
439 sc->pdata.xgmac_res = mac_res[0];
440 sc->pdata.xpcs_res = mac_res[1];
453 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
454 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
456 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
457 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
461 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
462 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
463 pdata->xpcs_window <<= 6;
464 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
465 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
466 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
468 pdata->xpcs_window_def_reg);
470 pdata->xpcs_window_sel_reg);
472 pdata->xpcs_window);
474 pdata->xpcs_window_size);
476 pdata->xpcs_window_mask);
479 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
482 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
483 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
484 pdata->mac_addr[0] = ma_lo & 0xff;
485 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
486 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
487 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
488 pdata->mac_addr[4] = ma_hi & 0xff;
489 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
495 iflib_set_mac(ctx, pdata->mac_addr);
498 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
499 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
502 pdata->coherent = 1;
503 pdata->arcr = XGBE_DMA_PCI_ARCR;
504 pdata->awcr = XGBE_DMA_PCI_AWCR;
505 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
508 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
509 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
510 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
511 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
512 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
513 DBGPR("port property 0 = %#010x\n", pdata->pp0);
514 DBGPR("port property 1 = %#010x\n", pdata->pp1);
515 DBGPR("port property 2 = %#010x\n", pdata->pp2);
516 DBGPR("port property 3 = %#010x\n", pdata->pp3);
517 DBGPR("port property 4 = %#010x\n", pdata->pp4);
520 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
522 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
524 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
526 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
529 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
531 pdata->tx_max_q_count, pdata->rx_max_q_count);
536 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
538 pdata->tx_max_fifo_size *= 16384;
539 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
540 pdata->vdata->tx_max_fifo_size);
541 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
543 pdata->rx_max_fifo_size *= 16384;
544 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
545 pdata->vdata->rx_max_fifo_size);
547 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
559 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
562 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
563 taskqueue_thread_enqueue, &pdata->dev_workqueue);
564 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
573 xgbe_init_timers(pdata);
578 taskqueue_free(pdata->dev_workqueue);
585 free(pdata->active_vlans, M_AXGBE);
591 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
593 xgbe_init_function_ptrs_dev(&pdata->hw_if);
594 xgbe_init_function_ptrs_phy(&pdata->phy_if);
595 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
596 xgbe_init_function_ptrs_desc(&pdata->desc_if);
598 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
605 struct xgbe_prv_data *pdata = &sc->pdata;
609 xgbe_init_all_fptrs(pdata);
612 xgbe_get_all_hw_features(pdata);
614 if (!pdata->tx_max_channel_count)
615 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
616 if (!pdata->rx_max_channel_count)
617 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
619 if (!pdata->tx_max_q_count)
620 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
621 if (!pdata->rx_max_q_count)
622 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
633 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
640 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
641 pdata->tx_ring_count = min(pdata->tx_ring_count,
642 pdata->tx_max_channel_count);
643 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
645 pdata->tx_q_count = pdata->tx_ring_count;
647 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
648 pdata->rx_ring_count = min(pdata->rx_ring_count,
649 pdata->rx_max_channel_count);
651 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
654 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
656 pdata->tx_max_q_count, pdata->rx_max_q_count);
658 pdata->tx_ring_count, pdata->rx_ring_count);
660 pdata->tx_q_count, pdata->rx_q_count);
666 struct xgbe_prv_data *pdata = &sc->pdata;
671 scctx->isc_nrxqsets = pdata->rx_q_count;
672 scctx->isc_ntxqsets = pdata->tx_q_count;
673 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
723 axgbe_initialize_rss_mapping(struct xgbe_prv_data *pdata)
732 rss_getkey((uint8_t *)&pdata->rss_key);
737 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
739 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
741 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
743 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
745 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
746 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
747 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
753 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
754 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
756 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
757 i % pdata->rx_ring_count);
767 struct xgbe_prv_data *pdata = &sc->pdata;
771 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
772 pdata->rx_ring_count);
775 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
784 free(pdata->channel[j], M_AXGBE);
785 pdata->channel[j] = NULL;
790 pdata->channel[i] = channel;
793 pdata->total_channel_count = count;
794 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
798 channel = pdata->channel[i];
801 channel->pdata = pdata;
803 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
805 rman_get_bushandle(pdata->xgmac_res),
818 struct xgbe_prv_data *pdata = &sc->pdata;
821 for (i = 0; i < pdata->total_channel_count ; i++) {
822 free(pdata->channel[i], M_AXGBE);
823 pdata->channel[i] = NULL;
826 pdata->total_channel_count = 0;
827 pdata->channel_count = 0;
833 struct xgbe_prv_data *pdata = ctx;
834 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
838 prev_state = pdata->phy.link;
840 pdata->phy_if.phy_status(pdata);
842 if (prev_state != pdata->phy.link) {
843 pdata->phy_link = pdata->phy.link;
847 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
853 struct xgbe_prv_data *pdata = data;
855 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
859 xgbe_init_timers(struct xgbe_prv_data *pdata)
861 callout_init(&pdata->service_timer, 1);
865 xgbe_start_timers(struct xgbe_prv_data *pdata)
867 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
871 xgbe_stop_timers(struct xgbe_prv_data *pdata)
873 callout_drain(&pdata->service_timer);
874 callout_stop(&pdata->service_timer);
878 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
883 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
885 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
887 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
889 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
891 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
893 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
895 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
897 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
900 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
903 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
906 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
909 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
915 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
923 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
929 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
937 XGMAC_IOREAD(pdata, DMA_MR));
939 XGMAC_IOREAD(pdata, DMA_SBMR));
941 XGMAC_IOREAD(pdata, DMA_ISR));
943 XGMAC_IOREAD(pdata, DMA_AXIARCR));
945 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
947 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
949 XGMAC_IOREAD(pdata, DMA_DSR0));
951 XGMAC_IOREAD(pdata, DMA_DSR1));
953 XGMAC_IOREAD(pdata, DMA_DSR2));
955 XGMAC_IOREAD(pdata, DMA_DSR3));
957 XGMAC_IOREAD(pdata, DMA_DSR4));
959 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
961 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
970 channel = pdata->channel[i];
1032 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
1039 XGMAC_IOREAD(pdata, MTL_OMR));
1041 XGMAC_IOREAD(pdata, MTL_FDCR));
1043 XGMAC_IOREAD(pdata, MTL_FDSR));
1045 XGMAC_IOREAD(pdata, MTL_FDDR));
1047 XGMAC_IOREAD(pdata, MTL_ISR));
1049 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1051 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1053 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1055 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1057 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1064 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1066 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1068 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1070 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1072 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1074 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1077 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1079 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1081 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1083 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1085 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1087 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1089 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1094 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1099 XGMAC_IOREAD(pdata, MAC_TCR));
1101 XGMAC_IOREAD(pdata, MAC_RCR));
1103 XGMAC_IOREAD(pdata, MAC_PFR));
1105 XGMAC_IOREAD(pdata, MAC_WTR));
1107 XGMAC_IOREAD(pdata, MAC_HTR0));
1109 XGMAC_IOREAD(pdata, MAC_HTR1));
1111 XGMAC_IOREAD(pdata, MAC_HTR2));
1113 XGMAC_IOREAD(pdata, MAC_HTR3));
1115 XGMAC_IOREAD(pdata, MAC_HTR4));
1117 XGMAC_IOREAD(pdata, MAC_HTR5));
1119 XGMAC_IOREAD(pdata, MAC_HTR6));
1121 XGMAC_IOREAD(pdata, MAC_HTR7));
1123 XGMAC_IOREAD(pdata, MAC_VLANTR));
1125 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1127 XGMAC_IOREAD(pdata, MAC_VLANIR));
1129 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1131 XGMAC_IOREAD(pdata, MAC_RETMR));
1133 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1135 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1137 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1139 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1141 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1143 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1145 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1147 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1149 XGMAC_IOREAD(pdata, MAC_RFCR));
1151 XGMAC_IOREAD(pdata, MAC_RQC0R));
1153 XGMAC_IOREAD(pdata, MAC_RQC1R));
1155 XGMAC_IOREAD(pdata, MAC_RQC2R));
1157 XGMAC_IOREAD(pdata, MAC_RQC3R));
1159 XGMAC_IOREAD(pdata, MAC_ISR));
1161 XGMAC_IOREAD(pdata, MAC_IER));
1163 XGMAC_IOREAD(pdata, MAC_RTSR));
1165 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1167 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1169 XGMAC_IOREAD(pdata, MAC_LPICSR));
1171 XGMAC_IOREAD(pdata, MAC_LPITCR));
1173 XGMAC_IOREAD(pdata, MAC_TIR));
1175 XGMAC_IOREAD(pdata, MAC_VR));
1177 XGMAC_IOREAD(pdata, MAC_DR));
1179 XGMAC_IOREAD(pdata, MAC_HWF0R));
1181 XGMAC_IOREAD(pdata, MAC_HWF1R));
1183 XGMAC_IOREAD(pdata, MAC_HWF2R));
1185 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1187 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1189 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1191 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1193 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1195 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1197 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1199 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1201 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1203 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1205 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1207 XGMAC_IOREAD(pdata, MAC_RSSCR));
1209 XGMAC_IOREAD(pdata, MAC_RSSDR));
1211 XGMAC_IOREAD(pdata, MAC_RSSAR));
1213 XGMAC_IOREAD(pdata, MAC_TSCR));
1215 XGMAC_IOREAD(pdata, MAC_SSIR));
1217 XGMAC_IOREAD(pdata, MAC_STSR));
1219 XGMAC_IOREAD(pdata, MAC_STNR));
1221 XGMAC_IOREAD(pdata, MAC_STSUR));
1223 XGMAC_IOREAD(pdata, MAC_STNUR));
1225 XGMAC_IOREAD(pdata, MAC_TSAR));
1227 XGMAC_IOREAD(pdata, MAC_TSSR));
1229 XGMAC_IOREAD(pdata, MAC_TXSNR));
1231 XGMAC_IOREAD(pdata, MAC_TXSSR));
1235 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1237 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1241 pdata->hw_if.read_mmc_stats(pdata);
1328 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1332 XI2C_IOREAD(pdata, 0x00));
1334 XI2C_IOREAD(pdata, 0x04));
1336 XI2C_IOREAD(pdata, 0x0c));
1338 XI2C_IOREAD(pdata, 0x2c));
1340 XI2C_IOREAD(pdata, 0x30));
1342 XI2C_IOREAD(pdata, 0x34));
1344 XI2C_IOREAD(pdata, 0x38));
1346 XI2C_IOREAD(pdata, 0x3c));
1348 XI2C_IOREAD(pdata, 0x6c));
1350 XI2C_IOREAD(pdata, 0x70));
1352 XI2C_IOREAD(pdata, 0x74));
1354 XI2C_IOREAD(pdata, 0x78));
1356 XI2C_IOREAD(pdata, 0x9c));
1358 XI2C_IOREAD(pdata, 0xf4));
1362 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1369 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1375 xgbe_default_config(struct xgbe_prv_data *pdata)
1377 pdata->blen = DMA_SBMR_BLEN_64;
1378 pdata->pbl = DMA_PBL_128;
1379 pdata->aal = 1;
1380 pdata->rd_osr_limit = 8;
1381 pdata->wr_osr_limit = 8;
1382 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1383 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1384 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1385 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1386 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1387 pdata->pause_autoneg = 1;
1388 pdata->phy_speed = SPEED_UNKNOWN;
1389 pdata->power_down = 0;
1390 pdata->enable_rss = 1;
1397 struct xgbe_prv_data *pdata = &sc->pdata;
1398 if_t ifp = pdata->netdev;
1399 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1400 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1405 pdata->sph_enable = axgbe_sph_enable;
1408 pdata->tx_sec_period = ticks;
1409 pdata->tx_ded_period = ticks;
1410 pdata->rx_sec_period = ticks;
1411 pdata->rx_ded_period = ticks;
1412 pdata->desc_sec_period = ticks;
1413 pdata->desc_ded_period = ticks;
1416 ret = hw_if->exit(&sc->pdata);
1420 axgbe_sysctl_init(pdata);
1423 xgbe_default_config(pdata);
1426 if (!pdata->tx_max_fifo_size)
1427 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1428 if (!pdata->rx_max_fifo_size)
1429 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1432 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1436 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1438 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1441 if (pdata->channel_irq_count) {
1442 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1443 pdata->channel_irq_count);
1444 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1445 pdata->channel_irq_count);
1448 pdata->tx_ring_count, pdata->tx_q_count,
1449 pdata->rx_ring_count, pdata->rx_q_count);
1453 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1455 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1457 axgbe_initialize_rss_mapping(pdata);
1460 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1461 phy_if->phy_init(pdata);
1464 xgbe_init_rx_coalesce(&sc->pdata);
1465 xgbe_init_tx_coalesce(&sc->pdata);
1482 pdata->phy_link = -1;
1483 pdata->phy_speed = SPEED_UNKNOWN;
1484 ret = phy_if->phy_reset(pdata);
1489 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1490 pdata->rx_buf_size = ret;
1498 set_bit(XGBE_DOWN, &pdata->dev_state);
1504 axgbe_pci_init(pdata);
1510 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1514 bus_teardown_intr(pdata->dev, res, tag);
1517 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1524 struct xgbe_prv_data *pdata = &sc->pdata;
1533 iflib_irq_free(ctx, &pdata->dev_irq);
1536 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1537 pdata->ecc_rid);
1540 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1541 pdata->i2c_rid);
1544 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1545 pdata->an_rid);
1549 channel = pdata->channel[i];
1561 struct xgbe_prv_data *pdata = &sc->pdata;
1562 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1565 mac_res[0] = pdata->xgmac_res;
1566 mac_res[1] = pdata->xpcs_res;
1568 phy_if->phy_stop(pdata);
1569 phy_if->phy_exit(pdata);
1575 taskqueue_free(pdata->dev_workqueue);
1581 free(pdata->active_vlans, M_AXGBE);
1583 axgbe_sysctl_exit(pdata);
1589 axgbe_pci_init(struct xgbe_prv_data *pdata)
1591 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1592 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1595 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1600 hw_if->init(pdata);
1602 ret = phy_if->phy_start(pdata);
1605 ret = hw_if->exit(pdata);
1611 hw_if->enable_tx(pdata);
1612 hw_if->enable_rx(pdata);
1614 xgbe_start_timers(pdata);
1616 clear_bit(XGBE_DOWN, &pdata->dev_state);
1618 xgbe_dump_phy_registers(pdata);
1619 xgbe_dump_prop_registers(pdata);
1620 xgbe_dump_dma_registers(pdata, -1);
1621 xgbe_dump_mtl_registers(pdata);
1622 xgbe_dump_mac_registers(pdata);
1623 xgbe_dump_rmon_counters(pdata);
1630 struct xgbe_prv_data *pdata = &sc->pdata;
1632 axgbe_pci_init(pdata);
1639 struct xgbe_prv_data *pdata = &sc->pdata;
1640 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1643 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1648 xgbe_stop_timers(pdata);
1649 taskqueue_drain_all(pdata->dev_workqueue);
1651 hw_if->disable_tx(pdata);
1652 hw_if->disable_rx(pdata);
1654 ret = hw_if->exit(pdata);
1658 set_bit(XGBE_DOWN, &pdata->dev_state);
1684 struct xgbe_prv_data *pdata = &sc->pdata;
1699 channel = pdata->channel[i];
1732 channel = pdata->channel[j];
1753 struct xgbe_prv_data *pdata = &sc->pdata;
1761 if (!pdata->sph_enable) {
1772 channel = pdata->channel[i];
1805 channel = pdata->channel[j];
1825 struct xgbe_prv_data *pdata = &sc->pdata;
1835 channel = pdata->channel[i];
1848 channel = pdata->channel[i];
1866 struct xgbe_prv_data *pdata = &sc->pdata;
1867 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1869 if (!bit_test(pdata->active_vlans, vtag)) {
1872 bit_set(pdata->active_vlans, vtag);
1873 hw_if->update_vlan_hash_table(pdata);
1874 pdata->num_active_vlans++;
1877 pdata->num_active_vlans);
1881 xgbe_dump_active_vlans(pdata);
1888 struct xgbe_prv_data *pdata = &sc->pdata;
1889 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1891 if (pdata->num_active_vlans == 0) {
1896 if (bit_test(pdata->active_vlans, vtag)){
1899 bit_clear(pdata->active_vlans, vtag);
1900 hw_if->update_vlan_hash_table(pdata);
1901 pdata->num_active_vlans--;
1904 pdata->num_active_vlans);
1908 xgbe_dump_active_vlans(pdata);
1927 struct xgbe_prv_data *pdata = &sc->pdata;
1936 pdata->isr_as_tasklet = 1;
1939 pdata->irq_count = 1;
1940 pdata->channel_irq_count = 1;
1951 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1961 pdata->ecc_rid = rid;
1962 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1964 if (!pdata->ecc_irq_res) {
1970 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1971 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1980 pdata->i2c_rid = rid;
1981 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1983 if (!pdata->i2c_irq_res) {
1989 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1990 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1999 pdata->an_rid = rid;
2000 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2002 if (!pdata->an_irq_res) {
2008 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2009 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2016 pdata->per_channel_irq = 1;
2017 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2021 channel = pdata->channel[i];
2039 pdata->irq_count = msix;
2040 pdata->channel_irq_count = scctx->isc_nrxqsets;
2044 channel = pdata->channel[i];
2056 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2058 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2076 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2078 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2096 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2100 for (i = 0; i < pdata->channel_count; i++)
2101 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2108 struct xgbe_prv_data *pdata = channel->pdata;
2116 XGMAC_IOREAD(pdata, DMA_ISR),
2117 XGMAC_IOREAD(pdata, MAC_ISR));
2122 xgbe_disable_rx_tx_int(pdata, channel);
2137 struct xgbe_prv_data *pdata = &sc->pdata;
2139 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2144 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2150 for (i = 0; i < pdata->channel_count; i++) {
2155 channel = pdata->channel[i];
2167 if (!pdata->per_channel_irq &&
2172 xgbe_disable_rx_tx_ints(pdata);
2185 pdata->ext_stats.rx_buffer_unavailable++;
2200 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2204 hw_if->tx_mmc_int(pdata);
2207 hw_if->rx_mmc_int(pdata);
2210 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2214 wakeup_one(pdata);
2227 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2241 sc->pdata.phy_if.an_isr(&sc->pdata);
2248 struct xgbe_prv_data *pdata = &sc->pdata;
2251 if (qid < pdata->tx_q_count) {
2252 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2267 struct xgbe_prv_data *pdata = &sc->pdata;
2270 if (qid < pdata->rx_q_count) {
2271 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2286 struct xgbe_prv_data *pdata = &sc->pdata;
2289 pdata->phy_link, sc->link_status, pdata->phy.speed);
2291 if (pdata->phy_link < 0)
2294 if (pdata->phy_link) {
2297 if (pdata->phy.speed & SPEED_10000)
2300 else if (pdata->phy.speed & SPEED_2500)
2303 else if (pdata->phy.speed & SPEED_1000)
2306 else if (pdata->phy.speed & SPEED_100)
2309 else if (pdata->phy.speed & SPEED_10)
2327 sx_xlock(&sc->pdata.an_mutex);
2333 sc->pdata.phy.speed = SPEED_10000;
2334 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2337 sc->pdata.phy.speed = SPEED_2500;
2338 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2341 sc->pdata.phy.speed = SPEED_1000;
2342 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2345 sc->pdata.phy.speed = SPEED_100;
2346 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2349 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2352 sx_xunlock(&sc->pdata.an_mutex);
2354 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2361 struct xgbe_prv_data *pdata = &sc->pdata;
2362 if_t ifp = pdata->netdev;
2365 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp),
2372 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2378 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2380 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2385 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2391 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2393 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2404 struct xgbe_prv_data *pdata = &sc->pdata;
2405 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2407 pdata->hw_if.read_mmc_stats(pdata);
2432 struct xgbe_prv_data *pdata = &sc->pdata;
2438 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2439 pdata->rx_buf_size = ret;
2450 struct xgbe_prv_data *pdata = &sc->pdata;
2453 if (!sc->pdata.phy.link)
2459 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2460 pdata->phy_if.phy_impl.cur_mode(pdata));
2461 pdata->phy_if.phy_impl.get_type(pdata, ifmr);