Lines Matching defs:channel
528 DBGPR("max tx/rx channel count = %u/%u\n",
554 axgbe_error("Unable to allocate channel memory\n");
653 DBGPR("TX/RX max channel count = %u/%u\n",
768 struct xgbe_channel *channel;
777 /* Allocate channel memory */
779 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
782 if (channel == NULL) {
784 free(pdata->channel[j], M_AXGBE);
785 pdata->channel[j] = NULL;
790 pdata->channel[i] = channel;
798 channel = pdata->channel[i];
799 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
801 channel->pdata = pdata;
802 channel->queue_index = i;
803 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
804 bus_space_subregion(channel->dma_tag,
807 &channel->dma_handle);
808 channel->tx_ring = NULL;
809 channel->rx_ring = NULL;
822 free(pdata->channel[i], M_AXGBE);
823 pdata->channel[i] = NULL;
931 struct xgbe_channel *channel;
970 channel = pdata->channel[i];
975 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
977 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
979 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
981 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
983 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
985 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
987 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
989 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
991 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
993 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
995 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
997 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
999 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
1001 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
1003 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
1005 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
1007 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
1009 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
1011 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
1013 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
1015 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
1017 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
1019 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
1021 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
1023 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
1025 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
1027 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
1452 /* Set channel count based on interrupts assigned */
1526 struct xgbe_channel *channel;
1549 channel = pdata->channel[i];
1550 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1551 irq.ii_res = channel->dma_irq_res;
1552 irq.ii_tag = channel->dma_irq_tag;
1686 struct xgbe_channel *channel;
1699 channel = pdata->channel[i];
1709 channel->tx_ring = tx_ring;
1732 channel = pdata->channel[j];
1734 tx_ring = channel->tx_ring;
1739 free(channel->tx_ring, M_AXGBE);
1741 channel->tx_ring = NULL;
1755 struct xgbe_channel *channel;
1772 channel = pdata->channel[i];
1782 channel->rx_ring = rx_ring;
1805 channel = pdata->channel[j];
1807 rx_ring = channel->rx_ring;
1812 free(channel->rx_ring, M_AXGBE);
1814 channel->rx_ring = NULL;
1828 struct xgbe_channel *channel;
1835 channel = pdata->channel[i];
1837 tx_ring = channel->tx_ring;
1842 free(channel->tx_ring, M_AXGBE);
1843 channel->tx_ring = NULL;
1848 channel = pdata->channel[i];
1850 rx_ring = channel->rx_ring;
1855 free(channel->rx_ring, M_AXGBE);
1856 channel->rx_ring = NULL;
1929 struct xgbe_channel *channel;
2021 channel = pdata->channel[i];
2025 axgbe_msix_que, channel, channel->queue_index, buf);
2033 channel->dma_irq_rid = rid;
2034 channel->dma_irq_res = irq.ii_res;
2035 channel->dma_irq_tag = irq.ii_tag;
2036 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2044 channel = pdata->channel[i];
2047 irq.ii_res = channel->dma_irq_res;
2048 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2049 channel->queue_index, buf);
2056 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2061 if (channel->tx_ring && channel->rx_ring)
2063 else if (channel->tx_ring)
2065 else if (channel->rx_ring)
2070 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2071 __func__, channel->queue_index, int_id);
2072 return (hw_if->enable_int(channel, int_id));
2076 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2081 if (channel->tx_ring && channel->rx_ring)
2083 else if (channel->tx_ring)
2085 else if (channel->rx_ring)
2090 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2091 __func__, channel->queue_index, int_id);
2092 hw_if->disable_int(channel, int_id);
2101 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2107 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2108 struct xgbe_prv_data *pdata = channel->pdata;
2112 __func__, channel->queue_index,
2113 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2114 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2115 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2119 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2121 /* Disable Tx and Rx channel interrupts */
2122 xgbe_disable_rx_tx_int(pdata, channel);
2128 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2138 struct xgbe_channel *channel;
2155 channel = pdata->channel[i];
2157 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2158 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2159 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2164 * per channel DMA interrupts. Check to be sure those are not
2176 * Don't clear Rx/Tx status if doing per channel DMA
2178 * per channel DMA interrupts
2193 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2252 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2258 axgbe_error("Queue ID exceed channel count\n");
2271 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2277 axgbe_error("Queue ID exceed channel count\n");