Lines Matching +full:edma +full:- +full:tx
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
52 * There is a separate TX ath_buf pool for management frames.
55 * TX activity.
60 * 802.11n requires more TX and RX buffers to do AMPDU.
72 #define ATH_TXBUF 200 /* number of TX buffers */
79 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
86 * The following bits can be set during the PCI (and perhaps non-PCI
106 * tracking station state such as the current tx antenna.
108 * and station state to short-circuit node lookups on rx.
122 * Per-TID state
124 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
148 * These are flags - perhaps later collapse
151 int addba_tx_pending; /* TX ADDBA pending */
158 * from aggregation to non-aggregation?
162 * TXed/completed; at which point (non-aggregation)
167 * How many hardware-queued packets are
182 /* active tx buffers, beginning at current BAW */
190 /* driver-specific node state */
199 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */
207 /* variable-length rate control state follows */
217 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
219 if ((y) >= -20) \
223 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
239 struct ath_desc_status bf_status; /* tx/rx status */
245 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */
247 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
251 /* Completion function to call on TX complete (fail or not) */
267 uint8_t bfs_tx_queue; /* destination hardware TX queue */
276 bfs_ismrr:1, /* do multi-rate TX retry */
278 bfs_doratelookup:1; /* do rate lookup before each TX */
293 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */
294 uint8_t bfs_txrate0; /* first TX rate */
297 uint16_t bfs_txpower; /* tx power */
298 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */
303 int32_t bfs_txantenna; /* TX antenna config */
309 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */
310 int32_t bfs_rc_maxpktlen; /* max packet length/bucket from ratectrl or -1 */
311 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */
316 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */
317 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */
325 * DMA state for tx/rx descriptors.
359 u_int32_t *axq_link; /* link ptr in last TX desc */
364 * This is the FIFO staging buffer when doing EDMA.
369 * For EDMA, the staging buffer is treated as normal;
377 u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */
388 * TX path lock.
390 struct ath_buf *axq_holdingbf; /* holding TX buffer */
393 /* Per-TID traffic queue for software -> hardware TX */
395 * This is protected by the general TX path lock, not (for now)
402 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
403 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
404 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
406 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
407 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
408 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
409 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
410 #define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \
413 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx)
414 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx)
415 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED)
416 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \
423 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
424 (_tq)->axq_depth++; \
427 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
428 (_tq)->axq_depth++; \
431 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
432 (_tq)->axq_depth--; \
434 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q)
435 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field)
441 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
442 (_tq)->axq_depth++; \
443 (_tq)->an->an_swq_depth++; \
446 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
447 (_tq)->axq_depth++; \
448 (_tq)->an->an_swq_depth++; \
451 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
452 (_tq)->axq_depth--; \
453 (_tq)->an->an_swq_depth--; \
455 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q)
456 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field)
462 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
463 (_tq)->axq_depth++; \
464 (_tq)->an->an_swq_depth++; \
467 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
468 (_tq)->axq_depth++; \
469 (_tq)->an->an_swq_depth++; \
472 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
473 (_tq)->axq_depth--; \
474 (_tq)->an->an_swq_depth--; \
476 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q)
477 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
503 * Whether to reset the TX/RX queue with or without
581 * This is (currently) protected by the TX queue lock;
590 int sc_tx_nmaps; /* Number of TX maps */
592 int sc_rx_stopped; /* XXX only for EDMA */
593 int sc_rx_resetted; /* XXX only for EDMA */
606 struct mtx sc_tx_mtx; /* TX handling/comp mutex */
608 struct mtx sc_tx_ic_mtx; /* TX queue mutex */
612 struct ath_ratectrl *sc_rc; /* tx rate control support */
620 sc_mrretry : 1,/* multi-rate retry support */
627 sc_hasveol : 1,/* tx VEOL support */
648 sc_rxslink : 1,/* do self-linked final descriptor */
650 sc_isedma : 1,/* supports EDMA */
680 u_int16_t sc_curtxpow; /* current tx power limit */
688 u_int8_t txflags; /* radiotap tx flags */
697 u_int sc_txantenna; /* tx antenna (fixed or auto) */
712 uint32_t sc_txproc_cnt; /* In TX processing */
713 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */
715 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */
728 u_int8_t sc_txrix; /* current tx rate for LED */
746 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
753 struct ath_descdma sc_txdma; /* TX descriptors */
757 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */
759 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */
763 u_int sc_txintrperiod;/* tx interrupt batching */
765 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
766 struct task sc_txtask; /* tx int processing */
767 struct task sc_txqtask; /* tx proc processing */
769 struct ath_descdma sc_txcompdma; /* TX EDMA completion */
770 struct mtx sc_txcomplock; /* TX EDMA completion lock */
774 struct callout sc_wd_ch; /* tx watchdog timer */
783 /* recent tx frames/antenna */
784 struct ath_txq *sc_cabq; /* tx q for cab frames */
805 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
813 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
815 uint32_t sc_txchainmask; /* hardware TX chainmask */
817 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */
819 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */
820 int sc_aggr_limit; /* TX limit on all aggregates */
853 * when to begin limiting non-aggregate frames to the
856 * when to begin limiting A-MPDU frames to the
858 * tid_hwq_lo: how low the per-TID hwq count has to be before the
886 /* TX AMPDU handling */
904 * target selfgen state is the self-generated frames
934 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
936 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
937 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
938 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
939 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
940 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
943 * The TX lock is non-reentrant and serialises the TX frame send
947 snprintf((_sc)->sc_tx_mtx_name, \
948 sizeof((_sc)->sc_tx_mtx_name), \
949 "%s TX lock", \
950 device_get_nameunit((_sc)->sc_dev)); \
951 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \
954 #define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx)
955 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx)
956 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx)
957 #define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
959 #define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
961 #define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \
962 mtx_trylock(&(_sc)->sc_tx_mtx))
965 * The PCU lock is non-recursive and should be treated as a spinlock.
972 * as TX, RX, state change (eg channel change), channel reset and updates
975 * Although the current single-thread taskqueue mechanism protects the
977 * a few others which occur at the same time. These include the TX path
982 snprintf((_sc)->sc_pcu_mtx_name, \
983 sizeof((_sc)->sc_pcu_mtx_name), \
985 device_get_nameunit((_sc)->sc_dev)); \
986 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \
989 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx)
990 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx)
991 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx)
992 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
994 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
1004 snprintf((_sc)->sc_rx_mtx_name, \
1005 sizeof((_sc)->sc_rx_mtx_name), \
1007 device_get_nameunit((_sc)->sc_dev)); \
1008 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \
1011 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx)
1012 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx)
1013 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx)
1014 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1016 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1019 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
1022 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
1023 device_get_nameunit((_sc)->sc_dev)); \
1024 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
1026 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
1027 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
1028 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
1030 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
1032 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED)
1035 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \
1037 device_get_nameunit((_sc)->sc_dev)); \
1038 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \
1041 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock)
1042 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock)
1043 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock)
1045 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED)
1058 ((*(_ah)->ah_detach)((_ah)))
1060 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \
1063 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
1065 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
1067 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
1069 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
1071 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
1073 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
1075 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
1077 ((*(_ah)->ah_getInterrupts)((_ah)))
1079 ((*(_ah)->ah_isInterruptPending)((_ah)))
1081 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
1083 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
1085 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1087 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE))
1089 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
1091 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1093 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1095 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1097 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1099 ((*(_ah)->ah_getRxFilter)((_ah)))
1101 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1103 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1105 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
1107 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
1113 ((*(_ah)->ah_getTsf64)((_ah)))
1115 ((*(_ah)->ah_setTsf64)((_ah), (_val)))
1117 ((*(_ah)->ah_resetTsf)((_ah)))
1119 ((*(_ah)->ah_enableReceive)((_ah)))
1121 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1123 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
1125 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
1127 ((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
1129 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
1131 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
1133 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
1135 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1137 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
1139 ((*(_ah)->ah_setLedState)((_ah), (_state)))
1141 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1143 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
1145 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
1147 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
1149 ((*(_ah)->ah_getNextTBTT)((_ah)))
1151 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1153 ((*(_ah)->ah_phyDisable)((_ah)))
1155 ((*(_ah)->ah_setPCUConfig)((_ah)))
1157 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1159 ((*(_ah)->ah_stopPcuReceive)((_ah)))
1161 ((*(_ah)->ah_startPcuReceive)((_ah), (_is_scanning)))
1163 ((*(_ah)->ah_stopDmaReceive)((_ah)))
1165 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
1170 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1172 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1174 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1176 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1178 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
1184 ((*(_ah)->ah_getRfGain)((_ah)))
1186 ((*(_ah)->ah_getDefAntenna)((_ah)))
1188 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1190 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
1192 ((*(_ah)->ah_aniPoll)((_ah), (_chan)))
1194 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1196 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1198 ((*(_ah)->ah_getSlotTime)((_ah)))
1200 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1202 ((*(_ah)->ah_getAckTimeout)((_ah)))
1204 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1206 ((*(_ah)->ah_getCTSTimeout)((_ah)))
1208 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1210 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1218 (*(_pcc) = (_ah)->ah_countryCode)
1240 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
1242 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
1254 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1336 /* EDMA definitions */
1360 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
1386 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
1388 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
1392 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1397 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1400 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1403 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
1405 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
1407 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1409 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1411 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1413 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1415 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1418 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1422 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1426 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1430 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1433 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1437 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1439 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1441 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1444 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1446 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1448 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
1451 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1453 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1455 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1457 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
1463 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1465 ((*(_ah)->ah_disablePCIE)((_ah)))
1468 * This is badly-named; you need to set the correct parameters
1474 ((*(_ah)->ah_enableDfs)((_ah), (_param)))
1476 ((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1478 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1480 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1483 ((*(_ah)->ah_isFastClockEnabled)((_ah)))
1485 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
1487 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1489 ((*(_ah)->ah_get11nExtBusy)((_ah)))
1491 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1493 ((*(_ah)->ah_setQuiet)((_ah), (_p), (_d), (_o), (_f)))
1495 ((*(_ah)->ah_getNav)((_ah)))
1497 ((*(_ah)->ah_setNav)((_ah), (_val)))
1502 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1504 ((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1506 ((*(_ah)->ah_spectralStart)((_ah)))
1508 ((*(_ah)->ah_spectralStop)((_ah)))
1513 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1515 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1517 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1519 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1521 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1523 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1525 ((*(_ah)->ah_btCoexEnable)((_ah)))
1527 ((*(_ah)->ah_btCoexDisable)((_ah)))
1530 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp)))
1532 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt)))
1534 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm)))
1536 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd)))
1538 ((*(_ah)->ah_btMciDetach)((_ah)))
1541 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1543 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))