Lines Matching defs:ath_softc
560 struct ath_softc { struct
561 struct ieee80211com sc_ic;
562 struct ath_stats sc_stats; /* device statistics */
563 struct ath_tx_aggr_stats sc_aggr_stats;
564 struct ath_intr_stats sc_intr_stats;
565 uint64_t sc_debug;
566 uint64_t sc_ktrdebug;
567 int sc_nvaps; /* # vaps */
568 int sc_nstavaps; /* # station vaps */
569 int sc_nmeshvaps; /* # mbss vaps */
570 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
571 u_int8_t sc_nbssid0; /* # vap's using base mac */
572 uint32_t sc_bssidmask; /* bssid mask */
574 struct ath_rx_methods sc_rx;
575 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */
576 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */
577 struct ath_tx_methods sc_tx;
578 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES];
585 ath_bufhead sc_txbuf_list;
587 int sc_rx_statuslen;
588 int sc_tx_desclen;
589 int sc_tx_statuslen;
590 int sc_tx_nmaps; /* Number of TX maps */
614 void (*sc_setdefantenna)(struct ath_softc *, u_int); argument
619 uint32_t sc_invalid : 1,/* disable hardware accesses */
620 sc_mrretry : 1,/* multi-rate retry support */
621 sc_mrrprot : 1,/* MRR + protection support */
622 sc_softled : 1,/* enable LED gpio status */
623 sc_hardled : 1,/* enable MAC LED status */
624 sc_splitmic : 1,/* split TKIP MIC keys */
625 sc_needmib : 1,/* enable MIB stats intr */
626 sc_diversity: 1,/* enable rx diversity */
627 sc_hasveol : 1,/* tx VEOL support */
628 sc_ledstate : 1,/* LED on/off state */
629 sc_blinking : 1,/* LED blink operation active */
630 sc_mcastkey : 1,/* mcast key cache search */
631 sc_scanning : 1,/* scanning active */
632 sc_syncbeacon:1,/* sync/resync beacon timers */
633 sc_hasclrkey: 1,/* CLR key supported */
634 sc_xchanmode: 1,/* extended channel mode */
635 sc_outdoor : 1,/* outdoor operation */
636 sc_dturbo : 1,/* dynamic turbo in use */
637 sc_hasbmask : 1,/* bssid mask support */
638 sc_hasbmatch: 1,/* bssid match disable support*/
639 sc_hastsfadd: 1,/* tsf adjust support */
640 sc_beacons : 1,/* beacons running */
641 sc_swbmiss : 1,/* sta mode using sw bmiss */
642 sc_stagbeacons:1,/* use staggered beacons */
643 sc_wmetkipmic:1,/* can do WME+TKIP MIC */
644 sc_resume_up: 1,/* on resume, start all vaps */
645 sc_tdma : 1,/* TDMA in use */
646 sc_setcca : 1,/* set/clr CCA with TDMA */
647 sc_resetcal : 1,/* reset cal state next trip */
648 sc_rxslink : 1,/* do self-linked final descriptor */
649 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */
650 sc_isedma : 1,/* supports EDMA */
651 sc_do_mybeacon : 1; /* supports mybeacon */
656 u_int32_t sc_running : 1, /* initialized */
657 sc_use_ent : 1,
658 sc_rx_stbc : 1,
659 sc_tx_stbc : 1,
660 sc_has_ldpc : 1,
661 sc_hasenforcetxop : 1, /* support enforce TxOP */
662 sc_hasdivcomb : 1, /* RX diversity combining */
663 sc_rx_lnamixer : 1, /* RX using LNA mixing */
664 sc_btcoex_mci : 1; /* MCI bluetooth coex */
666 int sc_cabq_enable; /* Enable cabq transmission */
671 uint32_t sc_ent_cfg;
673 uint32_t sc_eerd; /* regdomain from EEPROM */
674 uint32_t sc_eecc; /* country code from EEPROM */
676 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
677 const HAL_RATE_TABLE *sc_currates; /* current rate table */
678 enum ieee80211_phymode sc_curmode; /* current phy mode */
679 HAL_OPMODE sc_opmode; /* current operating mode */
680 u_int16_t sc_curtxpow; /* current tx power limit */
681 u_int16_t sc_curaid; /* current association id */
682 struct ieee80211_channel *sc_curchan; /* current installed channel */
683 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
684 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
685 struct {
691 } sc_hwmap[32]; /* h/w rate ix mappings */
692 u_int8_t sc_protrix; /* protection rate index */
693 u_int8_t sc_lastdatarix; /* last data frame rate index */
694 u_int sc_mcastrate; /* ieee rate for mcastrateix */
695 u_int sc_fftxqmin; /* min frames before staging */
696 u_int sc_fftxqmax; /* max frames before drop */
697 u_int sc_txantenna; /* tx antenna (fixed or auto) */
699 HAL_INT sc_imask; /* interrupt mask copy */
709 uint32_t sc_txq_active; /* bitmap of active TXQs */
710 uint32_t sc_kickpcu; /* whether to kick the PCU */
711 uint32_t sc_rxproc_cnt; /* In RX processing */
712 uint32_t sc_txproc_cnt; /* In TX processing */
713 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */
714 uint32_t sc_inreset_cnt; /* In active reset/chanchange */
715 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */
716 uint32_t sc_intr_cnt; /* refcount on interrupt handling */
718 u_int sc_keymax; /* size of key cache */
719 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
724 u_int sc_ledpin; /* GPIO pin for driving LED */
725 u_int sc_ledon; /* pin setting for LED on */
726 u_int sc_ledidle; /* idle polling interval */
727 int sc_ledevent; /* time of last LED event */
728 u_int8_t sc_txrix; /* current tx rate for LED */
729 u_int16_t sc_ledoff; /* off time for current blink */
730 struct callout sc_ledtimer; /* led off timer */
735 int sc_led_pwr_pin; /* MAC power LED GPIO pin */
736 int sc_led_net_pin; /* MAC network LED GPIO pin */
738 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
739 u_int sc_rfsilentpol; /* pin setting for rfkill on */
741 struct ath_descdma sc_rxdma; /* RX descriptors */
742 ath_bufhead sc_rxbuf; /* receive buffer */
743 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
744 struct task sc_rxtask; /* rx int processing */
745 u_int8_t sc_defant; /* current default antenna */
746 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
747 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
748 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */
749 struct ath_rx_radiotap_header sc_rx_th;
750 int sc_rx_th_len;
751 u_int sc_monpass; /* frames to pass in mon.mode */
753 struct ath_descdma sc_txdma; /* TX descriptors */
754 uint16_t sc_txbuf_descid;
755 ath_bufhead sc_txbuf; /* transmit buffer */
756 int sc_txbuf_cnt; /* how many buffers avail */
757 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */
758 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */
759 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */
760 struct mtx sc_txbuflock; /* txbuf lock */
761 char sc_txname[12]; /* e.g. "ath0_buf" */
762 u_int sc_txqsetup; /* h/w queues setup */
763 u_int sc_txintrperiod;/* tx interrupt batching */
764 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
765 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
766 struct task sc_txtask; /* tx int processing */
767 struct task sc_txqtask; /* tx proc processing */
769 struct ath_descdma sc_txcompdma; /* TX EDMA completion */
770 struct mtx sc_txcomplock; /* TX EDMA completion lock */
771 char sc_txcompname[12]; /* eg ath0_txcomp */
773 int sc_wd_timer; /* count down for wd timer */
774 struct callout sc_wd_ch; /* tx watchdog timer */
775 struct ath_tx_radiotap_header sc_tx_th;
776 int sc_tx_th_len;
778 struct ath_descdma sc_bdma; /* beacon descriptors */
779 ath_bufhead sc_bbuf; /* beacon buffers */
780 u_int sc_bhalq; /* HAL q for outgoing beacons */
781 u_int sc_bmisscount; /* missed beacon transmits */
782 u_int32_t sc_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA];
784 struct ath_txq *sc_cabq; /* tx q for cab frames */
785 struct task sc_bmisstask; /* bmiss int processing */
786 struct task sc_tsfoortask; /* TSFOOR int processing */
787 struct task sc_bstucktask; /* stuck beacon processing */
788 struct task sc_resettask; /* interface reset task */
789 struct task sc_fataltask; /* fatal task */
790 enum {
794 } sc_updateslot; /* slot time update fsm */
795 int sc_slotupdate; /* slot to advance fsm */
796 struct ieee80211vap *sc_bslot[ATH_BCBUF];
797 int sc_nbcnvaps; /* # vaps with beacons */
799 struct callout sc_cal_ch; /* callout handle for cals */
800 int sc_lastlongcal; /* last long cal completed */
801 int sc_lastcalreset;/* last cal reset done */
802 int sc_lastani; /* last ANI poll */
803 int sc_lastshortcal; /* last short calibration */
804 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */
805 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
806 u_int sc_tdmadbaprep; /* TDMA DBA prep time */
807 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */
808 u_int sc_tdmaswba; /* TDMA SWBA counter */
809 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */
810 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */
811 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */
812 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
813 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
814 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
815 uint32_t sc_txchainmask; /* hardware TX chainmask */
816 uint32_t sc_rxchainmask; /* hardware RX chainmask */
817 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */
818 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */
819 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */
820 int sc_aggr_limit; /* TX limit on all aggregates */
821 int sc_delim_min_pad; /* Minimum delimiter count */
844 int sc_txq_node_maxdepth;
845 int sc_txq_data_minfree;
846 int sc_txq_mcastq_maxdepth;
847 int sc_txq_node_psq_maxdepth;
863 int sc_hwq_limit_nonaggr;
864 int sc_hwq_limit_aggr;
865 int sc_tid_hwq_lo;
866 int sc_tid_hwq_hi;
869 void *sc_dfs; /* Used by an optional DFS module */
870 int sc_dodfs; /* Whether to enable DFS rx filter bits */
871 struct task sc_dfstask; /* DFS processing task */
874 void *sc_spectral;
875 int sc_dospectral;
878 void *sc_lna_div;
879 int sc_dolnadiv;
883 struct if_ath_alq sc_alq;
887 int (*sc_addba_request)(struct ieee80211_node *,
889 int (*sc_addba_response)(struct ieee80211_node *,
891 void (*sc_addba_stop)(struct ieee80211_node *,
893 void (*sc_addba_response_timeout)
896 void (*sc_bar_response)(struct ieee80211_node *ni,
909 HAL_POWER_MODE sc_target_powerstate;
910 HAL_POWER_MODE sc_target_selfgen_state;
912 HAL_POWER_MODE sc_cur_powerstate;
914 int sc_powersave_refcnt;
917 uint32_t sc_pci_devinfo;
920 struct {
930 } sc_btcoex;