Lines Matching +full:rx +full:- +full:tx
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
63 u_int32_t ast_rxorn; /* rx overrun interrupts */
64 u_int32_t ast_rxeol; /* rx eol interrupts */
65 u_int32_t ast_txurn; /* tx underrun interrupts */
72 u_int32_t ast_tx_encap; /* tx encapsulation failed */
73 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
74 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
75 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
76 u_int32_t ast_tx_linear; /* tx linearized to cluster */
77 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
78 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
79 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
80 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
81 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
82 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
83 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
84 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
85 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
86 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
87 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
88 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
89 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
90 u_int32_t ast_tx_protect; /* tx frames with protection */
91 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
92 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
93 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
94 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
95 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
96 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
97 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
98 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
99 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
100 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
102 /* rx PHY error per-code counts */
103 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
104 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
107 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
108 int8_t ast_tx_rssi; /* tx rssi of last ack */
109 int8_t ast_rx_rssi; /* rx rssi from histogram */
110 u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
119 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
120 u_int32_t ast_ant_txswitch;/* tx antenna switches */
122 /* rx frames with antenna */
124 /* tx frames with antenna */
127 u_int32_t ast_tx_raw; /* tx frames through raw api */
128 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
129 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
130 u_int32_t ast_ff_rx; /* fast frames rx'd */
132 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
133 int8_t ast_rx_noise; /* rx noise floor */
134 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
139 u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
140 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
141 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
142 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
145 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
146 u_int32_t ast_rx_halfgi; /* RX half-GI */
147 u_int32_t ast_rx_2040; /* RX 40mhz frame */
148 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
149 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
150 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
152 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
153 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
154 u_int32_t ast_tx_timeout; /* Global TX timeout */
156 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
157 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
158 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
159 u_int32_t ast_tx_swretries; /* software TX retries */
160 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
163 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
168 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
169 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
174 u_int32_t ast_rx_stbc; /* RX STBC frame */
176 u_int32_t ast_tx_ldpc; /* TX LDPC frame */
177 u_int32_t ast_tx_stbc; /* TX STBC frame */
220 * of rix -> net80211 ratecode as part of the update.
282 * per-chain info header be 4-byte aligned.
303 * two bytes so it can be accessed by alignment-strict
317 uint8_t vh_rs_status; /* RX status */
326 uint8_t vh_rx_hwrate; /* hardware RX ratecode */
327 uint8_t vh_rs_flags; /* RX HAL flags */
376 * useful way. So, this will include a two-byte version
377 * value which will force the structure to be 4-byte aligned.
429 /* FreeBSD-specific start at 32 */