160  * XXX TODO: push an aggregate as a single FIFO slot, even though
163  * The TX completion code handles a TX FIFO slot having multiple frames,
182 	    "%s: called; TXQ=%d, fifo.depth=%d, axq_q empty=%d\n",  in ath_tx_edma_push_staging_list()
223 	 * as one FIFO entry.  in ath_tx_edma_push_staging_list()
267 	 * of the FIFO queue.  We don't adjust the aggregate  in ath_tx_edma_push_staging_list()
272 	TAILQ_CONCAT(&txq->fifo.axq_q, &sq, bf_list);  in ath_tx_edma_push_staging_list()
273 	/* Bump total queue tracking in FIFO queue */  in ath_tx_edma_push_staging_list()
274 	txq->fifo.axq_depth += sqdepth;  in ath_tx_edma_push_staging_list()
276 	/* Bump FIFO queue */  in ath_tx_edma_push_staging_list()
279 	    "%s: queued %d packets; depth=%d, fifo depth=%d\n",  in ath_tx_edma_push_staging_list()
280 	    __func__, sqdepth, txq->fifo.axq_depth, txq->axq_fifo_depth);  in ath_tx_edma_push_staging_list()
291 	    txq->fifo.axq_depth);  in ath_tx_edma_push_staging_list()
298  * Push some frames into the TX FIFO if we have space.
307 	    "%s: Q%d: called; fifo.depth=%d, fifo depth=%d, depth=%d, aggr_depth=%d\n",  in ath_edma_tx_fifo_fill()
310 	    txq->fifo.axq_depth,  in ath_edma_tx_fifo_fill()
316 	 * For now, push up to 32 frames per TX FIFO slot.  in ath_edma_tx_fifo_fill()
327 	 * the TX FIFO since we don't want to necessarily  in ath_edma_tx_fifo_fill()
333 	 * It only ungates a single FIFO entry at a time,  in ath_edma_tx_fifo_fill()
335 	 * end of that FIFO entry descriptor list is reached.  in ath_edma_tx_fifo_fill()
337 	 * single TX FIFO entries mean the MAC only sends out  in ath_edma_tx_fifo_fill()
360 	 * FIFO.  in ath_edma_tx_fifo_fill()
363 	    txq->fifo.axq_depth <= TX_BATCH_SIZE) {  in ath_edma_tx_fifo_fill()
368 	 * Aggregate check: if we have less than two FIFO slots  in ath_edma_tx_fifo_fill()
372 	 * has given us aggregate frames and push them into the FIFO  in ath_edma_tx_fifo_fill()
374 	 * a single aggregate in as one FIFO slot.  in ath_edma_tx_fifo_fill()
384 	 * wait until we've finished sending the FIFO.  in ath_edma_tx_fifo_fill()
395  * Re-initialise the DMA FIFO with the current contents of
399  * assumes the FIFO is currently empty.
416 	 * Let's log if the tracked FIFO depth doesn't match  in ath_edma_dma_restart()
423 	 * Walk the FIFO staging list, looking for "head" entries.  in ath_edma_dma_restart()
425 	 * we push the first frame we see into the FIFO and re-mark  in ath_edma_dma_restart()
427 	 * FIFO end, at which point we get ready to push another  in ath_edma_dma_restart()
428 	 * entry into the FIFO.  in ath_edma_dma_restart()
430 	TAILQ_FOREACH(bf, &txq->fifo.axq_q, bf_list) {  in ath_edma_dma_restart()
453 		/* Make sure we're not overflowing the FIFO! */  in ath_edma_dma_restart()
456 			    "%s: Q%d: more frames in the queue; FIFO depth=%d?!\n",  in ath_edma_dma_restart()
474 		 * Set this to be the first buffer in the FIFO  in ath_edma_dma_restart()
476 		 * a FIFO list!  in ath_edma_dma_restart()
480 		/* Push it into the FIFO and bump the FIFO count */  in ath_edma_dma_restart()
498 	DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: FIFO depth was %d, is %d\n",  in ath_edma_dma_restart()
507 		    "%s: Q%d: FIFO depth should be %d, is %d\n",  in ath_edma_dma_restart()
518  * Things are a bit hairy in the EDMA world.  The TX FIFO is only
520  * pushed into the FIFO and what's just sitting in the TX queue,
525  * actual TX FIFO.
550 	 * Finally, call the FIFO schedule routine to schedule some  in ath_edma_xmit_handoff_hw()
551 	 * frames to the FIFO.  in ath_edma_xmit_handoff_hw()
611  * like before, then populate the FIFO from that.  Since the
612  * EDMA hardware has 8 FIFO slots per TXQ, this ensures that
719 	 * If reset type is noloss, the TX FIFO needs to be serviced  in ath_edma_tx_drain()
749 	/* XXX dump out the TX completion FIFO contents */  in ath_edma_tx_drain()
879 		bf = ATH_TXQ_FIRST(&txq->fifo);  in ath_edma_tx_processq()
916 		ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);  in ath_edma_tx_processq()
921 		 * If this was the end of a FIFO set, decrement FIFO depth  in ath_edma_tx_processq()
927 		 * If this isn't the final buffer in a FIFO set, mark  in ath_edma_tx_processq()
933 		DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: FIFO depth is now %d (%d)\n",  in ath_edma_tx_processq()
937 		    txq->fifo.axq_depth);  in ath_edma_tx_processq()
939 		/* XXX assert FIFO depth >= 0 */  in ath_edma_tx_processq()
944 		 * end buffer in this FIFO, we don't need a holding  in ath_edma_tx_processq()
960 		 * FIFO doesn't have this information.  So here we  in ath_edma_tx_processq()
1025 	 * XXX It's inefficient to do this if the FIFO queue is full,  in ath_edma_tx_processq()
1030 		/* Attempt to schedule more hardware frames to the TX FIFO */  in ath_edma_tx_processq()