Lines Matching +full:revision +full:- +full:id1
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
171 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
172 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
173 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
174 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
175 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
176 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
177 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
178 #define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */
205 #define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */
206 #define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */
207 #define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */
208 #define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */
209 #define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */
210 #define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */
211 #define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */
212 #define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */
213 #define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */
214 #define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */
219 /* MAC DCU-global IFS settings */
239 #define AR_SREV 0x4020 /* Silicon Revision register */
253 #define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */
254 #define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */
257 #define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */
258 #define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */
331 #define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */
341 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
348 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
375 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
413 * and IMR_P is non-zero. The secondary interrupt mask/status
429 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
432 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
449 #define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
451 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
454 #define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
456 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
459 #define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
472 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
473 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
475 #define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
499 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
502 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
517 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */
519 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */
522 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */
524 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */
527 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
547 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
548 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
549 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
551 #define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
555 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
575 /* bits 25-31 are reserved */
582 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
615 #define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
669 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
673 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
693 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
766 #define AR_SREV_REVISION 0x0000000F /* Mask for Chip revision level */
767 #define AR_SREV_REVISION_MIN 0 /* lowest revision level */
768 #define AR_SREV_REVISION_MAX 0xF /* highest revision level */
810 #define AR_RAD5112_SREV_2_0 0x35 /* AR5112 Revision 2.0 */
811 #define AR_RAD5112_SREV_2_1 0x36 /* AR5112 Revision 2.1 */
813 #define AR_RAD2112_SREV_2_0 0x45 /* AR2112 Revision 2.0 */
814 #define AR_RAD2112_SREV_2_1 0x46 /* AR2112 Revision 2.1 */
855 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
857 self-generated frames */
867 self-generated frames */
869 #define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */
880 #define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */
882 #define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */
926 #define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero
978 #define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */
980 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
981 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
982 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
983 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
984 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
994 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
995 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */